1 /* 2 * QEMU USB EHCI Emulation 3 * 4 * Copyright(c) 2008 Emutex Ltd. (address@hidden) 5 * Copyright(c) 2011-2012 Red Hat, Inc. 6 * 7 * Red Hat Authors: 8 * Gerd Hoffmann <kraxel@redhat.com> 9 * Hans de Goede <hdegoede@redhat.com> 10 * 11 * EHCI project was started by Mark Burkley, with contributions by 12 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf, 13 * Jan Kiszka and Vincent Palatin contributed bugfixes. 14 * 15 * 16 * This library is free software; you can redistribute it and/or 17 * modify it under the terms of the GNU Lesser General Public 18 * License as published by the Free Software Foundation; either 19 * version 2 of the License, or(at your option) any later version. 20 * 21 * This library is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 24 * Lesser General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; if not, see <http://www.gnu.org/licenses/>. 28 */ 29 30 #include "hw/hw.h" 31 #include "qemu-timer.h" 32 #include "hw/usb.h" 33 #include "hw/pci.h" 34 #include "monitor.h" 35 #include "trace.h" 36 #include "dma.h" 37 38 #define EHCI_DEBUG 0 39 40 #if EHCI_DEBUG 41 #define DPRINTF printf 42 #else 43 #define DPRINTF(...) 44 #endif 45 46 /* internal processing - reset HC to try and recover */ 47 #define USB_RET_PROCERR (-99) 48 49 #define MMIO_SIZE 0x1000 50 51 /* Capability Registers Base Address - section 2.2 */ 52 #define CAPREGBASE 0x0000 53 #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved 54 #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version # 55 #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params 56 #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params 57 #define EECP HCCPARAMS + 1 58 #define HCSPPORTROUTE1 CAPREGBASE + 0x000c 59 #define HCSPPORTROUTE2 CAPREGBASE + 0x0010 60 61 #define OPREGBASE 0x0020 // Operational Registers Base Address 62 63 #define USBCMD OPREGBASE + 0x0000 64 #define USBCMD_RUNSTOP (1 << 0) // run / Stop 65 #define USBCMD_HCRESET (1 << 1) // HC Reset 66 #define USBCMD_FLS (3 << 2) // Frame List Size 67 #define USBCMD_FLS_SH 2 // Frame List Size Shift 68 #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable 69 #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable 70 #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell 71 #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset 72 #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count 73 #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable 74 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control 75 #define USBCMD_ITC_SH 16 // Int Threshold Control Shift 76 77 #define USBSTS OPREGBASE + 0x0004 78 #define USBSTS_RO_MASK 0x0000003f 79 #define USBSTS_INT (1 << 0) // USB Interrupt 80 #define USBSTS_ERRINT (1 << 1) // Error Interrupt 81 #define USBSTS_PCD (1 << 2) // Port Change Detect 82 #define USBSTS_FLR (1 << 3) // Frame List Rollover 83 #define USBSTS_HSE (1 << 4) // Host System Error 84 #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance 85 #define USBSTS_HALT (1 << 12) // HC Halted 86 #define USBSTS_REC (1 << 13) // Reclamation 87 #define USBSTS_PSS (1 << 14) // Periodic Schedule Status 88 #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status 89 90 /* 91 * Interrupt enable bits correspond to the interrupt active bits in USBSTS 92 * so no need to redefine here. 93 */ 94 #define USBINTR OPREGBASE + 0x0008 95 #define USBINTR_MASK 0x0000003f 96 97 #define FRINDEX OPREGBASE + 0x000c 98 #define CTRLDSSEGMENT OPREGBASE + 0x0010 99 #define PERIODICLISTBASE OPREGBASE + 0x0014 100 #define ASYNCLISTADDR OPREGBASE + 0x0018 101 #define ASYNCLISTADDR_MASK 0xffffffe0 102 103 #define CONFIGFLAG OPREGBASE + 0x0040 104 105 #define PORTSC (OPREGBASE + 0x0044) 106 #define PORTSC_BEGIN PORTSC 107 #define PORTSC_END (PORTSC + 4 * NB_PORTS) 108 /* 109 * Bits that are reserved or are read-only are masked out of values 110 * written to us by software 111 */ 112 #define PORTSC_RO_MASK 0x007001c0 113 #define PORTSC_RWC_MASK 0x0000002a 114 #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable 115 #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable 116 #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable 117 #define PORTSC_PTC (15 << 16) // Port Test Control 118 #define PORTSC_PTC_SH 16 // Port Test Control shift 119 #define PORTSC_PIC (3 << 14) // Port Indicator Control 120 #define PORTSC_PIC_SH 14 // Port Indicator Control Shift 121 #define PORTSC_POWNER (1 << 13) // Port Owner 122 #define PORTSC_PPOWER (1 << 12) // Port Power 123 #define PORTSC_LINESTAT (3 << 10) // Port Line Status 124 #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift 125 #define PORTSC_PRESET (1 << 8) // Port Reset 126 #define PORTSC_SUSPEND (1 << 7) // Port Suspend 127 #define PORTSC_FPRES (1 << 6) // Force Port Resume 128 #define PORTSC_OCC (1 << 5) // Over Current Change 129 #define PORTSC_OCA (1 << 4) // Over Current Active 130 #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change 131 #define PORTSC_PED (1 << 2) // Port Enable/Disable 132 #define PORTSC_CSC (1 << 1) // Connect Status Change 133 #define PORTSC_CONNECT (1 << 0) // Current Connect Status 134 135 #define FRAME_TIMER_FREQ 1000 136 #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ) 137 138 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints 139 #define NB_PORTS 6 // Number of downstream ports 140 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction 141 #define MAX_QH 100 // Max allowable queue heads in a chain 142 143 /* Internal periodic / asynchronous schedule state machine states 144 */ 145 typedef enum { 146 EST_INACTIVE = 1000, 147 EST_ACTIVE, 148 EST_EXECUTING, 149 EST_SLEEPING, 150 /* The following states are internal to the state machine function 151 */ 152 EST_WAITLISTHEAD, 153 EST_FETCHENTRY, 154 EST_FETCHQH, 155 EST_FETCHITD, 156 EST_FETCHSITD, 157 EST_ADVANCEQUEUE, 158 EST_FETCHQTD, 159 EST_EXECUTE, 160 EST_WRITEBACK, 161 EST_HORIZONTALQH 162 } EHCI_STATES; 163 164 /* macros for accessing fields within next link pointer entry */ 165 #define NLPTR_GET(x) ((x) & 0xffffffe0) 166 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3) 167 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid 168 169 /* link pointer types */ 170 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor 171 #define NLPTR_TYPE_QH 1 // queue head 172 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor 173 #define NLPTR_TYPE_FSTN 3 // frame span traversal node 174 175 176 /* EHCI spec version 1.0 Section 3.3 177 */ 178 typedef struct EHCIitd { 179 uint32_t next; 180 181 uint32_t transact[8]; 182 #define ITD_XACT_ACTIVE (1 << 31) 183 #define ITD_XACT_DBERROR (1 << 30) 184 #define ITD_XACT_BABBLE (1 << 29) 185 #define ITD_XACT_XACTERR (1 << 28) 186 #define ITD_XACT_LENGTH_MASK 0x0fff0000 187 #define ITD_XACT_LENGTH_SH 16 188 #define ITD_XACT_IOC (1 << 15) 189 #define ITD_XACT_PGSEL_MASK 0x00007000 190 #define ITD_XACT_PGSEL_SH 12 191 #define ITD_XACT_OFFSET_MASK 0x00000fff 192 193 uint32_t bufptr[7]; 194 #define ITD_BUFPTR_MASK 0xfffff000 195 #define ITD_BUFPTR_SH 12 196 #define ITD_BUFPTR_EP_MASK 0x00000f00 197 #define ITD_BUFPTR_EP_SH 8 198 #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f 199 #define ITD_BUFPTR_DEVADDR_SH 0 200 #define ITD_BUFPTR_DIRECTION (1 << 11) 201 #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff 202 #define ITD_BUFPTR_MAXPKT_SH 0 203 #define ITD_BUFPTR_MULT_MASK 0x00000003 204 #define ITD_BUFPTR_MULT_SH 0 205 } EHCIitd; 206 207 /* EHCI spec version 1.0 Section 3.4 208 */ 209 typedef struct EHCIsitd { 210 uint32_t next; // Standard next link pointer 211 uint32_t epchar; 212 #define SITD_EPCHAR_IO (1 << 31) 213 #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000 214 #define SITD_EPCHAR_PORTNUM_SH 24 215 #define SITD_EPCHAR_HUBADD_MASK 0x007f0000 216 #define SITD_EPCHAR_HUBADDR_SH 16 217 #define SITD_EPCHAR_EPNUM_MASK 0x00000f00 218 #define SITD_EPCHAR_EPNUM_SH 8 219 #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f 220 221 uint32_t uframe; 222 #define SITD_UFRAME_CMASK_MASK 0x0000ff00 223 #define SITD_UFRAME_CMASK_SH 8 224 #define SITD_UFRAME_SMASK_MASK 0x000000ff 225 226 uint32_t results; 227 #define SITD_RESULTS_IOC (1 << 31) 228 #define SITD_RESULTS_PGSEL (1 << 30) 229 #define SITD_RESULTS_TBYTES_MASK 0x03ff0000 230 #define SITD_RESULTS_TYBYTES_SH 16 231 #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00 232 #define SITD_RESULTS_CPROGMASK_SH 8 233 #define SITD_RESULTS_ACTIVE (1 << 7) 234 #define SITD_RESULTS_ERR (1 << 6) 235 #define SITD_RESULTS_DBERR (1 << 5) 236 #define SITD_RESULTS_BABBLE (1 << 4) 237 #define SITD_RESULTS_XACTERR (1 << 3) 238 #define SITD_RESULTS_MISSEDUF (1 << 2) 239 #define SITD_RESULTS_SPLITXSTATE (1 << 1) 240 241 uint32_t bufptr[2]; 242 #define SITD_BUFPTR_MASK 0xfffff000 243 #define SITD_BUFPTR_CURROFF_MASK 0x00000fff 244 #define SITD_BUFPTR_TPOS_MASK 0x00000018 245 #define SITD_BUFPTR_TPOS_SH 3 246 #define SITD_BUFPTR_TCNT_MASK 0x00000007 247 248 uint32_t backptr; // Standard next link pointer 249 } EHCIsitd; 250 251 /* EHCI spec version 1.0 Section 3.5 252 */ 253 typedef struct EHCIqtd { 254 uint32_t next; // Standard next link pointer 255 uint32_t altnext; // Standard next link pointer 256 uint32_t token; 257 #define QTD_TOKEN_DTOGGLE (1 << 31) 258 #define QTD_TOKEN_TBYTES_MASK 0x7fff0000 259 #define QTD_TOKEN_TBYTES_SH 16 260 #define QTD_TOKEN_IOC (1 << 15) 261 #define QTD_TOKEN_CPAGE_MASK 0x00007000 262 #define QTD_TOKEN_CPAGE_SH 12 263 #define QTD_TOKEN_CERR_MASK 0x00000c00 264 #define QTD_TOKEN_CERR_SH 10 265 #define QTD_TOKEN_PID_MASK 0x00000300 266 #define QTD_TOKEN_PID_SH 8 267 #define QTD_TOKEN_ACTIVE (1 << 7) 268 #define QTD_TOKEN_HALT (1 << 6) 269 #define QTD_TOKEN_DBERR (1 << 5) 270 #define QTD_TOKEN_BABBLE (1 << 4) 271 #define QTD_TOKEN_XACTERR (1 << 3) 272 #define QTD_TOKEN_MISSEDUF (1 << 2) 273 #define QTD_TOKEN_SPLITXSTATE (1 << 1) 274 #define QTD_TOKEN_PING (1 << 0) 275 276 uint32_t bufptr[5]; // Standard buffer pointer 277 #define QTD_BUFPTR_MASK 0xfffff000 278 #define QTD_BUFPTR_SH 12 279 } EHCIqtd; 280 281 /* EHCI spec version 1.0 Section 3.6 282 */ 283 typedef struct EHCIqh { 284 uint32_t next; // Standard next link pointer 285 286 /* endpoint characteristics */ 287 uint32_t epchar; 288 #define QH_EPCHAR_RL_MASK 0xf0000000 289 #define QH_EPCHAR_RL_SH 28 290 #define QH_EPCHAR_C (1 << 27) 291 #define QH_EPCHAR_MPLEN_MASK 0x07FF0000 292 #define QH_EPCHAR_MPLEN_SH 16 293 #define QH_EPCHAR_H (1 << 15) 294 #define QH_EPCHAR_DTC (1 << 14) 295 #define QH_EPCHAR_EPS_MASK 0x00003000 296 #define QH_EPCHAR_EPS_SH 12 297 #define EHCI_QH_EPS_FULL 0 298 #define EHCI_QH_EPS_LOW 1 299 #define EHCI_QH_EPS_HIGH 2 300 #define EHCI_QH_EPS_RESERVED 3 301 302 #define QH_EPCHAR_EP_MASK 0x00000f00 303 #define QH_EPCHAR_EP_SH 8 304 #define QH_EPCHAR_I (1 << 7) 305 #define QH_EPCHAR_DEVADDR_MASK 0x0000007f 306 #define QH_EPCHAR_DEVADDR_SH 0 307 308 /* endpoint capabilities */ 309 uint32_t epcap; 310 #define QH_EPCAP_MULT_MASK 0xc0000000 311 #define QH_EPCAP_MULT_SH 30 312 #define QH_EPCAP_PORTNUM_MASK 0x3f800000 313 #define QH_EPCAP_PORTNUM_SH 23 314 #define QH_EPCAP_HUBADDR_MASK 0x007f0000 315 #define QH_EPCAP_HUBADDR_SH 16 316 #define QH_EPCAP_CMASK_MASK 0x0000ff00 317 #define QH_EPCAP_CMASK_SH 8 318 #define QH_EPCAP_SMASK_MASK 0x000000ff 319 #define QH_EPCAP_SMASK_SH 0 320 321 uint32_t current_qtd; // Standard next link pointer 322 uint32_t next_qtd; // Standard next link pointer 323 uint32_t altnext_qtd; 324 #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e 325 #define QH_ALTNEXT_NAKCNT_SH 1 326 327 uint32_t token; // Same as QTD token 328 uint32_t bufptr[5]; // Standard buffer pointer 329 #define BUFPTR_CPROGMASK_MASK 0x000000ff 330 #define BUFPTR_FRAMETAG_MASK 0x0000001f 331 #define BUFPTR_SBYTES_MASK 0x00000fe0 332 #define BUFPTR_SBYTES_SH 5 333 } EHCIqh; 334 335 /* EHCI spec version 1.0 Section 3.7 336 */ 337 typedef struct EHCIfstn { 338 uint32_t next; // Standard next link pointer 339 uint32_t backptr; // Standard next link pointer 340 } EHCIfstn; 341 342 typedef struct EHCIPacket EHCIPacket; 343 typedef struct EHCIQueue EHCIQueue; 344 typedef struct EHCIState EHCIState; 345 346 enum async_state { 347 EHCI_ASYNC_NONE = 0, 348 EHCI_ASYNC_INITIALIZED, 349 EHCI_ASYNC_INFLIGHT, 350 EHCI_ASYNC_FINISHED, 351 }; 352 353 struct EHCIPacket { 354 EHCIQueue *queue; 355 QTAILQ_ENTRY(EHCIPacket) next; 356 357 EHCIqtd qtd; /* copy of current QTD (being worked on) */ 358 uint32_t qtdaddr; /* address QTD read from */ 359 360 USBPacket packet; 361 QEMUSGList sgl; 362 int pid; 363 uint32_t tbytes; 364 enum async_state async; 365 int usb_status; 366 }; 367 368 struct EHCIQueue { 369 EHCIState *ehci; 370 QTAILQ_ENTRY(EHCIQueue) next; 371 uint32_t seen; 372 uint64_t ts; 373 int async; 374 375 /* cached data from guest - needs to be flushed 376 * when guest removes an entry (doorbell, handshake sequence) 377 */ 378 EHCIqh qh; /* copy of current QH (being worked on) */ 379 uint32_t qhaddr; /* address QH read from */ 380 uint32_t qtdaddr; /* address QTD read from */ 381 USBDevice *dev; 382 QTAILQ_HEAD(, EHCIPacket) packets; 383 }; 384 385 typedef QTAILQ_HEAD(EHCIQueueHead, EHCIQueue) EHCIQueueHead; 386 387 struct EHCIState { 388 PCIDevice dev; 389 USBBus bus; 390 qemu_irq irq; 391 MemoryRegion mem; 392 int companion_count; 393 394 /* properties */ 395 uint32_t maxframes; 396 397 /* 398 * EHCI spec version 1.0 Section 2.3 399 * Host Controller Operational Registers 400 */ 401 union { 402 uint8_t mmio[MMIO_SIZE]; 403 struct { 404 uint8_t cap[OPREGBASE]; 405 uint32_t usbcmd; 406 uint32_t usbsts; 407 uint32_t usbintr; 408 uint32_t frindex; 409 uint32_t ctrldssegment; 410 uint32_t periodiclistbase; 411 uint32_t asynclistaddr; 412 uint32_t notused[9]; 413 uint32_t configflag; 414 uint32_t portsc[NB_PORTS]; 415 }; 416 }; 417 418 /* 419 * Internal states, shadow registers, etc 420 */ 421 QEMUTimer *frame_timer; 422 QEMUBH *async_bh; 423 uint32_t astate; /* Current state in asynchronous schedule */ 424 uint32_t pstate; /* Current state in periodic schedule */ 425 USBPort ports[NB_PORTS]; 426 USBPort *companion_ports[NB_PORTS]; 427 uint32_t usbsts_pending; 428 uint32_t usbsts_frindex; 429 EHCIQueueHead aqueues; 430 EHCIQueueHead pqueues; 431 432 /* which address to look at next */ 433 uint32_t a_fetch_addr; 434 uint32_t p_fetch_addr; 435 436 USBPacket ipacket; 437 QEMUSGList isgl; 438 439 uint64_t last_run_ns; 440 uint32_t async_stepdown; 441 }; 442 443 #define SET_LAST_RUN_CLOCK(s) \ 444 (s)->last_run_ns = qemu_get_clock_ns(vm_clock); 445 446 /* nifty macros from Arnon's EHCI version */ 447 #define get_field(data, field) \ 448 (((data) & field##_MASK) >> field##_SH) 449 450 #define set_field(data, newval, field) do { \ 451 uint32_t val = *data; \ 452 val &= ~ field##_MASK; \ 453 val |= ((newval) << field##_SH) & field##_MASK; \ 454 *data = val; \ 455 } while(0) 456 457 static const char *ehci_state_names[] = { 458 [EST_INACTIVE] = "INACTIVE", 459 [EST_ACTIVE] = "ACTIVE", 460 [EST_EXECUTING] = "EXECUTING", 461 [EST_SLEEPING] = "SLEEPING", 462 [EST_WAITLISTHEAD] = "WAITLISTHEAD", 463 [EST_FETCHENTRY] = "FETCH ENTRY", 464 [EST_FETCHQH] = "FETCH QH", 465 [EST_FETCHITD] = "FETCH ITD", 466 [EST_ADVANCEQUEUE] = "ADVANCEQUEUE", 467 [EST_FETCHQTD] = "FETCH QTD", 468 [EST_EXECUTE] = "EXECUTE", 469 [EST_WRITEBACK] = "WRITEBACK", 470 [EST_HORIZONTALQH] = "HORIZONTALQH", 471 }; 472 473 static const char *ehci_mmio_names[] = { 474 [CAPLENGTH] = "CAPLENGTH", 475 [HCIVERSION] = "HCIVERSION", 476 [HCSPARAMS] = "HCSPARAMS", 477 [HCCPARAMS] = "HCCPARAMS", 478 [USBCMD] = "USBCMD", 479 [USBSTS] = "USBSTS", 480 [USBINTR] = "USBINTR", 481 [FRINDEX] = "FRINDEX", 482 [PERIODICLISTBASE] = "P-LIST BASE", 483 [ASYNCLISTADDR] = "A-LIST ADDR", 484 [PORTSC_BEGIN] = "PORTSC #0", 485 [PORTSC_BEGIN + 4] = "PORTSC #1", 486 [PORTSC_BEGIN + 8] = "PORTSC #2", 487 [PORTSC_BEGIN + 12] = "PORTSC #3", 488 [PORTSC_BEGIN + 16] = "PORTSC #4", 489 [PORTSC_BEGIN + 20] = "PORTSC #5", 490 [CONFIGFLAG] = "CONFIGFLAG", 491 }; 492 493 static int ehci_state_executing(EHCIQueue *q); 494 static int ehci_state_writeback(EHCIQueue *q); 495 496 static const char *nr2str(const char **n, size_t len, uint32_t nr) 497 { 498 if (nr < len && n[nr] != NULL) { 499 return n[nr]; 500 } else { 501 return "unknown"; 502 } 503 } 504 505 static const char *state2str(uint32_t state) 506 { 507 return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state); 508 } 509 510 static const char *addr2str(target_phys_addr_t addr) 511 { 512 return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr); 513 } 514 515 static void ehci_trace_usbsts(uint32_t mask, int state) 516 { 517 /* interrupts */ 518 if (mask & USBSTS_INT) { 519 trace_usb_ehci_usbsts("INT", state); 520 } 521 if (mask & USBSTS_ERRINT) { 522 trace_usb_ehci_usbsts("ERRINT", state); 523 } 524 if (mask & USBSTS_PCD) { 525 trace_usb_ehci_usbsts("PCD", state); 526 } 527 if (mask & USBSTS_FLR) { 528 trace_usb_ehci_usbsts("FLR", state); 529 } 530 if (mask & USBSTS_HSE) { 531 trace_usb_ehci_usbsts("HSE", state); 532 } 533 if (mask & USBSTS_IAA) { 534 trace_usb_ehci_usbsts("IAA", state); 535 } 536 537 /* status */ 538 if (mask & USBSTS_HALT) { 539 trace_usb_ehci_usbsts("HALT", state); 540 } 541 if (mask & USBSTS_REC) { 542 trace_usb_ehci_usbsts("REC", state); 543 } 544 if (mask & USBSTS_PSS) { 545 trace_usb_ehci_usbsts("PSS", state); 546 } 547 if (mask & USBSTS_ASS) { 548 trace_usb_ehci_usbsts("ASS", state); 549 } 550 } 551 552 static inline void ehci_set_usbsts(EHCIState *s, int mask) 553 { 554 if ((s->usbsts & mask) == mask) { 555 return; 556 } 557 ehci_trace_usbsts(mask, 1); 558 s->usbsts |= mask; 559 } 560 561 static inline void ehci_clear_usbsts(EHCIState *s, int mask) 562 { 563 if ((s->usbsts & mask) == 0) { 564 return; 565 } 566 ehci_trace_usbsts(mask, 0); 567 s->usbsts &= ~mask; 568 } 569 570 /* update irq line */ 571 static inline void ehci_update_irq(EHCIState *s) 572 { 573 int level = 0; 574 575 if ((s->usbsts & USBINTR_MASK) & s->usbintr) { 576 level = 1; 577 } 578 579 trace_usb_ehci_irq(level, s->frindex, s->usbsts, s->usbintr); 580 qemu_set_irq(s->irq, level); 581 } 582 583 /* flag interrupt condition */ 584 static inline void ehci_raise_irq(EHCIState *s, int intr) 585 { 586 if (intr & (USBSTS_PCD | USBSTS_FLR | USBSTS_HSE)) { 587 s->usbsts |= intr; 588 ehci_update_irq(s); 589 } else { 590 s->usbsts_pending |= intr; 591 } 592 } 593 594 /* 595 * Commit pending interrupts (added via ehci_raise_irq), 596 * at the rate allowed by "Interrupt Threshold Control". 597 */ 598 static inline void ehci_commit_irq(EHCIState *s) 599 { 600 uint32_t itc; 601 602 if (!s->usbsts_pending) { 603 return; 604 } 605 if (s->usbsts_frindex > s->frindex) { 606 return; 607 } 608 609 itc = (s->usbcmd >> 16) & 0xff; 610 s->usbsts |= s->usbsts_pending; 611 s->usbsts_pending = 0; 612 s->usbsts_frindex = s->frindex + itc; 613 ehci_update_irq(s); 614 } 615 616 static void ehci_update_halt(EHCIState *s) 617 { 618 if (s->usbcmd & USBCMD_RUNSTOP) { 619 ehci_clear_usbsts(s, USBSTS_HALT); 620 } else { 621 if (s->astate == EST_INACTIVE && s->pstate == EST_INACTIVE) { 622 ehci_set_usbsts(s, USBSTS_HALT); 623 } 624 } 625 } 626 627 static void ehci_set_state(EHCIState *s, int async, int state) 628 { 629 if (async) { 630 trace_usb_ehci_state("async", state2str(state)); 631 s->astate = state; 632 if (s->astate == EST_INACTIVE) { 633 ehci_clear_usbsts(s, USBSTS_ASS); 634 ehci_update_halt(s); 635 } else { 636 ehci_set_usbsts(s, USBSTS_ASS); 637 } 638 } else { 639 trace_usb_ehci_state("periodic", state2str(state)); 640 s->pstate = state; 641 if (s->pstate == EST_INACTIVE) { 642 ehci_clear_usbsts(s, USBSTS_PSS); 643 ehci_update_halt(s); 644 } else { 645 ehci_set_usbsts(s, USBSTS_PSS); 646 } 647 } 648 } 649 650 static int ehci_get_state(EHCIState *s, int async) 651 { 652 return async ? s->astate : s->pstate; 653 } 654 655 static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr) 656 { 657 if (async) { 658 s->a_fetch_addr = addr; 659 } else { 660 s->p_fetch_addr = addr; 661 } 662 } 663 664 static int ehci_get_fetch_addr(EHCIState *s, int async) 665 { 666 return async ? s->a_fetch_addr : s->p_fetch_addr; 667 } 668 669 static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh) 670 { 671 /* need three here due to argument count limits */ 672 trace_usb_ehci_qh_ptrs(q, addr, qh->next, 673 qh->current_qtd, qh->next_qtd, qh->altnext_qtd); 674 trace_usb_ehci_qh_fields(addr, 675 get_field(qh->epchar, QH_EPCHAR_RL), 676 get_field(qh->epchar, QH_EPCHAR_MPLEN), 677 get_field(qh->epchar, QH_EPCHAR_EPS), 678 get_field(qh->epchar, QH_EPCHAR_EP), 679 get_field(qh->epchar, QH_EPCHAR_DEVADDR)); 680 trace_usb_ehci_qh_bits(addr, 681 (bool)(qh->epchar & QH_EPCHAR_C), 682 (bool)(qh->epchar & QH_EPCHAR_H), 683 (bool)(qh->epchar & QH_EPCHAR_DTC), 684 (bool)(qh->epchar & QH_EPCHAR_I)); 685 } 686 687 static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd) 688 { 689 /* need three here due to argument count limits */ 690 trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext); 691 trace_usb_ehci_qtd_fields(addr, 692 get_field(qtd->token, QTD_TOKEN_TBYTES), 693 get_field(qtd->token, QTD_TOKEN_CPAGE), 694 get_field(qtd->token, QTD_TOKEN_CERR), 695 get_field(qtd->token, QTD_TOKEN_PID)); 696 trace_usb_ehci_qtd_bits(addr, 697 (bool)(qtd->token & QTD_TOKEN_IOC), 698 (bool)(qtd->token & QTD_TOKEN_ACTIVE), 699 (bool)(qtd->token & QTD_TOKEN_HALT), 700 (bool)(qtd->token & QTD_TOKEN_BABBLE), 701 (bool)(qtd->token & QTD_TOKEN_XACTERR)); 702 } 703 704 static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd) 705 { 706 trace_usb_ehci_itd(addr, itd->next, 707 get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT), 708 get_field(itd->bufptr[2], ITD_BUFPTR_MULT), 709 get_field(itd->bufptr[0], ITD_BUFPTR_EP), 710 get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR)); 711 } 712 713 static void ehci_trace_sitd(EHCIState *s, target_phys_addr_t addr, 714 EHCIsitd *sitd) 715 { 716 trace_usb_ehci_sitd(addr, sitd->next, 717 (bool)(sitd->results & SITD_RESULTS_ACTIVE)); 718 } 719 720 static void ehci_trace_guest_bug(EHCIState *s, const char *message) 721 { 722 trace_usb_ehci_guest_bug(message); 723 fprintf(stderr, "ehci warning: %s\n", message); 724 } 725 726 static inline bool ehci_enabled(EHCIState *s) 727 { 728 return s->usbcmd & USBCMD_RUNSTOP; 729 } 730 731 static inline bool ehci_async_enabled(EHCIState *s) 732 { 733 return ehci_enabled(s) && (s->usbcmd & USBCMD_ASE); 734 } 735 736 static inline bool ehci_periodic_enabled(EHCIState *s) 737 { 738 return ehci_enabled(s) && (s->usbcmd & USBCMD_PSE); 739 } 740 741 /* packet management */ 742 743 static EHCIPacket *ehci_alloc_packet(EHCIQueue *q) 744 { 745 EHCIPacket *p; 746 747 p = g_new0(EHCIPacket, 1); 748 p->queue = q; 749 usb_packet_init(&p->packet); 750 QTAILQ_INSERT_TAIL(&q->packets, p, next); 751 trace_usb_ehci_packet_action(p->queue, p, "alloc"); 752 return p; 753 } 754 755 static void ehci_free_packet(EHCIPacket *p) 756 { 757 if (p->async == EHCI_ASYNC_FINISHED) { 758 int state = ehci_get_state(p->queue->ehci, p->queue->async); 759 /* This is a normal, but rare condition (cancel racing completion) */ 760 fprintf(stderr, "EHCI: Warning packet completed but not processed\n"); 761 ehci_state_executing(p->queue); 762 ehci_state_writeback(p->queue); 763 ehci_set_state(p->queue->ehci, p->queue->async, state); 764 /* state_writeback recurses into us with async == EHCI_ASYNC_NONE!! */ 765 return; 766 } 767 trace_usb_ehci_packet_action(p->queue, p, "free"); 768 if (p->async == EHCI_ASYNC_INITIALIZED) { 769 usb_packet_unmap(&p->packet, &p->sgl); 770 qemu_sglist_destroy(&p->sgl); 771 } 772 if (p->async == EHCI_ASYNC_INFLIGHT) { 773 usb_cancel_packet(&p->packet); 774 usb_packet_unmap(&p->packet, &p->sgl); 775 qemu_sglist_destroy(&p->sgl); 776 } 777 QTAILQ_REMOVE(&p->queue->packets, p, next); 778 usb_packet_cleanup(&p->packet); 779 g_free(p); 780 } 781 782 /* queue management */ 783 784 static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, uint32_t addr, int async) 785 { 786 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; 787 EHCIQueue *q; 788 789 q = g_malloc0(sizeof(*q)); 790 q->ehci = ehci; 791 q->qhaddr = addr; 792 q->async = async; 793 QTAILQ_INIT(&q->packets); 794 QTAILQ_INSERT_HEAD(head, q, next); 795 trace_usb_ehci_queue_action(q, "alloc"); 796 return q; 797 } 798 799 static int ehci_cancel_queue(EHCIQueue *q) 800 { 801 EHCIPacket *p; 802 int packets = 0; 803 804 p = QTAILQ_FIRST(&q->packets); 805 if (p == NULL) { 806 return 0; 807 } 808 809 trace_usb_ehci_queue_action(q, "cancel"); 810 do { 811 ehci_free_packet(p); 812 packets++; 813 } while ((p = QTAILQ_FIRST(&q->packets)) != NULL); 814 return packets; 815 } 816 817 static int ehci_reset_queue(EHCIQueue *q) 818 { 819 int packets; 820 821 trace_usb_ehci_queue_action(q, "reset"); 822 packets = ehci_cancel_queue(q); 823 q->dev = NULL; 824 q->qtdaddr = 0; 825 return packets; 826 } 827 828 static void ehci_free_queue(EHCIQueue *q, const char *warn) 829 { 830 EHCIQueueHead *head = q->async ? &q->ehci->aqueues : &q->ehci->pqueues; 831 int cancelled; 832 833 trace_usb_ehci_queue_action(q, "free"); 834 cancelled = ehci_cancel_queue(q); 835 if (warn && cancelled > 0) { 836 ehci_trace_guest_bug(q->ehci, warn); 837 } 838 QTAILQ_REMOVE(head, q, next); 839 g_free(q); 840 } 841 842 static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr, 843 int async) 844 { 845 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; 846 EHCIQueue *q; 847 848 QTAILQ_FOREACH(q, head, next) { 849 if (addr == q->qhaddr) { 850 return q; 851 } 852 } 853 return NULL; 854 } 855 856 static void ehci_queues_rip_unused(EHCIState *ehci, int async, int flush) 857 { 858 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; 859 const char *warn = (async && !flush) ? "guest unlinked busy QH" : NULL; 860 uint64_t maxage = FRAME_TIMER_NS * ehci->maxframes * 4; 861 EHCIQueue *q, *tmp; 862 863 QTAILQ_FOREACH_SAFE(q, head, next, tmp) { 864 if (q->seen) { 865 q->seen = 0; 866 q->ts = ehci->last_run_ns; 867 continue; 868 } 869 if (!flush && ehci->last_run_ns < q->ts + maxage) { 870 continue; 871 } 872 ehci_free_queue(q, warn); 873 } 874 } 875 876 static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev, int async) 877 { 878 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; 879 EHCIQueue *q, *tmp; 880 881 QTAILQ_FOREACH_SAFE(q, head, next, tmp) { 882 if (q->dev != dev) { 883 continue; 884 } 885 ehci_free_queue(q, NULL); 886 } 887 } 888 889 static void ehci_queues_rip_all(EHCIState *ehci, int async) 890 { 891 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; 892 const char *warn = async ? "guest stopped busy async schedule" : NULL; 893 EHCIQueue *q, *tmp; 894 895 QTAILQ_FOREACH_SAFE(q, head, next, tmp) { 896 ehci_free_queue(q, warn); 897 } 898 } 899 900 /* Attach or detach a device on root hub */ 901 902 static void ehci_attach(USBPort *port) 903 { 904 EHCIState *s = port->opaque; 905 uint32_t *portsc = &s->portsc[port->index]; 906 const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci"; 907 908 trace_usb_ehci_port_attach(port->index, owner, port->dev->product_desc); 909 910 if (*portsc & PORTSC_POWNER) { 911 USBPort *companion = s->companion_ports[port->index]; 912 companion->dev = port->dev; 913 companion->ops->attach(companion); 914 return; 915 } 916 917 *portsc |= PORTSC_CONNECT; 918 *portsc |= PORTSC_CSC; 919 920 ehci_raise_irq(s, USBSTS_PCD); 921 ehci_commit_irq(s); 922 } 923 924 static void ehci_detach(USBPort *port) 925 { 926 EHCIState *s = port->opaque; 927 uint32_t *portsc = &s->portsc[port->index]; 928 const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci"; 929 930 trace_usb_ehci_port_detach(port->index, owner); 931 932 if (*portsc & PORTSC_POWNER) { 933 USBPort *companion = s->companion_ports[port->index]; 934 companion->ops->detach(companion); 935 companion->dev = NULL; 936 /* 937 * EHCI spec 4.2.2: "When a disconnect occurs... On the event, 938 * the port ownership is returned immediately to the EHCI controller." 939 */ 940 *portsc &= ~PORTSC_POWNER; 941 return; 942 } 943 944 ehci_queues_rip_device(s, port->dev, 0); 945 ehci_queues_rip_device(s, port->dev, 1); 946 947 *portsc &= ~(PORTSC_CONNECT|PORTSC_PED); 948 *portsc |= PORTSC_CSC; 949 950 ehci_raise_irq(s, USBSTS_PCD); 951 ehci_commit_irq(s); 952 } 953 954 static void ehci_child_detach(USBPort *port, USBDevice *child) 955 { 956 EHCIState *s = port->opaque; 957 uint32_t portsc = s->portsc[port->index]; 958 959 if (portsc & PORTSC_POWNER) { 960 USBPort *companion = s->companion_ports[port->index]; 961 companion->ops->child_detach(companion, child); 962 return; 963 } 964 965 ehci_queues_rip_device(s, child, 0); 966 ehci_queues_rip_device(s, child, 1); 967 } 968 969 static void ehci_wakeup(USBPort *port) 970 { 971 EHCIState *s = port->opaque; 972 uint32_t portsc = s->portsc[port->index]; 973 974 if (portsc & PORTSC_POWNER) { 975 USBPort *companion = s->companion_ports[port->index]; 976 if (companion->ops->wakeup) { 977 companion->ops->wakeup(companion); 978 } 979 return; 980 } 981 982 qemu_bh_schedule(s->async_bh); 983 } 984 985 static int ehci_register_companion(USBBus *bus, USBPort *ports[], 986 uint32_t portcount, uint32_t firstport) 987 { 988 EHCIState *s = container_of(bus, EHCIState, bus); 989 uint32_t i; 990 991 if (firstport + portcount > NB_PORTS) { 992 qerror_report(QERR_INVALID_PARAMETER_VALUE, "firstport", 993 "firstport on masterbus"); 994 error_printf_unless_qmp( 995 "firstport value of %u makes companion take ports %u - %u, which " 996 "is outside of the valid range of 0 - %u\n", firstport, firstport, 997 firstport + portcount - 1, NB_PORTS - 1); 998 return -1; 999 } 1000 1001 for (i = 0; i < portcount; i++) { 1002 if (s->companion_ports[firstport + i]) { 1003 qerror_report(QERR_INVALID_PARAMETER_VALUE, "masterbus", 1004 "an USB masterbus"); 1005 error_printf_unless_qmp( 1006 "port %u on masterbus %s already has a companion assigned\n", 1007 firstport + i, bus->qbus.name); 1008 return -1; 1009 } 1010 } 1011 1012 for (i = 0; i < portcount; i++) { 1013 s->companion_ports[firstport + i] = ports[i]; 1014 s->ports[firstport + i].speedmask |= 1015 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL; 1016 /* Ensure devs attached before the initial reset go to the companion */ 1017 s->portsc[firstport + i] = PORTSC_POWNER; 1018 } 1019 1020 s->companion_count++; 1021 s->mmio[0x05] = (s->companion_count << 4) | portcount; 1022 1023 return 0; 1024 } 1025 1026 static USBDevice *ehci_find_device(EHCIState *ehci, uint8_t addr) 1027 { 1028 USBDevice *dev; 1029 USBPort *port; 1030 int i; 1031 1032 for (i = 0; i < NB_PORTS; i++) { 1033 port = &ehci->ports[i]; 1034 if (!(ehci->portsc[i] & PORTSC_PED)) { 1035 DPRINTF("Port %d not enabled\n", i); 1036 continue; 1037 } 1038 dev = usb_find_device(port, addr); 1039 if (dev != NULL) { 1040 return dev; 1041 } 1042 } 1043 return NULL; 1044 } 1045 1046 /* 4.1 host controller initialization */ 1047 static void ehci_reset(void *opaque) 1048 { 1049 EHCIState *s = opaque; 1050 int i; 1051 USBDevice *devs[NB_PORTS]; 1052 1053 trace_usb_ehci_reset(); 1054 1055 /* 1056 * Do the detach before touching portsc, so that it correctly gets send to 1057 * us or to our companion based on PORTSC_POWNER before the reset. 1058 */ 1059 for(i = 0; i < NB_PORTS; i++) { 1060 devs[i] = s->ports[i].dev; 1061 if (devs[i] && devs[i]->attached) { 1062 usb_detach(&s->ports[i]); 1063 } 1064 } 1065 1066 memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE); 1067 1068 s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH; 1069 s->usbsts = USBSTS_HALT; 1070 s->usbsts_pending = 0; 1071 s->usbsts_frindex = 0; 1072 1073 s->astate = EST_INACTIVE; 1074 s->pstate = EST_INACTIVE; 1075 1076 for(i = 0; i < NB_PORTS; i++) { 1077 if (s->companion_ports[i]) { 1078 s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER; 1079 } else { 1080 s->portsc[i] = PORTSC_PPOWER; 1081 } 1082 if (devs[i] && devs[i]->attached) { 1083 usb_attach(&s->ports[i]); 1084 usb_device_reset(devs[i]); 1085 } 1086 } 1087 ehci_queues_rip_all(s, 0); 1088 ehci_queues_rip_all(s, 1); 1089 qemu_del_timer(s->frame_timer); 1090 qemu_bh_cancel(s->async_bh); 1091 } 1092 1093 static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr) 1094 { 1095 EHCIState *s = ptr; 1096 uint32_t val; 1097 1098 val = s->mmio[addr]; 1099 1100 return val; 1101 } 1102 1103 static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr) 1104 { 1105 EHCIState *s = ptr; 1106 uint32_t val; 1107 1108 val = s->mmio[addr] | (s->mmio[addr+1] << 8); 1109 1110 return val; 1111 } 1112 1113 static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr) 1114 { 1115 EHCIState *s = ptr; 1116 uint32_t val; 1117 1118 val = s->mmio[addr] | (s->mmio[addr+1] << 8) | 1119 (s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24); 1120 1121 trace_usb_ehci_mmio_readl(addr, addr2str(addr), val); 1122 return val; 1123 } 1124 1125 static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val) 1126 { 1127 fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n"); 1128 exit(1); 1129 } 1130 1131 static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val) 1132 { 1133 fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n"); 1134 exit(1); 1135 } 1136 1137 static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner) 1138 { 1139 USBDevice *dev = s->ports[port].dev; 1140 uint32_t *portsc = &s->portsc[port]; 1141 uint32_t orig; 1142 1143 if (s->companion_ports[port] == NULL) 1144 return; 1145 1146 owner = owner & PORTSC_POWNER; 1147 orig = *portsc & PORTSC_POWNER; 1148 1149 if (!(owner ^ orig)) { 1150 return; 1151 } 1152 1153 if (dev && dev->attached) { 1154 usb_detach(&s->ports[port]); 1155 } 1156 1157 *portsc &= ~PORTSC_POWNER; 1158 *portsc |= owner; 1159 1160 if (dev && dev->attached) { 1161 usb_attach(&s->ports[port]); 1162 } 1163 } 1164 1165 static void handle_port_status_write(EHCIState *s, int port, uint32_t val) 1166 { 1167 uint32_t *portsc = &s->portsc[port]; 1168 USBDevice *dev = s->ports[port].dev; 1169 1170 /* Clear rwc bits */ 1171 *portsc &= ~(val & PORTSC_RWC_MASK); 1172 /* The guest may clear, but not set the PED bit */ 1173 *portsc &= val | ~PORTSC_PED; 1174 /* POWNER is masked out by RO_MASK as it is RO when we've no companion */ 1175 handle_port_owner_write(s, port, val); 1176 /* And finally apply RO_MASK */ 1177 val &= PORTSC_RO_MASK; 1178 1179 if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) { 1180 trace_usb_ehci_port_reset(port, 1); 1181 } 1182 1183 if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) { 1184 trace_usb_ehci_port_reset(port, 0); 1185 if (dev && dev->attached) { 1186 usb_port_reset(&s->ports[port]); 1187 *portsc &= ~PORTSC_CSC; 1188 } 1189 1190 /* 1191 * Table 2.16 Set the enable bit(and enable bit change) to indicate 1192 * to SW that this port has a high speed device attached 1193 */ 1194 if (dev && dev->attached && (dev->speedmask & USB_SPEED_MASK_HIGH)) { 1195 val |= PORTSC_PED; 1196 } 1197 } 1198 1199 *portsc &= ~PORTSC_RO_MASK; 1200 *portsc |= val; 1201 } 1202 1203 static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val) 1204 { 1205 EHCIState *s = ptr; 1206 uint32_t *mmio = (uint32_t *)(&s->mmio[addr]); 1207 uint32_t old = *mmio; 1208 int i; 1209 1210 trace_usb_ehci_mmio_writel(addr, addr2str(addr), val); 1211 1212 /* Only aligned reads are allowed on OHCI */ 1213 if (addr & 3) { 1214 fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x" 1215 TARGET_FMT_plx "\n", addr); 1216 return; 1217 } 1218 1219 if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) { 1220 handle_port_status_write(s, (addr-PORTSC)/4, val); 1221 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old); 1222 return; 1223 } 1224 1225 if (addr < OPREGBASE) { 1226 fprintf(stderr, "usb-ehci: write attempt to read-only register" 1227 TARGET_FMT_plx "\n", addr); 1228 return; 1229 } 1230 1231 1232 /* Do any register specific pre-write processing here. */ 1233 switch(addr) { 1234 case USBCMD: 1235 if (val & USBCMD_HCRESET) { 1236 ehci_reset(s); 1237 val = s->usbcmd; 1238 break; 1239 } 1240 1241 /* not supporting dynamic frame list size at the moment */ 1242 if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) { 1243 fprintf(stderr, "attempt to set frame list size -- value %d\n", 1244 val & USBCMD_FLS); 1245 val &= ~USBCMD_FLS; 1246 } 1247 1248 if (val & USBCMD_IAAD) { 1249 /* 1250 * Process IAAD immediately, otherwise the Linux IAAD watchdog may 1251 * trigger and re-use a qh without us seeing the unlink. 1252 */ 1253 s->async_stepdown = 0; 1254 qemu_bh_schedule(s->async_bh); 1255 trace_usb_ehci_doorbell_ring(); 1256 } 1257 1258 if (((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & val) != 1259 ((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & s->usbcmd)) { 1260 if (s->pstate == EST_INACTIVE) { 1261 SET_LAST_RUN_CLOCK(s); 1262 } 1263 s->usbcmd = val; /* Set usbcmd for ehci_update_halt() */ 1264 ehci_update_halt(s); 1265 s->async_stepdown = 0; 1266 qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock)); 1267 } 1268 break; 1269 1270 case USBSTS: 1271 val &= USBSTS_RO_MASK; // bits 6 through 31 are RO 1272 ehci_clear_usbsts(s, val); // bits 0 through 5 are R/WC 1273 val = s->usbsts; 1274 ehci_update_irq(s); 1275 break; 1276 1277 case USBINTR: 1278 val &= USBINTR_MASK; 1279 break; 1280 1281 case FRINDEX: 1282 val &= 0x00003ff8; /* frindex is 14bits and always a multiple of 8 */ 1283 break; 1284 1285 case CONFIGFLAG: 1286 val &= 0x1; 1287 if (val) { 1288 for(i = 0; i < NB_PORTS; i++) 1289 handle_port_owner_write(s, i, 0); 1290 } 1291 break; 1292 1293 case PERIODICLISTBASE: 1294 if (ehci_periodic_enabled(s)) { 1295 fprintf(stderr, 1296 "ehci: PERIODIC list base register set while periodic schedule\n" 1297 " is enabled and HC is enabled\n"); 1298 } 1299 break; 1300 1301 case ASYNCLISTADDR: 1302 if (ehci_async_enabled(s)) { 1303 fprintf(stderr, 1304 "ehci: ASYNC list address register set while async schedule\n" 1305 " is enabled and HC is enabled\n"); 1306 } 1307 break; 1308 } 1309 1310 *mmio = val; 1311 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old); 1312 } 1313 1314 1315 // TODO : Put in common header file, duplication from usb-ohci.c 1316 1317 /* Get an array of dwords from main memory */ 1318 static inline int get_dwords(EHCIState *ehci, uint32_t addr, 1319 uint32_t *buf, int num) 1320 { 1321 int i; 1322 1323 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { 1324 pci_dma_read(&ehci->dev, addr, buf, sizeof(*buf)); 1325 *buf = le32_to_cpu(*buf); 1326 } 1327 1328 return 1; 1329 } 1330 1331 /* Put an array of dwords in to main memory */ 1332 static inline int put_dwords(EHCIState *ehci, uint32_t addr, 1333 uint32_t *buf, int num) 1334 { 1335 int i; 1336 1337 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { 1338 uint32_t tmp = cpu_to_le32(*buf); 1339 pci_dma_write(&ehci->dev, addr, &tmp, sizeof(tmp)); 1340 } 1341 1342 return 1; 1343 } 1344 1345 /* 1346 * Write the qh back to guest physical memory. This step isn't 1347 * in the EHCI spec but we need to do it since we don't share 1348 * physical memory with our guest VM. 1349 * 1350 * The first three dwords are read-only for the EHCI, so skip them 1351 * when writing back the qh. 1352 */ 1353 static void ehci_flush_qh(EHCIQueue *q) 1354 { 1355 uint32_t *qh = (uint32_t *) &q->qh; 1356 uint32_t dwords = sizeof(EHCIqh) >> 2; 1357 uint32_t addr = NLPTR_GET(q->qhaddr); 1358 1359 put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3); 1360 } 1361 1362 // 4.10.2 1363 1364 static int ehci_qh_do_overlay(EHCIQueue *q) 1365 { 1366 EHCIPacket *p = QTAILQ_FIRST(&q->packets); 1367 int i; 1368 int dtoggle; 1369 int ping; 1370 int eps; 1371 int reload; 1372 1373 assert(p != NULL); 1374 assert(p->qtdaddr == q->qtdaddr); 1375 1376 // remember values in fields to preserve in qh after overlay 1377 1378 dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE; 1379 ping = q->qh.token & QTD_TOKEN_PING; 1380 1381 q->qh.current_qtd = p->qtdaddr; 1382 q->qh.next_qtd = p->qtd.next; 1383 q->qh.altnext_qtd = p->qtd.altnext; 1384 q->qh.token = p->qtd.token; 1385 1386 1387 eps = get_field(q->qh.epchar, QH_EPCHAR_EPS); 1388 if (eps == EHCI_QH_EPS_HIGH) { 1389 q->qh.token &= ~QTD_TOKEN_PING; 1390 q->qh.token |= ping; 1391 } 1392 1393 reload = get_field(q->qh.epchar, QH_EPCHAR_RL); 1394 set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT); 1395 1396 for (i = 0; i < 5; i++) { 1397 q->qh.bufptr[i] = p->qtd.bufptr[i]; 1398 } 1399 1400 if (!(q->qh.epchar & QH_EPCHAR_DTC)) { 1401 // preserve QH DT bit 1402 q->qh.token &= ~QTD_TOKEN_DTOGGLE; 1403 q->qh.token |= dtoggle; 1404 } 1405 1406 q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK; 1407 q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK; 1408 1409 ehci_flush_qh(q); 1410 1411 return 0; 1412 } 1413 1414 static int ehci_init_transfer(EHCIPacket *p) 1415 { 1416 uint32_t cpage, offset, bytes, plen; 1417 dma_addr_t page; 1418 1419 cpage = get_field(p->qtd.token, QTD_TOKEN_CPAGE); 1420 bytes = get_field(p->qtd.token, QTD_TOKEN_TBYTES); 1421 offset = p->qtd.bufptr[0] & ~QTD_BUFPTR_MASK; 1422 pci_dma_sglist_init(&p->sgl, &p->queue->ehci->dev, 5); 1423 1424 while (bytes > 0) { 1425 if (cpage > 4) { 1426 fprintf(stderr, "cpage out of range (%d)\n", cpage); 1427 return USB_RET_PROCERR; 1428 } 1429 1430 page = p->qtd.bufptr[cpage] & QTD_BUFPTR_MASK; 1431 page += offset; 1432 plen = bytes; 1433 if (plen > 4096 - offset) { 1434 plen = 4096 - offset; 1435 offset = 0; 1436 cpage++; 1437 } 1438 1439 qemu_sglist_add(&p->sgl, page, plen); 1440 bytes -= plen; 1441 } 1442 return 0; 1443 } 1444 1445 static void ehci_finish_transfer(EHCIQueue *q, int status) 1446 { 1447 uint32_t cpage, offset; 1448 1449 if (status > 0) { 1450 /* update cpage & offset */ 1451 cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE); 1452 offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK; 1453 1454 offset += status; 1455 cpage += offset >> QTD_BUFPTR_SH; 1456 offset &= ~QTD_BUFPTR_MASK; 1457 1458 set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE); 1459 q->qh.bufptr[0] &= QTD_BUFPTR_MASK; 1460 q->qh.bufptr[0] |= offset; 1461 } 1462 } 1463 1464 static void ehci_async_complete_packet(USBPort *port, USBPacket *packet) 1465 { 1466 EHCIPacket *p; 1467 EHCIState *s = port->opaque; 1468 uint32_t portsc = s->portsc[port->index]; 1469 1470 if (portsc & PORTSC_POWNER) { 1471 USBPort *companion = s->companion_ports[port->index]; 1472 companion->ops->complete(companion, packet); 1473 return; 1474 } 1475 1476 p = container_of(packet, EHCIPacket, packet); 1477 trace_usb_ehci_packet_action(p->queue, p, "wakeup"); 1478 assert(p->async == EHCI_ASYNC_INFLIGHT); 1479 p->async = EHCI_ASYNC_FINISHED; 1480 p->usb_status = packet->result; 1481 1482 if (p->queue->async) { 1483 qemu_bh_schedule(p->queue->ehci->async_bh); 1484 } 1485 } 1486 1487 static void ehci_execute_complete(EHCIQueue *q) 1488 { 1489 EHCIPacket *p = QTAILQ_FIRST(&q->packets); 1490 1491 assert(p != NULL); 1492 assert(p->qtdaddr == q->qtdaddr); 1493 assert(p->async == EHCI_ASYNC_INITIALIZED || 1494 p->async == EHCI_ASYNC_FINISHED); 1495 1496 DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n", 1497 q->qhaddr, q->qh.next, q->qtdaddr, q->usb_status); 1498 1499 if (p->usb_status < 0) { 1500 switch (p->usb_status) { 1501 case USB_RET_IOERROR: 1502 case USB_RET_NODEV: 1503 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR); 1504 set_field(&q->qh.token, 0, QTD_TOKEN_CERR); 1505 ehci_raise_irq(q->ehci, USBSTS_ERRINT); 1506 break; 1507 case USB_RET_STALL: 1508 q->qh.token |= QTD_TOKEN_HALT; 1509 ehci_raise_irq(q->ehci, USBSTS_ERRINT); 1510 break; 1511 case USB_RET_NAK: 1512 set_field(&q->qh.altnext_qtd, 0, QH_ALTNEXT_NAKCNT); 1513 return; /* We're not done yet with this transaction */ 1514 case USB_RET_BABBLE: 1515 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE); 1516 ehci_raise_irq(q->ehci, USBSTS_ERRINT); 1517 break; 1518 default: 1519 /* should not be triggerable */ 1520 fprintf(stderr, "USB invalid response %d\n", p->usb_status); 1521 assert(0); 1522 break; 1523 } 1524 } else { 1525 // TODO check 4.12 for splits 1526 1527 if (p->tbytes && p->pid == USB_TOKEN_IN) { 1528 p->tbytes -= p->usb_status; 1529 } else { 1530 p->tbytes = 0; 1531 } 1532 1533 DPRINTF("updating tbytes to %d\n", p->tbytes); 1534 set_field(&q->qh.token, p->tbytes, QTD_TOKEN_TBYTES); 1535 } 1536 ehci_finish_transfer(q, p->usb_status); 1537 usb_packet_unmap(&p->packet, &p->sgl); 1538 qemu_sglist_destroy(&p->sgl); 1539 p->async = EHCI_ASYNC_NONE; 1540 1541 q->qh.token ^= QTD_TOKEN_DTOGGLE; 1542 q->qh.token &= ~QTD_TOKEN_ACTIVE; 1543 1544 if (q->qh.token & QTD_TOKEN_IOC) { 1545 ehci_raise_irq(q->ehci, USBSTS_INT); 1546 } 1547 } 1548 1549 // 4.10.3 1550 1551 static int ehci_execute(EHCIPacket *p, const char *action) 1552 { 1553 USBEndpoint *ep; 1554 int ret; 1555 int endp; 1556 1557 assert(p->async == EHCI_ASYNC_NONE || 1558 p->async == EHCI_ASYNC_INITIALIZED); 1559 1560 if (!(p->qtd.token & QTD_TOKEN_ACTIVE)) { 1561 fprintf(stderr, "Attempting to execute inactive qtd\n"); 1562 return USB_RET_PROCERR; 1563 } 1564 1565 p->tbytes = (p->qtd.token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH; 1566 if (p->tbytes > BUFF_SIZE) { 1567 ehci_trace_guest_bug(p->queue->ehci, 1568 "guest requested more bytes than allowed"); 1569 return USB_RET_PROCERR; 1570 } 1571 1572 p->pid = (p->qtd.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH; 1573 switch (p->pid) { 1574 case 0: 1575 p->pid = USB_TOKEN_OUT; 1576 break; 1577 case 1: 1578 p->pid = USB_TOKEN_IN; 1579 break; 1580 case 2: 1581 p->pid = USB_TOKEN_SETUP; 1582 break; 1583 default: 1584 fprintf(stderr, "bad token\n"); 1585 break; 1586 } 1587 1588 endp = get_field(p->queue->qh.epchar, QH_EPCHAR_EP); 1589 ep = usb_ep_get(p->queue->dev, p->pid, endp); 1590 1591 if (p->async == EHCI_ASYNC_NONE) { 1592 if (ehci_init_transfer(p) != 0) { 1593 return USB_RET_PROCERR; 1594 } 1595 1596 usb_packet_setup(&p->packet, p->pid, ep, p->qtdaddr); 1597 usb_packet_map(&p->packet, &p->sgl); 1598 p->async = EHCI_ASYNC_INITIALIZED; 1599 } 1600 1601 trace_usb_ehci_packet_action(p->queue, p, action); 1602 ret = usb_handle_packet(p->queue->dev, &p->packet); 1603 DPRINTF("submit: qh %x next %x qtd %x pid %x len %zd " 1604 "(total %d) endp %x ret %d\n", 1605 q->qhaddr, q->qh.next, q->qtdaddr, q->pid, 1606 q->packet.iov.size, q->tbytes, endp, ret); 1607 1608 if (ret > BUFF_SIZE) { 1609 fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n"); 1610 return USB_RET_PROCERR; 1611 } 1612 1613 return ret; 1614 } 1615 1616 /* 4.7.2 1617 */ 1618 1619 static int ehci_process_itd(EHCIState *ehci, 1620 EHCIitd *itd, 1621 uint32_t addr) 1622 { 1623 USBDevice *dev; 1624 USBEndpoint *ep; 1625 int ret; 1626 uint32_t i, len, pid, dir, devaddr, endp; 1627 uint32_t pg, off, ptr1, ptr2, max, mult; 1628 1629 dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION); 1630 devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR); 1631 endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP); 1632 max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT); 1633 mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT); 1634 1635 for(i = 0; i < 8; i++) { 1636 if (itd->transact[i] & ITD_XACT_ACTIVE) { 1637 pg = get_field(itd->transact[i], ITD_XACT_PGSEL); 1638 off = itd->transact[i] & ITD_XACT_OFFSET_MASK; 1639 ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK); 1640 ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK); 1641 len = get_field(itd->transact[i], ITD_XACT_LENGTH); 1642 1643 if (len > max * mult) { 1644 len = max * mult; 1645 } 1646 1647 if (len > BUFF_SIZE) { 1648 return USB_RET_PROCERR; 1649 } 1650 1651 pci_dma_sglist_init(&ehci->isgl, &ehci->dev, 2); 1652 if (off + len > 4096) { 1653 /* transfer crosses page border */ 1654 uint32_t len2 = off + len - 4096; 1655 uint32_t len1 = len - len2; 1656 qemu_sglist_add(&ehci->isgl, ptr1 + off, len1); 1657 qemu_sglist_add(&ehci->isgl, ptr2, len2); 1658 } else { 1659 qemu_sglist_add(&ehci->isgl, ptr1 + off, len); 1660 } 1661 1662 pid = dir ? USB_TOKEN_IN : USB_TOKEN_OUT; 1663 1664 dev = ehci_find_device(ehci, devaddr); 1665 ep = usb_ep_get(dev, pid, endp); 1666 if (ep && ep->type == USB_ENDPOINT_XFER_ISOC) { 1667 usb_packet_setup(&ehci->ipacket, pid, ep, addr); 1668 usb_packet_map(&ehci->ipacket, &ehci->isgl); 1669 ret = usb_handle_packet(dev, &ehci->ipacket); 1670 assert(ret != USB_RET_ASYNC); 1671 usb_packet_unmap(&ehci->ipacket, &ehci->isgl); 1672 } else { 1673 DPRINTF("ISOCH: attempt to addess non-iso endpoint\n"); 1674 ret = USB_RET_NAK; 1675 } 1676 qemu_sglist_destroy(&ehci->isgl); 1677 1678 if (ret < 0) { 1679 switch (ret) { 1680 default: 1681 fprintf(stderr, "Unexpected iso usb result: %d\n", ret); 1682 /* Fall through */ 1683 case USB_RET_IOERROR: 1684 case USB_RET_NODEV: 1685 /* 3.3.2: XACTERR is only allowed on IN transactions */ 1686 if (dir) { 1687 itd->transact[i] |= ITD_XACT_XACTERR; 1688 ehci_raise_irq(ehci, USBSTS_ERRINT); 1689 } 1690 break; 1691 case USB_RET_BABBLE: 1692 itd->transact[i] |= ITD_XACT_BABBLE; 1693 ehci_raise_irq(ehci, USBSTS_ERRINT); 1694 break; 1695 case USB_RET_NAK: 1696 /* no data for us, so do a zero-length transfer */ 1697 ret = 0; 1698 break; 1699 } 1700 } 1701 if (ret >= 0) { 1702 if (!dir) { 1703 /* OUT */ 1704 set_field(&itd->transact[i], len - ret, ITD_XACT_LENGTH); 1705 } else { 1706 /* IN */ 1707 set_field(&itd->transact[i], ret, ITD_XACT_LENGTH); 1708 } 1709 } 1710 if (itd->transact[i] & ITD_XACT_IOC) { 1711 ehci_raise_irq(ehci, USBSTS_INT); 1712 } 1713 itd->transact[i] &= ~ITD_XACT_ACTIVE; 1714 } 1715 } 1716 return 0; 1717 } 1718 1719 1720 /* This state is the entry point for asynchronous schedule 1721 * processing. Entry here consitutes a EHCI start event state (4.8.5) 1722 */ 1723 static int ehci_state_waitlisthead(EHCIState *ehci, int async) 1724 { 1725 EHCIqh qh; 1726 int i = 0; 1727 int again = 0; 1728 uint32_t entry = ehci->asynclistaddr; 1729 1730 /* set reclamation flag at start event (4.8.6) */ 1731 if (async) { 1732 ehci_set_usbsts(ehci, USBSTS_REC); 1733 } 1734 1735 ehci_queues_rip_unused(ehci, async, 0); 1736 1737 /* Find the head of the list (4.9.1.1) */ 1738 for(i = 0; i < MAX_QH; i++) { 1739 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &qh, 1740 sizeof(EHCIqh) >> 2); 1741 ehci_trace_qh(NULL, NLPTR_GET(entry), &qh); 1742 1743 if (qh.epchar & QH_EPCHAR_H) { 1744 if (async) { 1745 entry |= (NLPTR_TYPE_QH << 1); 1746 } 1747 1748 ehci_set_fetch_addr(ehci, async, entry); 1749 ehci_set_state(ehci, async, EST_FETCHENTRY); 1750 again = 1; 1751 goto out; 1752 } 1753 1754 entry = qh.next; 1755 if (entry == ehci->asynclistaddr) { 1756 break; 1757 } 1758 } 1759 1760 /* no head found for list. */ 1761 1762 ehci_set_state(ehci, async, EST_ACTIVE); 1763 1764 out: 1765 return again; 1766 } 1767 1768 1769 /* This state is the entry point for periodic schedule processing as 1770 * well as being a continuation state for async processing. 1771 */ 1772 static int ehci_state_fetchentry(EHCIState *ehci, int async) 1773 { 1774 int again = 0; 1775 uint32_t entry = ehci_get_fetch_addr(ehci, async); 1776 1777 if (NLPTR_TBIT(entry)) { 1778 ehci_set_state(ehci, async, EST_ACTIVE); 1779 goto out; 1780 } 1781 1782 /* section 4.8, only QH in async schedule */ 1783 if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) { 1784 fprintf(stderr, "non queue head request in async schedule\n"); 1785 return -1; 1786 } 1787 1788 switch (NLPTR_TYPE_GET(entry)) { 1789 case NLPTR_TYPE_QH: 1790 ehci_set_state(ehci, async, EST_FETCHQH); 1791 again = 1; 1792 break; 1793 1794 case NLPTR_TYPE_ITD: 1795 ehci_set_state(ehci, async, EST_FETCHITD); 1796 again = 1; 1797 break; 1798 1799 case NLPTR_TYPE_STITD: 1800 ehci_set_state(ehci, async, EST_FETCHSITD); 1801 again = 1; 1802 break; 1803 1804 default: 1805 /* TODO: handle FSTN type */ 1806 fprintf(stderr, "FETCHENTRY: entry at %X is of type %d " 1807 "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry)); 1808 return -1; 1809 } 1810 1811 out: 1812 return again; 1813 } 1814 1815 static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async) 1816 { 1817 EHCIPacket *p; 1818 uint32_t entry, devaddr, endp; 1819 EHCIQueue *q; 1820 EHCIqh qh; 1821 1822 entry = ehci_get_fetch_addr(ehci, async); 1823 q = ehci_find_queue_by_qh(ehci, entry, async); 1824 if (NULL == q) { 1825 q = ehci_alloc_queue(ehci, entry, async); 1826 } 1827 p = QTAILQ_FIRST(&q->packets); 1828 1829 q->seen++; 1830 if (q->seen > 1) { 1831 /* we are going in circles -- stop processing */ 1832 ehci_set_state(ehci, async, EST_ACTIVE); 1833 q = NULL; 1834 goto out; 1835 } 1836 1837 get_dwords(ehci, NLPTR_GET(q->qhaddr), 1838 (uint32_t *) &qh, sizeof(EHCIqh) >> 2); 1839 ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &qh); 1840 1841 /* 1842 * The overlay area of the qh should never be changed by the guest, 1843 * except when idle, in which case the reset is a nop. 1844 */ 1845 devaddr = get_field(qh.epchar, QH_EPCHAR_DEVADDR); 1846 endp = get_field(qh.epchar, QH_EPCHAR_EP); 1847 if ((devaddr != get_field(q->qh.epchar, QH_EPCHAR_DEVADDR)) || 1848 (endp != get_field(q->qh.epchar, QH_EPCHAR_EP)) || 1849 (memcmp(&qh.current_qtd, &q->qh.current_qtd, 1850 9 * sizeof(uint32_t)) != 0) || 1851 (q->dev != NULL && q->dev->addr != devaddr)) { 1852 if (ehci_reset_queue(q) > 0) { 1853 ehci_trace_guest_bug(ehci, "guest updated active QH"); 1854 } 1855 p = NULL; 1856 } 1857 q->qh = qh; 1858 1859 if (q->dev == NULL) { 1860 q->dev = ehci_find_device(q->ehci, devaddr); 1861 } 1862 1863 if (p && p->async == EHCI_ASYNC_FINISHED) { 1864 /* I/O finished -- continue processing queue */ 1865 trace_usb_ehci_packet_action(p->queue, p, "complete"); 1866 ehci_set_state(ehci, async, EST_EXECUTING); 1867 goto out; 1868 } 1869 1870 if (async && (q->qh.epchar & QH_EPCHAR_H)) { 1871 1872 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */ 1873 if (ehci->usbsts & USBSTS_REC) { 1874 ehci_clear_usbsts(ehci, USBSTS_REC); 1875 } else { 1876 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset" 1877 " - done processing\n", q->qhaddr); 1878 ehci_set_state(ehci, async, EST_ACTIVE); 1879 q = NULL; 1880 goto out; 1881 } 1882 } 1883 1884 #if EHCI_DEBUG 1885 if (q->qhaddr != q->qh.next) { 1886 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n", 1887 q->qhaddr, 1888 q->qh.epchar & QH_EPCHAR_H, 1889 q->qh.token & QTD_TOKEN_HALT, 1890 q->qh.token & QTD_TOKEN_ACTIVE, 1891 q->qh.next); 1892 } 1893 #endif 1894 1895 if (q->qh.token & QTD_TOKEN_HALT) { 1896 ehci_set_state(ehci, async, EST_HORIZONTALQH); 1897 1898 } else if ((q->qh.token & QTD_TOKEN_ACTIVE) && 1899 (NLPTR_TBIT(q->qh.current_qtd) == 0)) { 1900 q->qtdaddr = q->qh.current_qtd; 1901 ehci_set_state(ehci, async, EST_FETCHQTD); 1902 1903 } else { 1904 /* EHCI spec version 1.0 Section 4.10.2 */ 1905 ehci_set_state(ehci, async, EST_ADVANCEQUEUE); 1906 } 1907 1908 out: 1909 return q; 1910 } 1911 1912 static int ehci_state_fetchitd(EHCIState *ehci, int async) 1913 { 1914 uint32_t entry; 1915 EHCIitd itd; 1916 1917 assert(!async); 1918 entry = ehci_get_fetch_addr(ehci, async); 1919 1920 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd, 1921 sizeof(EHCIitd) >> 2); 1922 ehci_trace_itd(ehci, entry, &itd); 1923 1924 if (ehci_process_itd(ehci, &itd, entry) != 0) { 1925 return -1; 1926 } 1927 1928 put_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd, 1929 sizeof(EHCIitd) >> 2); 1930 ehci_set_fetch_addr(ehci, async, itd.next); 1931 ehci_set_state(ehci, async, EST_FETCHENTRY); 1932 1933 return 1; 1934 } 1935 1936 static int ehci_state_fetchsitd(EHCIState *ehci, int async) 1937 { 1938 uint32_t entry; 1939 EHCIsitd sitd; 1940 1941 assert(!async); 1942 entry = ehci_get_fetch_addr(ehci, async); 1943 1944 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *)&sitd, 1945 sizeof(EHCIsitd) >> 2); 1946 ehci_trace_sitd(ehci, entry, &sitd); 1947 1948 if (!(sitd.results & SITD_RESULTS_ACTIVE)) { 1949 /* siTD is not active, nothing to do */; 1950 } else { 1951 /* TODO: split transfers are not implemented */ 1952 fprintf(stderr, "WARNING: Skipping active siTD\n"); 1953 } 1954 1955 ehci_set_fetch_addr(ehci, async, sitd.next); 1956 ehci_set_state(ehci, async, EST_FETCHENTRY); 1957 return 1; 1958 } 1959 1960 /* Section 4.10.2 - paragraph 3 */ 1961 static int ehci_state_advqueue(EHCIQueue *q) 1962 { 1963 #if 0 1964 /* TO-DO: 4.10.2 - paragraph 2 1965 * if I-bit is set to 1 and QH is not active 1966 * go to horizontal QH 1967 */ 1968 if (I-bit set) { 1969 ehci_set_state(ehci, async, EST_HORIZONTALQH); 1970 goto out; 1971 } 1972 #endif 1973 1974 /* 1975 * want data and alt-next qTD is valid 1976 */ 1977 if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) && 1978 (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) { 1979 q->qtdaddr = q->qh.altnext_qtd; 1980 ehci_set_state(q->ehci, q->async, EST_FETCHQTD); 1981 1982 /* 1983 * next qTD is valid 1984 */ 1985 } else if (NLPTR_TBIT(q->qh.next_qtd) == 0) { 1986 q->qtdaddr = q->qh.next_qtd; 1987 ehci_set_state(q->ehci, q->async, EST_FETCHQTD); 1988 1989 /* 1990 * no valid qTD, try next QH 1991 */ 1992 } else { 1993 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); 1994 } 1995 1996 return 1; 1997 } 1998 1999 /* Section 4.10.2 - paragraph 4 */ 2000 static int ehci_state_fetchqtd(EHCIQueue *q) 2001 { 2002 EHCIqtd qtd; 2003 EHCIPacket *p; 2004 int again = 0; 2005 2006 get_dwords(q->ehci, NLPTR_GET(q->qtdaddr), (uint32_t *) &qtd, 2007 sizeof(EHCIqtd) >> 2); 2008 ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &qtd); 2009 2010 p = QTAILQ_FIRST(&q->packets); 2011 if (p != NULL) { 2012 if (p->qtdaddr != q->qtdaddr || 2013 (!NLPTR_TBIT(p->qtd.next) && (p->qtd.next != qtd.next)) || 2014 (!NLPTR_TBIT(p->qtd.altnext) && (p->qtd.altnext != qtd.altnext)) || 2015 p->qtd.bufptr[0] != qtd.bufptr[0]) { 2016 ehci_cancel_queue(q); 2017 ehci_trace_guest_bug(q->ehci, "guest updated active QH or qTD"); 2018 p = NULL; 2019 } else { 2020 p->qtd = qtd; 2021 ehci_qh_do_overlay(q); 2022 } 2023 } 2024 2025 if (!(qtd.token & QTD_TOKEN_ACTIVE)) { 2026 if (p != NULL) { 2027 /* transfer canceled by guest (clear active) */ 2028 ehci_cancel_queue(q); 2029 p = NULL; 2030 } 2031 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); 2032 again = 1; 2033 } else if (p != NULL) { 2034 switch (p->async) { 2035 case EHCI_ASYNC_NONE: 2036 /* Should never happen packet should at least be initialized */ 2037 assert(0); 2038 break; 2039 case EHCI_ASYNC_INITIALIZED: 2040 /* Previously nacked packet (likely interrupt ep) */ 2041 ehci_set_state(q->ehci, q->async, EST_EXECUTE); 2042 break; 2043 case EHCI_ASYNC_INFLIGHT: 2044 /* Unfinished async handled packet, go horizontal */ 2045 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); 2046 break; 2047 case EHCI_ASYNC_FINISHED: 2048 /* 2049 * We get here when advqueue moves to a packet which is already 2050 * finished, which can happen with packets queued up by fill_queue 2051 */ 2052 ehci_set_state(q->ehci, q->async, EST_EXECUTING); 2053 break; 2054 } 2055 again = 1; 2056 } else { 2057 p = ehci_alloc_packet(q); 2058 p->qtdaddr = q->qtdaddr; 2059 p->qtd = qtd; 2060 ehci_set_state(q->ehci, q->async, EST_EXECUTE); 2061 again = 1; 2062 } 2063 2064 return again; 2065 } 2066 2067 static int ehci_state_horizqh(EHCIQueue *q) 2068 { 2069 int again = 0; 2070 2071 if (ehci_get_fetch_addr(q->ehci, q->async) != q->qh.next) { 2072 ehci_set_fetch_addr(q->ehci, q->async, q->qh.next); 2073 ehci_set_state(q->ehci, q->async, EST_FETCHENTRY); 2074 again = 1; 2075 } else { 2076 ehci_set_state(q->ehci, q->async, EST_ACTIVE); 2077 } 2078 2079 return again; 2080 } 2081 2082 static int ehci_fill_queue(EHCIPacket *p) 2083 { 2084 EHCIQueue *q = p->queue; 2085 EHCIqtd qtd = p->qtd; 2086 uint32_t qtdaddr; 2087 2088 for (;;) { 2089 if (NLPTR_TBIT(qtd.altnext) == 0) { 2090 break; 2091 } 2092 if (NLPTR_TBIT(qtd.next) != 0) { 2093 break; 2094 } 2095 qtdaddr = qtd.next; 2096 get_dwords(q->ehci, NLPTR_GET(qtdaddr), 2097 (uint32_t *) &qtd, sizeof(EHCIqtd) >> 2); 2098 ehci_trace_qtd(q, NLPTR_GET(qtdaddr), &qtd); 2099 if (!(qtd.token & QTD_TOKEN_ACTIVE)) { 2100 break; 2101 } 2102 p = ehci_alloc_packet(q); 2103 p->qtdaddr = qtdaddr; 2104 p->qtd = qtd; 2105 p->usb_status = ehci_execute(p, "queue"); 2106 if (p->usb_status == USB_RET_PROCERR) { 2107 break; 2108 } 2109 assert(p->usb_status == USB_RET_ASYNC); 2110 p->async = EHCI_ASYNC_INFLIGHT; 2111 } 2112 return p->usb_status; 2113 } 2114 2115 static int ehci_state_execute(EHCIQueue *q) 2116 { 2117 EHCIPacket *p = QTAILQ_FIRST(&q->packets); 2118 int again = 0; 2119 2120 assert(p != NULL); 2121 assert(p->qtdaddr == q->qtdaddr); 2122 2123 if (ehci_qh_do_overlay(q) != 0) { 2124 return -1; 2125 } 2126 2127 // TODO verify enough time remains in the uframe as in 4.4.1.1 2128 // TODO write back ptr to async list when done or out of time 2129 // TODO Windows does not seem to ever set the MULT field 2130 2131 if (!q->async) { 2132 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT); 2133 if (!transactCtr) { 2134 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); 2135 again = 1; 2136 goto out; 2137 } 2138 } 2139 2140 if (q->async) { 2141 ehci_set_usbsts(q->ehci, USBSTS_REC); 2142 } 2143 2144 p->usb_status = ehci_execute(p, "process"); 2145 if (p->usb_status == USB_RET_PROCERR) { 2146 again = -1; 2147 goto out; 2148 } 2149 if (p->usb_status == USB_RET_ASYNC) { 2150 ehci_flush_qh(q); 2151 trace_usb_ehci_packet_action(p->queue, p, "async"); 2152 p->async = EHCI_ASYNC_INFLIGHT; 2153 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); 2154 again = (ehci_fill_queue(p) == USB_RET_PROCERR) ? -1 : 1; 2155 goto out; 2156 } 2157 2158 ehci_set_state(q->ehci, q->async, EST_EXECUTING); 2159 again = 1; 2160 2161 out: 2162 return again; 2163 } 2164 2165 static int ehci_state_executing(EHCIQueue *q) 2166 { 2167 EHCIPacket *p = QTAILQ_FIRST(&q->packets); 2168 2169 assert(p != NULL); 2170 assert(p->qtdaddr == q->qtdaddr); 2171 2172 ehci_execute_complete(q); 2173 2174 // 4.10.3 2175 if (!q->async) { 2176 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT); 2177 transactCtr--; 2178 set_field(&q->qh.epcap, transactCtr, QH_EPCAP_MULT); 2179 // 4.10.3, bottom of page 82, should exit this state when transaction 2180 // counter decrements to 0 2181 } 2182 2183 /* 4.10.5 */ 2184 if (p->usb_status == USB_RET_NAK) { 2185 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); 2186 } else { 2187 ehci_set_state(q->ehci, q->async, EST_WRITEBACK); 2188 } 2189 2190 ehci_flush_qh(q); 2191 return 1; 2192 } 2193 2194 2195 static int ehci_state_writeback(EHCIQueue *q) 2196 { 2197 EHCIPacket *p = QTAILQ_FIRST(&q->packets); 2198 uint32_t *qtd, addr; 2199 int again = 0; 2200 2201 /* Write back the QTD from the QH area */ 2202 assert(p != NULL); 2203 assert(p->qtdaddr == q->qtdaddr); 2204 2205 ehci_trace_qtd(q, NLPTR_GET(p->qtdaddr), (EHCIqtd *) &q->qh.next_qtd); 2206 qtd = (uint32_t *) &q->qh.next_qtd; 2207 addr = NLPTR_GET(p->qtdaddr); 2208 put_dwords(q->ehci, addr + 2 * sizeof(uint32_t), qtd + 2, 2); 2209 ehci_free_packet(p); 2210 2211 /* 2212 * EHCI specs say go horizontal here. 2213 * 2214 * We can also advance the queue here for performance reasons. We 2215 * need to take care to only take that shortcut in case we've 2216 * processed the qtd just written back without errors, i.e. halt 2217 * bit is clear. 2218 */ 2219 if (q->qh.token & QTD_TOKEN_HALT) { 2220 /* 2221 * We should not do any further processing on a halted queue! 2222 * This is esp. important for bulk endpoints with pipelining enabled 2223 * (redirection to a real USB device), where we must cancel all the 2224 * transfers after this one so that: 2225 * 1) If they've completed already, they are not processed further 2226 * causing more stalls, originating from the same failed transfer 2227 * 2) If still in flight, they are cancelled before the guest does 2228 * a clear stall, otherwise the guest and device can loose sync! 2229 */ 2230 while ((p = QTAILQ_FIRST(&q->packets)) != NULL) { 2231 ehci_free_packet(p); 2232 } 2233 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); 2234 again = 1; 2235 } else { 2236 ehci_set_state(q->ehci, q->async, EST_ADVANCEQUEUE); 2237 again = 1; 2238 } 2239 return again; 2240 } 2241 2242 /* 2243 * This is the state machine that is common to both async and periodic 2244 */ 2245 2246 static void ehci_advance_state(EHCIState *ehci, int async) 2247 { 2248 EHCIQueue *q = NULL; 2249 int again; 2250 2251 do { 2252 switch(ehci_get_state(ehci, async)) { 2253 case EST_WAITLISTHEAD: 2254 again = ehci_state_waitlisthead(ehci, async); 2255 break; 2256 2257 case EST_FETCHENTRY: 2258 again = ehci_state_fetchentry(ehci, async); 2259 break; 2260 2261 case EST_FETCHQH: 2262 q = ehci_state_fetchqh(ehci, async); 2263 if (q != NULL) { 2264 assert(q->async == async); 2265 again = 1; 2266 } else { 2267 again = 0; 2268 } 2269 break; 2270 2271 case EST_FETCHITD: 2272 again = ehci_state_fetchitd(ehci, async); 2273 break; 2274 2275 case EST_FETCHSITD: 2276 again = ehci_state_fetchsitd(ehci, async); 2277 break; 2278 2279 case EST_ADVANCEQUEUE: 2280 again = ehci_state_advqueue(q); 2281 break; 2282 2283 case EST_FETCHQTD: 2284 again = ehci_state_fetchqtd(q); 2285 break; 2286 2287 case EST_HORIZONTALQH: 2288 again = ehci_state_horizqh(q); 2289 break; 2290 2291 case EST_EXECUTE: 2292 again = ehci_state_execute(q); 2293 if (async) { 2294 ehci->async_stepdown = 0; 2295 } 2296 break; 2297 2298 case EST_EXECUTING: 2299 assert(q != NULL); 2300 if (async) { 2301 ehci->async_stepdown = 0; 2302 } 2303 again = ehci_state_executing(q); 2304 break; 2305 2306 case EST_WRITEBACK: 2307 assert(q != NULL); 2308 again = ehci_state_writeback(q); 2309 break; 2310 2311 default: 2312 fprintf(stderr, "Bad state!\n"); 2313 again = -1; 2314 assert(0); 2315 break; 2316 } 2317 2318 if (again < 0) { 2319 fprintf(stderr, "processing error - resetting ehci HC\n"); 2320 ehci_reset(ehci); 2321 again = 0; 2322 } 2323 } 2324 while (again); 2325 } 2326 2327 static void ehci_advance_async_state(EHCIState *ehci) 2328 { 2329 const int async = 1; 2330 2331 switch(ehci_get_state(ehci, async)) { 2332 case EST_INACTIVE: 2333 if (!ehci_async_enabled(ehci)) { 2334 break; 2335 } 2336 ehci_set_state(ehci, async, EST_ACTIVE); 2337 // No break, fall through to ACTIVE 2338 2339 case EST_ACTIVE: 2340 if (!ehci_async_enabled(ehci)) { 2341 ehci_queues_rip_all(ehci, async); 2342 ehci_set_state(ehci, async, EST_INACTIVE); 2343 break; 2344 } 2345 2346 /* make sure guest has acknowledged the doorbell interrupt */ 2347 /* TO-DO: is this really needed? */ 2348 if (ehci->usbsts & USBSTS_IAA) { 2349 DPRINTF("IAA status bit still set.\n"); 2350 break; 2351 } 2352 2353 /* check that address register has been set */ 2354 if (ehci->asynclistaddr == 0) { 2355 break; 2356 } 2357 2358 ehci_set_state(ehci, async, EST_WAITLISTHEAD); 2359 ehci_advance_state(ehci, async); 2360 2361 /* If the doorbell is set, the guest wants to make a change to the 2362 * schedule. The host controller needs to release cached data. 2363 * (section 4.8.2) 2364 */ 2365 if (ehci->usbcmd & USBCMD_IAAD) { 2366 /* Remove all unseen qhs from the async qhs queue */ 2367 ehci_queues_rip_unused(ehci, async, 1); 2368 trace_usb_ehci_doorbell_ack(); 2369 ehci->usbcmd &= ~USBCMD_IAAD; 2370 ehci_raise_irq(ehci, USBSTS_IAA); 2371 } 2372 break; 2373 2374 default: 2375 /* this should only be due to a developer mistake */ 2376 fprintf(stderr, "ehci: Bad asynchronous state %d. " 2377 "Resetting to active\n", ehci->astate); 2378 assert(0); 2379 } 2380 } 2381 2382 static void ehci_advance_periodic_state(EHCIState *ehci) 2383 { 2384 uint32_t entry; 2385 uint32_t list; 2386 const int async = 0; 2387 2388 // 4.6 2389 2390 switch(ehci_get_state(ehci, async)) { 2391 case EST_INACTIVE: 2392 if (!(ehci->frindex & 7) && ehci_periodic_enabled(ehci)) { 2393 ehci_set_state(ehci, async, EST_ACTIVE); 2394 // No break, fall through to ACTIVE 2395 } else 2396 break; 2397 2398 case EST_ACTIVE: 2399 if (!(ehci->frindex & 7) && !ehci_periodic_enabled(ehci)) { 2400 ehci_queues_rip_all(ehci, async); 2401 ehci_set_state(ehci, async, EST_INACTIVE); 2402 break; 2403 } 2404 2405 list = ehci->periodiclistbase & 0xfffff000; 2406 /* check that register has been set */ 2407 if (list == 0) { 2408 break; 2409 } 2410 list |= ((ehci->frindex & 0x1ff8) >> 1); 2411 2412 pci_dma_read(&ehci->dev, list, &entry, sizeof entry); 2413 entry = le32_to_cpu(entry); 2414 2415 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n", 2416 ehci->frindex / 8, list, entry); 2417 ehci_set_fetch_addr(ehci, async,entry); 2418 ehci_set_state(ehci, async, EST_FETCHENTRY); 2419 ehci_advance_state(ehci, async); 2420 ehci_queues_rip_unused(ehci, async, 0); 2421 break; 2422 2423 default: 2424 /* this should only be due to a developer mistake */ 2425 fprintf(stderr, "ehci: Bad periodic state %d. " 2426 "Resetting to active\n", ehci->pstate); 2427 assert(0); 2428 } 2429 } 2430 2431 static void ehci_update_frindex(EHCIState *ehci, int frames) 2432 { 2433 int i; 2434 2435 if (!ehci_enabled(ehci)) { 2436 return; 2437 } 2438 2439 for (i = 0; i < frames; i++) { 2440 ehci->frindex += 8; 2441 2442 if (ehci->frindex == 0x00002000) { 2443 ehci_raise_irq(ehci, USBSTS_FLR); 2444 } 2445 2446 if (ehci->frindex == 0x00004000) { 2447 ehci_raise_irq(ehci, USBSTS_FLR); 2448 ehci->frindex = 0; 2449 if (ehci->usbsts_frindex > 0x00004000) { 2450 ehci->usbsts_frindex -= 0x00004000; 2451 } else { 2452 ehci->usbsts_frindex = 0; 2453 } 2454 } 2455 } 2456 } 2457 2458 static void ehci_frame_timer(void *opaque) 2459 { 2460 EHCIState *ehci = opaque; 2461 int need_timer = 0; 2462 int64_t expire_time, t_now; 2463 uint64_t ns_elapsed; 2464 int frames, skipped_frames; 2465 int i; 2466 2467 t_now = qemu_get_clock_ns(vm_clock); 2468 ns_elapsed = t_now - ehci->last_run_ns; 2469 frames = ns_elapsed / FRAME_TIMER_NS; 2470 2471 if (ehci_periodic_enabled(ehci) || ehci->pstate != EST_INACTIVE) { 2472 need_timer++; 2473 ehci->async_stepdown = 0; 2474 2475 if (frames > ehci->maxframes) { 2476 skipped_frames = frames - ehci->maxframes; 2477 ehci_update_frindex(ehci, skipped_frames); 2478 ehci->last_run_ns += FRAME_TIMER_NS * skipped_frames; 2479 frames -= skipped_frames; 2480 DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames); 2481 } 2482 2483 for (i = 0; i < frames; i++) { 2484 ehci_update_frindex(ehci, 1); 2485 ehci_advance_periodic_state(ehci); 2486 ehci->last_run_ns += FRAME_TIMER_NS; 2487 } 2488 } else { 2489 if (ehci->async_stepdown < ehci->maxframes / 2) { 2490 ehci->async_stepdown++; 2491 } 2492 ehci_update_frindex(ehci, frames); 2493 ehci->last_run_ns += FRAME_TIMER_NS * frames; 2494 } 2495 2496 /* Async is not inside loop since it executes everything it can once 2497 * called 2498 */ 2499 if (ehci_async_enabled(ehci) || ehci->astate != EST_INACTIVE) { 2500 need_timer++; 2501 ehci_advance_async_state(ehci); 2502 } 2503 2504 ehci_commit_irq(ehci); 2505 if (ehci->usbsts_pending) { 2506 need_timer++; 2507 ehci->async_stepdown = 0; 2508 } 2509 2510 if (need_timer) { 2511 expire_time = t_now + (get_ticks_per_sec() 2512 * (ehci->async_stepdown+1) / FRAME_TIMER_FREQ); 2513 qemu_mod_timer(ehci->frame_timer, expire_time); 2514 } 2515 } 2516 2517 static void ehci_async_bh(void *opaque) 2518 { 2519 EHCIState *ehci = opaque; 2520 ehci_advance_async_state(ehci); 2521 } 2522 2523 static const MemoryRegionOps ehci_mem_ops = { 2524 .old_mmio = { 2525 .read = { ehci_mem_readb, ehci_mem_readw, ehci_mem_readl }, 2526 .write = { ehci_mem_writeb, ehci_mem_writew, ehci_mem_writel }, 2527 }, 2528 .endianness = DEVICE_LITTLE_ENDIAN, 2529 }; 2530 2531 static int usb_ehci_initfn(PCIDevice *dev); 2532 2533 static USBPortOps ehci_port_ops = { 2534 .attach = ehci_attach, 2535 .detach = ehci_detach, 2536 .child_detach = ehci_child_detach, 2537 .wakeup = ehci_wakeup, 2538 .complete = ehci_async_complete_packet, 2539 }; 2540 2541 static USBBusOps ehci_bus_ops = { 2542 .register_companion = ehci_register_companion, 2543 }; 2544 2545 static int usb_ehci_post_load(void *opaque, int version_id) 2546 { 2547 EHCIState *s = opaque; 2548 int i; 2549 2550 for (i = 0; i < NB_PORTS; i++) { 2551 USBPort *companion = s->companion_ports[i]; 2552 if (companion == NULL) { 2553 continue; 2554 } 2555 if (s->portsc[i] & PORTSC_POWNER) { 2556 companion->dev = s->ports[i].dev; 2557 } else { 2558 companion->dev = NULL; 2559 } 2560 } 2561 2562 return 0; 2563 } 2564 2565 static const VMStateDescription vmstate_ehci = { 2566 .name = "ehci", 2567 .version_id = 2, 2568 .minimum_version_id = 1, 2569 .post_load = usb_ehci_post_load, 2570 .fields = (VMStateField[]) { 2571 VMSTATE_PCI_DEVICE(dev, EHCIState), 2572 /* mmio registers */ 2573 VMSTATE_UINT32(usbcmd, EHCIState), 2574 VMSTATE_UINT32(usbsts, EHCIState), 2575 VMSTATE_UINT32_V(usbsts_pending, EHCIState, 2), 2576 VMSTATE_UINT32_V(usbsts_frindex, EHCIState, 2), 2577 VMSTATE_UINT32(usbintr, EHCIState), 2578 VMSTATE_UINT32(frindex, EHCIState), 2579 VMSTATE_UINT32(ctrldssegment, EHCIState), 2580 VMSTATE_UINT32(periodiclistbase, EHCIState), 2581 VMSTATE_UINT32(asynclistaddr, EHCIState), 2582 VMSTATE_UINT32(configflag, EHCIState), 2583 VMSTATE_UINT32(portsc[0], EHCIState), 2584 VMSTATE_UINT32(portsc[1], EHCIState), 2585 VMSTATE_UINT32(portsc[2], EHCIState), 2586 VMSTATE_UINT32(portsc[3], EHCIState), 2587 VMSTATE_UINT32(portsc[4], EHCIState), 2588 VMSTATE_UINT32(portsc[5], EHCIState), 2589 /* frame timer */ 2590 VMSTATE_TIMER(frame_timer, EHCIState), 2591 VMSTATE_UINT64(last_run_ns, EHCIState), 2592 VMSTATE_UINT32(async_stepdown, EHCIState), 2593 /* schedule state */ 2594 VMSTATE_UINT32(astate, EHCIState), 2595 VMSTATE_UINT32(pstate, EHCIState), 2596 VMSTATE_UINT32(a_fetch_addr, EHCIState), 2597 VMSTATE_UINT32(p_fetch_addr, EHCIState), 2598 VMSTATE_END_OF_LIST() 2599 } 2600 }; 2601 2602 static Property ehci_properties[] = { 2603 DEFINE_PROP_UINT32("maxframes", EHCIState, maxframes, 128), 2604 DEFINE_PROP_END_OF_LIST(), 2605 }; 2606 2607 static void ehci_class_init(ObjectClass *klass, void *data) 2608 { 2609 DeviceClass *dc = DEVICE_CLASS(klass); 2610 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2611 2612 k->init = usb_ehci_initfn; 2613 k->vendor_id = PCI_VENDOR_ID_INTEL; 2614 k->device_id = PCI_DEVICE_ID_INTEL_82801D; /* ich4 */ 2615 k->revision = 0x10; 2616 k->class_id = PCI_CLASS_SERIAL_USB; 2617 dc->vmsd = &vmstate_ehci; 2618 dc->props = ehci_properties; 2619 } 2620 2621 static TypeInfo ehci_info = { 2622 .name = "usb-ehci", 2623 .parent = TYPE_PCI_DEVICE, 2624 .instance_size = sizeof(EHCIState), 2625 .class_init = ehci_class_init, 2626 }; 2627 2628 static void ich9_ehci_class_init(ObjectClass *klass, void *data) 2629 { 2630 DeviceClass *dc = DEVICE_CLASS(klass); 2631 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2632 2633 k->init = usb_ehci_initfn; 2634 k->vendor_id = PCI_VENDOR_ID_INTEL; 2635 k->device_id = PCI_DEVICE_ID_INTEL_82801I_EHCI1; 2636 k->revision = 0x03; 2637 k->class_id = PCI_CLASS_SERIAL_USB; 2638 dc->vmsd = &vmstate_ehci; 2639 dc->props = ehci_properties; 2640 } 2641 2642 static TypeInfo ich9_ehci_info = { 2643 .name = "ich9-usb-ehci1", 2644 .parent = TYPE_PCI_DEVICE, 2645 .instance_size = sizeof(EHCIState), 2646 .class_init = ich9_ehci_class_init, 2647 }; 2648 2649 static int usb_ehci_initfn(PCIDevice *dev) 2650 { 2651 EHCIState *s = DO_UPCAST(EHCIState, dev, dev); 2652 uint8_t *pci_conf = s->dev.config; 2653 int i; 2654 2655 pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20); 2656 2657 /* capabilities pointer */ 2658 pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00); 2659 //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50); 2660 2661 pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); /* interrupt pin D */ 2662 pci_set_byte(&pci_conf[PCI_MIN_GNT], 0); 2663 pci_set_byte(&pci_conf[PCI_MAX_LAT], 0); 2664 2665 // pci_conf[0x50] = 0x01; // power management caps 2666 2667 pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); // release number (2.1.4) 2668 pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5) 2669 pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6) 2670 2671 pci_conf[0x64] = 0x00; 2672 pci_conf[0x65] = 0x00; 2673 pci_conf[0x66] = 0x00; 2674 pci_conf[0x67] = 0x00; 2675 pci_conf[0x68] = 0x01; 2676 pci_conf[0x69] = 0x00; 2677 pci_conf[0x6a] = 0x00; 2678 pci_conf[0x6b] = 0x00; // USBLEGSUP 2679 pci_conf[0x6c] = 0x00; 2680 pci_conf[0x6d] = 0x00; 2681 pci_conf[0x6e] = 0x00; 2682 pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS 2683 2684 // 2.2 host controller interface version 2685 s->mmio[0x00] = (uint8_t) OPREGBASE; 2686 s->mmio[0x01] = 0x00; 2687 s->mmio[0x02] = 0x00; 2688 s->mmio[0x03] = 0x01; // HC version 2689 s->mmio[0x04] = NB_PORTS; // Number of downstream ports 2690 s->mmio[0x05] = 0x00; // No companion ports at present 2691 s->mmio[0x06] = 0x00; 2692 s->mmio[0x07] = 0x00; 2693 s->mmio[0x08] = 0x80; // We can cache whole frame, not 64-bit capable 2694 s->mmio[0x09] = 0x68; // EECP 2695 s->mmio[0x0a] = 0x00; 2696 s->mmio[0x0b] = 0x00; 2697 2698 s->irq = s->dev.irq[3]; 2699 2700 usb_bus_new(&s->bus, &ehci_bus_ops, &s->dev.qdev); 2701 for(i = 0; i < NB_PORTS; i++) { 2702 usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops, 2703 USB_SPEED_MASK_HIGH); 2704 s->ports[i].dev = 0; 2705 } 2706 2707 s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s); 2708 s->async_bh = qemu_bh_new(ehci_async_bh, s); 2709 QTAILQ_INIT(&s->aqueues); 2710 QTAILQ_INIT(&s->pqueues); 2711 usb_packet_init(&s->ipacket); 2712 2713 qemu_register_reset(ehci_reset, s); 2714 2715 memory_region_init_io(&s->mem, &ehci_mem_ops, s, "ehci", MMIO_SIZE); 2716 pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem); 2717 2718 return 0; 2719 } 2720 2721 static void ehci_register_types(void) 2722 { 2723 type_register_static(&ehci_info); 2724 type_register_static(&ich9_ehci_info); 2725 } 2726 2727 type_init(ehci_register_types) 2728 2729 /* 2730 * vim: expandtab ts=4 2731 */ 2732