1 /* 2 * QEMU USB EHCI Emulation 3 * 4 * This library is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU Lesser General Public 6 * License as published by the Free Software Foundation; either 7 * version 2 of the License, or(at your option) any later version. 8 * 9 * This library is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 12 * Lesser General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "hw/usb/hcd-ehci.h" 20 21 static const VMStateDescription vmstate_ehci_sysbus = { 22 .name = "ehci-sysbus", 23 .version_id = 2, 24 .minimum_version_id = 1, 25 .fields = (VMStateField[]) { 26 VMSTATE_STRUCT(ehci, EHCISysBusState, 2, vmstate_ehci, EHCIState), 27 VMSTATE_END_OF_LIST() 28 } 29 }; 30 31 static Property ehci_sysbus_properties[] = { 32 DEFINE_PROP_UINT32("maxframes", EHCISysBusState, ehci.maxframes, 128), 33 DEFINE_PROP_END_OF_LIST(), 34 }; 35 36 static void usb_ehci_sysbus_realize(DeviceState *dev, Error **errp) 37 { 38 SysBusDevice *d = SYS_BUS_DEVICE(dev); 39 EHCISysBusState *i = SYS_BUS_EHCI(dev); 40 EHCIState *s = &i->ehci; 41 42 usb_ehci_realize(s, dev, errp); 43 sysbus_init_irq(d, &s->irq); 44 } 45 46 static void usb_ehci_sysbus_reset(DeviceState *dev) 47 { 48 SysBusDevice *d = SYS_BUS_DEVICE(dev); 49 EHCISysBusState *i = SYS_BUS_EHCI(d); 50 EHCIState *s = &i->ehci; 51 52 ehci_reset(s); 53 } 54 55 static void ehci_sysbus_init(Object *obj) 56 { 57 SysBusDevice *d = SYS_BUS_DEVICE(obj); 58 EHCISysBusState *i = SYS_BUS_EHCI(obj); 59 SysBusEHCIClass *sec = SYS_BUS_EHCI_GET_CLASS(obj); 60 EHCIState *s = &i->ehci; 61 62 s->capsbase = sec->capsbase; 63 s->opregbase = sec->opregbase; 64 s->portscbase = sec->portscbase; 65 s->portnr = sec->portnr; 66 s->as = &address_space_memory; 67 68 usb_ehci_init(s, DEVICE(obj)); 69 sysbus_init_mmio(d, &s->mem); 70 } 71 72 static void ehci_sysbus_class_init(ObjectClass *klass, void *data) 73 { 74 DeviceClass *dc = DEVICE_CLASS(klass); 75 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(klass); 76 77 sec->portscbase = 0x44; 78 sec->portnr = NB_PORTS; 79 80 dc->realize = usb_ehci_sysbus_realize; 81 dc->vmsd = &vmstate_ehci_sysbus; 82 dc->props = ehci_sysbus_properties; 83 dc->reset = usb_ehci_sysbus_reset; 84 set_bit(DEVICE_CATEGORY_USB, dc->categories); 85 } 86 87 static const TypeInfo ehci_type_info = { 88 .name = TYPE_SYS_BUS_EHCI, 89 .parent = TYPE_SYS_BUS_DEVICE, 90 .instance_size = sizeof(EHCISysBusState), 91 .instance_init = ehci_sysbus_init, 92 .abstract = true, 93 .class_init = ehci_sysbus_class_init, 94 .class_size = sizeof(SysBusEHCIClass), 95 }; 96 97 static void ehci_xlnx_class_init(ObjectClass *oc, void *data) 98 { 99 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); 100 DeviceClass *dc = DEVICE_CLASS(oc); 101 102 set_bit(DEVICE_CATEGORY_USB, dc->categories); 103 sec->capsbase = 0x100; 104 sec->opregbase = 0x140; 105 } 106 107 static const TypeInfo ehci_xlnx_type_info = { 108 .name = "xlnx,ps7-usb", 109 .parent = TYPE_SYS_BUS_EHCI, 110 .class_init = ehci_xlnx_class_init, 111 }; 112 113 static void ehci_exynos4210_class_init(ObjectClass *oc, void *data) 114 { 115 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); 116 DeviceClass *dc = DEVICE_CLASS(oc); 117 118 sec->capsbase = 0x0; 119 sec->opregbase = 0x10; 120 set_bit(DEVICE_CATEGORY_USB, dc->categories); 121 } 122 123 static const TypeInfo ehci_exynos4210_type_info = { 124 .name = TYPE_EXYNOS4210_EHCI, 125 .parent = TYPE_SYS_BUS_EHCI, 126 .class_init = ehci_exynos4210_class_init, 127 }; 128 129 static void ehci_tegra2_class_init(ObjectClass *oc, void *data) 130 { 131 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); 132 DeviceClass *dc = DEVICE_CLASS(oc); 133 134 sec->capsbase = 0x100; 135 sec->opregbase = 0x140; 136 set_bit(DEVICE_CATEGORY_USB, dc->categories); 137 } 138 139 static const TypeInfo ehci_tegra2_type_info = { 140 .name = TYPE_TEGRA2_EHCI, 141 .parent = TYPE_SYS_BUS_EHCI, 142 .class_init = ehci_tegra2_class_init, 143 }; 144 145 static void ehci_ppc4xx_init(Object *o) 146 { 147 EHCISysBusState *s = SYS_BUS_EHCI(o); 148 149 s->ehci.companion_enable = true; 150 } 151 152 static void ehci_ppc4xx_class_init(ObjectClass *oc, void *data) 153 { 154 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); 155 DeviceClass *dc = DEVICE_CLASS(oc); 156 157 sec->capsbase = 0x0; 158 sec->opregbase = 0x10; 159 set_bit(DEVICE_CATEGORY_USB, dc->categories); 160 } 161 162 static const TypeInfo ehci_ppc4xx_type_info = { 163 .name = TYPE_PPC4xx_EHCI, 164 .parent = TYPE_SYS_BUS_EHCI, 165 .class_init = ehci_ppc4xx_class_init, 166 .instance_init = ehci_ppc4xx_init, 167 }; 168 169 /* 170 * Faraday FUSBH200 USB 2.0 EHCI 171 */ 172 173 /** 174 * FUSBH200EHCIRegs: 175 * @FUSBH200_REG_EOF_ASTR: EOF/Async. Sleep Timer Register 176 * @FUSBH200_REG_BMCSR: Bus Monitor Control/Status Register 177 */ 178 enum FUSBH200EHCIRegs { 179 FUSBH200_REG_EOF_ASTR = 0x34, 180 FUSBH200_REG_BMCSR = 0x40, 181 }; 182 183 static uint64_t fusbh200_ehci_read(void *opaque, hwaddr addr, unsigned size) 184 { 185 EHCIState *s = opaque; 186 hwaddr off = s->opregbase + s->portscbase + 4 * s->portnr + addr; 187 188 switch (off) { 189 case FUSBH200_REG_EOF_ASTR: 190 return 0x00000041; 191 case FUSBH200_REG_BMCSR: 192 /* High-Speed, VBUS valid, interrupt level-high active */ 193 return (2 << 9) | (1 << 8) | (1 << 3); 194 } 195 196 return 0; 197 } 198 199 static void fusbh200_ehci_write(void *opaque, hwaddr addr, uint64_t val, 200 unsigned size) 201 { 202 } 203 204 static const MemoryRegionOps fusbh200_ehci_mmio_ops = { 205 .read = fusbh200_ehci_read, 206 .write = fusbh200_ehci_write, 207 .valid.min_access_size = 4, 208 .valid.max_access_size = 4, 209 .endianness = DEVICE_LITTLE_ENDIAN, 210 }; 211 212 static void fusbh200_ehci_init(Object *obj) 213 { 214 EHCISysBusState *i = SYS_BUS_EHCI(obj); 215 FUSBH200EHCIState *f = FUSBH200_EHCI(obj); 216 EHCIState *s = &i->ehci; 217 218 memory_region_init_io(&f->mem_vendor, OBJECT(f), &fusbh200_ehci_mmio_ops, s, 219 "fusbh200", 0x4c); 220 memory_region_add_subregion(&s->mem, 221 s->opregbase + s->portscbase + 4 * s->portnr, 222 &f->mem_vendor); 223 } 224 225 static void fusbh200_ehci_class_init(ObjectClass *oc, void *data) 226 { 227 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); 228 DeviceClass *dc = DEVICE_CLASS(oc); 229 230 sec->capsbase = 0x0; 231 sec->opregbase = 0x10; 232 sec->portscbase = 0x20; 233 sec->portnr = 1; 234 set_bit(DEVICE_CATEGORY_USB, dc->categories); 235 } 236 237 static const TypeInfo ehci_fusbh200_type_info = { 238 .name = TYPE_FUSBH200_EHCI, 239 .parent = TYPE_SYS_BUS_EHCI, 240 .instance_size = sizeof(FUSBH200EHCIState), 241 .instance_init = fusbh200_ehci_init, 242 .class_init = fusbh200_ehci_class_init, 243 }; 244 245 static void ehci_sysbus_register_types(void) 246 { 247 type_register_static(&ehci_type_info); 248 type_register_static(&ehci_xlnx_type_info); 249 type_register_static(&ehci_exynos4210_type_info); 250 type_register_static(&ehci_tegra2_type_info); 251 type_register_static(&ehci_ppc4xx_type_info); 252 type_register_static(&ehci_fusbh200_type_info); 253 } 254 255 type_init(ehci_sysbus_register_types) 256