1 /* 2 * QEMU USB EHCI Emulation 3 * 4 * This library is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU Lesser General Public 6 * License as published by the Free Software Foundation; either 7 * version 2.1 of the License, or (at your option) any later version. 8 * 9 * This library is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 12 * Lesser General Public License for more details. 13 * 14 * You should have received a copy of the GNU Lesser General Public License 15 * along with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "hw/usb/hcd-ehci.h" 20 #include "migration/vmstate.h" 21 #include "qemu/module.h" 22 23 static const VMStateDescription vmstate_ehci_sysbus = { 24 .name = "ehci-sysbus", 25 .version_id = 2, 26 .minimum_version_id = 1, 27 .fields = (VMStateField[]) { 28 VMSTATE_STRUCT(ehci, EHCISysBusState, 2, vmstate_ehci, EHCIState), 29 VMSTATE_END_OF_LIST() 30 } 31 }; 32 33 static Property ehci_sysbus_properties[] = { 34 DEFINE_PROP_UINT32("maxframes", EHCISysBusState, ehci.maxframes, 128), 35 DEFINE_PROP_END_OF_LIST(), 36 }; 37 38 static void usb_ehci_sysbus_realize(DeviceState *dev, Error **errp) 39 { 40 SysBusDevice *d = SYS_BUS_DEVICE(dev); 41 EHCISysBusState *i = SYS_BUS_EHCI(dev); 42 EHCIState *s = &i->ehci; 43 44 usb_ehci_realize(s, dev, errp); 45 sysbus_init_irq(d, &s->irq); 46 } 47 48 static void usb_ehci_sysbus_reset(DeviceState *dev) 49 { 50 SysBusDevice *d = SYS_BUS_DEVICE(dev); 51 EHCISysBusState *i = SYS_BUS_EHCI(d); 52 EHCIState *s = &i->ehci; 53 54 ehci_reset(s); 55 } 56 57 static void ehci_sysbus_init(Object *obj) 58 { 59 SysBusDevice *d = SYS_BUS_DEVICE(obj); 60 EHCISysBusState *i = SYS_BUS_EHCI(obj); 61 SysBusEHCIClass *sec = SYS_BUS_EHCI_GET_CLASS(obj); 62 EHCIState *s = &i->ehci; 63 64 s->capsbase = sec->capsbase; 65 s->opregbase = sec->opregbase; 66 s->portscbase = sec->portscbase; 67 s->portnr = sec->portnr; 68 s->as = &address_space_memory; 69 70 usb_ehci_init(s, DEVICE(obj)); 71 sysbus_init_mmio(d, &s->mem); 72 } 73 74 static void ehci_sysbus_class_init(ObjectClass *klass, void *data) 75 { 76 DeviceClass *dc = DEVICE_CLASS(klass); 77 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(klass); 78 79 sec->portscbase = 0x44; 80 sec->portnr = NB_PORTS; 81 82 dc->realize = usb_ehci_sysbus_realize; 83 dc->vmsd = &vmstate_ehci_sysbus; 84 dc->props = ehci_sysbus_properties; 85 dc->reset = usb_ehci_sysbus_reset; 86 set_bit(DEVICE_CATEGORY_USB, dc->categories); 87 } 88 89 static const TypeInfo ehci_type_info = { 90 .name = TYPE_SYS_BUS_EHCI, 91 .parent = TYPE_SYS_BUS_DEVICE, 92 .instance_size = sizeof(EHCISysBusState), 93 .instance_init = ehci_sysbus_init, 94 .abstract = true, 95 .class_init = ehci_sysbus_class_init, 96 .class_size = sizeof(SysBusEHCIClass), 97 }; 98 99 static void ehci_platform_class_init(ObjectClass *oc, void *data) 100 { 101 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); 102 DeviceClass *dc = DEVICE_CLASS(oc); 103 104 sec->capsbase = 0x0; 105 sec->opregbase = 0x20; 106 set_bit(DEVICE_CATEGORY_USB, dc->categories); 107 } 108 109 static const TypeInfo ehci_platform_type_info = { 110 .name = TYPE_PLATFORM_EHCI, 111 .parent = TYPE_SYS_BUS_EHCI, 112 .class_init = ehci_platform_class_init, 113 }; 114 115 static void ehci_xlnx_class_init(ObjectClass *oc, void *data) 116 { 117 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); 118 DeviceClass *dc = DEVICE_CLASS(oc); 119 120 set_bit(DEVICE_CATEGORY_USB, dc->categories); 121 sec->capsbase = 0x100; 122 sec->opregbase = 0x140; 123 } 124 125 static const TypeInfo ehci_xlnx_type_info = { 126 .name = "xlnx,ps7-usb", 127 .parent = TYPE_SYS_BUS_EHCI, 128 .class_init = ehci_xlnx_class_init, 129 }; 130 131 static void ehci_exynos4210_class_init(ObjectClass *oc, void *data) 132 { 133 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); 134 DeviceClass *dc = DEVICE_CLASS(oc); 135 136 sec->capsbase = 0x0; 137 sec->opregbase = 0x10; 138 set_bit(DEVICE_CATEGORY_USB, dc->categories); 139 } 140 141 static const TypeInfo ehci_exynos4210_type_info = { 142 .name = TYPE_EXYNOS4210_EHCI, 143 .parent = TYPE_SYS_BUS_EHCI, 144 .class_init = ehci_exynos4210_class_init, 145 }; 146 147 static void ehci_tegra2_class_init(ObjectClass *oc, void *data) 148 { 149 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); 150 DeviceClass *dc = DEVICE_CLASS(oc); 151 152 sec->capsbase = 0x100; 153 sec->opregbase = 0x140; 154 set_bit(DEVICE_CATEGORY_USB, dc->categories); 155 } 156 157 static const TypeInfo ehci_tegra2_type_info = { 158 .name = TYPE_TEGRA2_EHCI, 159 .parent = TYPE_SYS_BUS_EHCI, 160 .class_init = ehci_tegra2_class_init, 161 }; 162 163 static void ehci_ppc4xx_init(Object *o) 164 { 165 EHCISysBusState *s = SYS_BUS_EHCI(o); 166 167 s->ehci.companion_enable = true; 168 } 169 170 static void ehci_ppc4xx_class_init(ObjectClass *oc, void *data) 171 { 172 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); 173 DeviceClass *dc = DEVICE_CLASS(oc); 174 175 sec->capsbase = 0x0; 176 sec->opregbase = 0x10; 177 set_bit(DEVICE_CATEGORY_USB, dc->categories); 178 } 179 180 static const TypeInfo ehci_ppc4xx_type_info = { 181 .name = TYPE_PPC4xx_EHCI, 182 .parent = TYPE_SYS_BUS_EHCI, 183 .class_init = ehci_ppc4xx_class_init, 184 .instance_init = ehci_ppc4xx_init, 185 }; 186 187 /* 188 * Faraday FUSBH200 USB 2.0 EHCI 189 */ 190 191 /** 192 * FUSBH200EHCIRegs: 193 * @FUSBH200_REG_EOF_ASTR: EOF/Async. Sleep Timer Register 194 * @FUSBH200_REG_BMCSR: Bus Monitor Control/Status Register 195 */ 196 enum FUSBH200EHCIRegs { 197 FUSBH200_REG_EOF_ASTR = 0x34, 198 FUSBH200_REG_BMCSR = 0x40, 199 }; 200 201 static uint64_t fusbh200_ehci_read(void *opaque, hwaddr addr, unsigned size) 202 { 203 EHCIState *s = opaque; 204 hwaddr off = s->opregbase + s->portscbase + 4 * s->portnr + addr; 205 206 switch (off) { 207 case FUSBH200_REG_EOF_ASTR: 208 return 0x00000041; 209 case FUSBH200_REG_BMCSR: 210 /* High-Speed, VBUS valid, interrupt level-high active */ 211 return (2 << 9) | (1 << 8) | (1 << 3); 212 } 213 214 return 0; 215 } 216 217 static void fusbh200_ehci_write(void *opaque, hwaddr addr, uint64_t val, 218 unsigned size) 219 { 220 } 221 222 static const MemoryRegionOps fusbh200_ehci_mmio_ops = { 223 .read = fusbh200_ehci_read, 224 .write = fusbh200_ehci_write, 225 .valid.min_access_size = 4, 226 .valid.max_access_size = 4, 227 .endianness = DEVICE_LITTLE_ENDIAN, 228 }; 229 230 static void fusbh200_ehci_init(Object *obj) 231 { 232 EHCISysBusState *i = SYS_BUS_EHCI(obj); 233 FUSBH200EHCIState *f = FUSBH200_EHCI(obj); 234 EHCIState *s = &i->ehci; 235 236 memory_region_init_io(&f->mem_vendor, OBJECT(f), &fusbh200_ehci_mmio_ops, s, 237 "fusbh200", 0x4c); 238 memory_region_add_subregion(&s->mem, 239 s->opregbase + s->portscbase + 4 * s->portnr, 240 &f->mem_vendor); 241 } 242 243 static void fusbh200_ehci_class_init(ObjectClass *oc, void *data) 244 { 245 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); 246 DeviceClass *dc = DEVICE_CLASS(oc); 247 248 sec->capsbase = 0x0; 249 sec->opregbase = 0x10; 250 sec->portscbase = 0x20; 251 sec->portnr = 1; 252 set_bit(DEVICE_CATEGORY_USB, dc->categories); 253 } 254 255 static const TypeInfo ehci_fusbh200_type_info = { 256 .name = TYPE_FUSBH200_EHCI, 257 .parent = TYPE_SYS_BUS_EHCI, 258 .instance_size = sizeof(FUSBH200EHCIState), 259 .instance_init = fusbh200_ehci_init, 260 .class_init = fusbh200_ehci_class_init, 261 }; 262 263 static void ehci_sysbus_register_types(void) 264 { 265 type_register_static(&ehci_type_info); 266 type_register_static(&ehci_platform_type_info); 267 type_register_static(&ehci_xlnx_type_info); 268 type_register_static(&ehci_exynos4210_type_info); 269 type_register_static(&ehci_tegra2_type_info); 270 type_register_static(&ehci_ppc4xx_type_info); 271 type_register_static(&ehci_fusbh200_type_info); 272 } 273 274 type_init(ehci_sysbus_register_types) 275