1 /* 2 * QEMU USB EHCI Emulation 3 * 4 * This library is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU Lesser General Public 6 * License as published by the Free Software Foundation; either 7 * version 2 of the License, or(at your option) any later version. 8 * 9 * This library is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 12 * Lesser General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include "hw/usb/hcd-ehci.h" 19 20 static const VMStateDescription vmstate_ehci_sysbus = { 21 .name = "ehci-sysbus", 22 .version_id = 2, 23 .minimum_version_id = 1, 24 .fields = (VMStateField[]) { 25 VMSTATE_STRUCT(ehci, EHCISysBusState, 2, vmstate_ehci, EHCIState), 26 VMSTATE_END_OF_LIST() 27 } 28 }; 29 30 static Property ehci_sysbus_properties[] = { 31 DEFINE_PROP_UINT32("maxframes", EHCISysBusState, ehci.maxframes, 128), 32 DEFINE_PROP_END_OF_LIST(), 33 }; 34 35 static void usb_ehci_sysbus_realize(DeviceState *dev, Error **errp) 36 { 37 SysBusDevice *d = SYS_BUS_DEVICE(dev); 38 EHCISysBusState *i = SYS_BUS_EHCI(dev); 39 EHCIState *s = &i->ehci; 40 41 usb_ehci_realize(s, dev, errp); 42 sysbus_init_irq(d, &s->irq); 43 } 44 45 static void ehci_sysbus_init(Object *obj) 46 { 47 SysBusDevice *d = SYS_BUS_DEVICE(obj); 48 EHCISysBusState *i = SYS_BUS_EHCI(obj); 49 SysBusEHCIClass *sec = SYS_BUS_EHCI_GET_CLASS(obj); 50 EHCIState *s = &i->ehci; 51 52 s->capsbase = sec->capsbase; 53 s->opregbase = sec->opregbase; 54 s->portscbase = sec->portscbase; 55 s->portnr = sec->portnr; 56 s->as = &address_space_memory; 57 58 usb_ehci_init(s, DEVICE(obj)); 59 sysbus_init_mmio(d, &s->mem); 60 } 61 62 static void ehci_sysbus_class_init(ObjectClass *klass, void *data) 63 { 64 DeviceClass *dc = DEVICE_CLASS(klass); 65 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(klass); 66 67 sec->portscbase = 0x44; 68 sec->portnr = NB_PORTS; 69 70 dc->realize = usb_ehci_sysbus_realize; 71 dc->vmsd = &vmstate_ehci_sysbus; 72 dc->props = ehci_sysbus_properties; 73 set_bit(DEVICE_CATEGORY_USB, dc->categories); 74 } 75 76 static const TypeInfo ehci_type_info = { 77 .name = TYPE_SYS_BUS_EHCI, 78 .parent = TYPE_SYS_BUS_DEVICE, 79 .instance_size = sizeof(EHCISysBusState), 80 .instance_init = ehci_sysbus_init, 81 .abstract = true, 82 .class_init = ehci_sysbus_class_init, 83 .class_size = sizeof(SysBusEHCIClass), 84 }; 85 86 static void ehci_xlnx_class_init(ObjectClass *oc, void *data) 87 { 88 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); 89 DeviceClass *dc = DEVICE_CLASS(oc); 90 91 set_bit(DEVICE_CATEGORY_USB, dc->categories); 92 sec->capsbase = 0x100; 93 sec->opregbase = 0x140; 94 } 95 96 static const TypeInfo ehci_xlnx_type_info = { 97 .name = "xlnx,ps7-usb", 98 .parent = TYPE_SYS_BUS_EHCI, 99 .class_init = ehci_xlnx_class_init, 100 }; 101 102 static void ehci_exynos4210_class_init(ObjectClass *oc, void *data) 103 { 104 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); 105 DeviceClass *dc = DEVICE_CLASS(oc); 106 107 sec->capsbase = 0x0; 108 sec->opregbase = 0x10; 109 set_bit(DEVICE_CATEGORY_USB, dc->categories); 110 } 111 112 static const TypeInfo ehci_exynos4210_type_info = { 113 .name = TYPE_EXYNOS4210_EHCI, 114 .parent = TYPE_SYS_BUS_EHCI, 115 .class_init = ehci_exynos4210_class_init, 116 }; 117 118 static void ehci_tegra2_class_init(ObjectClass *oc, void *data) 119 { 120 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); 121 DeviceClass *dc = DEVICE_CLASS(oc); 122 123 sec->capsbase = 0x100; 124 sec->opregbase = 0x140; 125 set_bit(DEVICE_CATEGORY_USB, dc->categories); 126 } 127 128 static const TypeInfo ehci_tegra2_type_info = { 129 .name = TYPE_TEGRA2_EHCI, 130 .parent = TYPE_SYS_BUS_EHCI, 131 .class_init = ehci_tegra2_class_init, 132 }; 133 134 /* 135 * Faraday FUSBH200 USB 2.0 EHCI 136 */ 137 138 /** 139 * FUSBH200EHCIRegs: 140 * @FUSBH200_REG_EOF_ASTR: EOF/Async. Sleep Timer Register 141 * @FUSBH200_REG_BMCSR: Bus Monitor Control/Status Register 142 */ 143 enum FUSBH200EHCIRegs { 144 FUSBH200_REG_EOF_ASTR = 0x34, 145 FUSBH200_REG_BMCSR = 0x40, 146 }; 147 148 static uint64_t fusbh200_ehci_read(void *opaque, hwaddr addr, unsigned size) 149 { 150 EHCIState *s = opaque; 151 hwaddr off = s->opregbase + s->portscbase + 4 * s->portnr + addr; 152 153 switch (off) { 154 case FUSBH200_REG_EOF_ASTR: 155 return 0x00000041; 156 case FUSBH200_REG_BMCSR: 157 /* High-Speed, VBUS valid, interrupt level-high active */ 158 return (2 << 9) | (1 << 8) | (1 << 3); 159 } 160 161 return 0; 162 } 163 164 static void fusbh200_ehci_write(void *opaque, hwaddr addr, uint64_t val, 165 unsigned size) 166 { 167 } 168 169 static const MemoryRegionOps fusbh200_ehci_mmio_ops = { 170 .read = fusbh200_ehci_read, 171 .write = fusbh200_ehci_write, 172 .valid.min_access_size = 4, 173 .valid.max_access_size = 4, 174 .endianness = DEVICE_LITTLE_ENDIAN, 175 }; 176 177 static void fusbh200_ehci_init(Object *obj) 178 { 179 EHCISysBusState *i = SYS_BUS_EHCI(obj); 180 FUSBH200EHCIState *f = FUSBH200_EHCI(obj); 181 EHCIState *s = &i->ehci; 182 183 memory_region_init_io(&f->mem_vendor, OBJECT(f), &fusbh200_ehci_mmio_ops, s, 184 "fusbh200", 0x4c); 185 memory_region_add_subregion(&s->mem, 186 s->opregbase + s->portscbase + 4 * s->portnr, 187 &f->mem_vendor); 188 } 189 190 static void fusbh200_ehci_class_init(ObjectClass *oc, void *data) 191 { 192 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); 193 DeviceClass *dc = DEVICE_CLASS(oc); 194 195 sec->capsbase = 0x0; 196 sec->opregbase = 0x10; 197 sec->portscbase = 0x20; 198 sec->portnr = 1; 199 set_bit(DEVICE_CATEGORY_USB, dc->categories); 200 } 201 202 static const TypeInfo ehci_fusbh200_type_info = { 203 .name = TYPE_FUSBH200_EHCI, 204 .parent = TYPE_SYS_BUS_EHCI, 205 .instance_size = sizeof(FUSBH200EHCIState), 206 .instance_init = fusbh200_ehci_init, 207 .class_init = fusbh200_ehci_class_init, 208 }; 209 210 static void ehci_sysbus_register_types(void) 211 { 212 type_register_static(&ehci_type_info); 213 type_register_static(&ehci_xlnx_type_info); 214 type_register_static(&ehci_exynos4210_type_info); 215 type_register_static(&ehci_tegra2_type_info); 216 type_register_static(&ehci_fusbh200_type_info); 217 } 218 219 type_init(ehci_sysbus_register_types) 220