1 /* 2 * QEMU USB EHCI Emulation 3 * 4 * This library is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU Lesser General Public 6 * License as published by the Free Software Foundation; either 7 * version 2.1 of the License, or (at your option) any later version. 8 * 9 * This library is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 12 * Lesser General Public License for more details. 13 * 14 * You should have received a copy of the GNU Lesser General Public License 15 * along with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "hw/qdev-properties.h" 20 #include "hw/usb/hcd-ehci.h" 21 #include "migration/vmstate.h" 22 #include "qemu/module.h" 23 24 static const VMStateDescription vmstate_ehci_sysbus = { 25 .name = "ehci-sysbus", 26 .version_id = 2, 27 .minimum_version_id = 1, 28 .fields = (VMStateField[]) { 29 VMSTATE_STRUCT(ehci, EHCISysBusState, 2, vmstate_ehci, EHCIState), 30 VMSTATE_END_OF_LIST() 31 } 32 }; 33 34 static Property ehci_sysbus_properties[] = { 35 DEFINE_PROP_UINT32("maxframes", EHCISysBusState, ehci.maxframes, 128), 36 DEFINE_PROP_BOOL("companion-enable", EHCISysBusState, ehci.companion_enable, 37 false), 38 DEFINE_PROP_END_OF_LIST(), 39 }; 40 41 static void usb_ehci_sysbus_realize(DeviceState *dev, Error **errp) 42 { 43 SysBusDevice *d = SYS_BUS_DEVICE(dev); 44 EHCISysBusState *i = SYS_BUS_EHCI(dev); 45 EHCIState *s = &i->ehci; 46 47 usb_ehci_realize(s, dev, errp); 48 sysbus_init_irq(d, &s->irq); 49 } 50 51 static void usb_ehci_sysbus_reset(DeviceState *dev) 52 { 53 SysBusDevice *d = SYS_BUS_DEVICE(dev); 54 EHCISysBusState *i = SYS_BUS_EHCI(d); 55 EHCIState *s = &i->ehci; 56 57 ehci_reset(s); 58 } 59 60 static void ehci_sysbus_init(Object *obj) 61 { 62 SysBusDevice *d = SYS_BUS_DEVICE(obj); 63 EHCISysBusState *i = SYS_BUS_EHCI(obj); 64 SysBusEHCIClass *sec = SYS_BUS_EHCI_GET_CLASS(obj); 65 EHCIState *s = &i->ehci; 66 67 s->capsbase = sec->capsbase; 68 s->opregbase = sec->opregbase; 69 s->portscbase = sec->portscbase; 70 s->portnr = sec->portnr; 71 s->as = &address_space_memory; 72 73 usb_ehci_init(s, DEVICE(obj)); 74 sysbus_init_mmio(d, &s->mem); 75 } 76 77 static void ehci_sysbus_class_init(ObjectClass *klass, void *data) 78 { 79 DeviceClass *dc = DEVICE_CLASS(klass); 80 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(klass); 81 82 sec->portscbase = 0x44; 83 sec->portnr = NB_PORTS; 84 85 dc->realize = usb_ehci_sysbus_realize; 86 dc->vmsd = &vmstate_ehci_sysbus; 87 device_class_set_props(dc, ehci_sysbus_properties); 88 dc->reset = usb_ehci_sysbus_reset; 89 set_bit(DEVICE_CATEGORY_USB, dc->categories); 90 } 91 92 static const TypeInfo ehci_type_info = { 93 .name = TYPE_SYS_BUS_EHCI, 94 .parent = TYPE_SYS_BUS_DEVICE, 95 .instance_size = sizeof(EHCISysBusState), 96 .instance_init = ehci_sysbus_init, 97 .abstract = true, 98 .class_init = ehci_sysbus_class_init, 99 .class_size = sizeof(SysBusEHCIClass), 100 }; 101 102 static void ehci_platform_class_init(ObjectClass *oc, void *data) 103 { 104 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); 105 DeviceClass *dc = DEVICE_CLASS(oc); 106 107 sec->capsbase = 0x0; 108 sec->opregbase = 0x20; 109 set_bit(DEVICE_CATEGORY_USB, dc->categories); 110 } 111 112 static const TypeInfo ehci_platform_type_info = { 113 .name = TYPE_PLATFORM_EHCI, 114 .parent = TYPE_SYS_BUS_EHCI, 115 .class_init = ehci_platform_class_init, 116 }; 117 118 static void ehci_exynos4210_class_init(ObjectClass *oc, void *data) 119 { 120 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); 121 DeviceClass *dc = DEVICE_CLASS(oc); 122 123 sec->capsbase = 0x0; 124 sec->opregbase = 0x10; 125 set_bit(DEVICE_CATEGORY_USB, dc->categories); 126 } 127 128 static const TypeInfo ehci_exynos4210_type_info = { 129 .name = TYPE_EXYNOS4210_EHCI, 130 .parent = TYPE_SYS_BUS_EHCI, 131 .class_init = ehci_exynos4210_class_init, 132 }; 133 134 static void ehci_aw_h3_class_init(ObjectClass *oc, void *data) 135 { 136 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); 137 DeviceClass *dc = DEVICE_CLASS(oc); 138 139 sec->capsbase = 0x0; 140 sec->opregbase = 0x10; 141 set_bit(DEVICE_CATEGORY_USB, dc->categories); 142 } 143 144 static const TypeInfo ehci_aw_h3_type_info = { 145 .name = TYPE_AW_H3_EHCI, 146 .parent = TYPE_SYS_BUS_EHCI, 147 .class_init = ehci_aw_h3_class_init, 148 }; 149 150 static void ehci_npcm7xx_class_init(ObjectClass *oc, void *data) 151 { 152 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); 153 DeviceClass *dc = DEVICE_CLASS(oc); 154 155 sec->capsbase = 0x0; 156 sec->opregbase = 0x10; 157 sec->portscbase = 0x44; 158 sec->portnr = 1; 159 set_bit(DEVICE_CATEGORY_USB, dc->categories); 160 } 161 162 static const TypeInfo ehci_npcm7xx_type_info = { 163 .name = TYPE_NPCM7XX_EHCI, 164 .parent = TYPE_SYS_BUS_EHCI, 165 .class_init = ehci_npcm7xx_class_init, 166 }; 167 168 static void ehci_tegra2_class_init(ObjectClass *oc, void *data) 169 { 170 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); 171 DeviceClass *dc = DEVICE_CLASS(oc); 172 173 sec->capsbase = 0x100; 174 sec->opregbase = 0x140; 175 set_bit(DEVICE_CATEGORY_USB, dc->categories); 176 } 177 178 static const TypeInfo ehci_tegra2_type_info = { 179 .name = TYPE_TEGRA2_EHCI, 180 .parent = TYPE_SYS_BUS_EHCI, 181 .class_init = ehci_tegra2_class_init, 182 }; 183 184 static void ehci_ppc4xx_init(Object *o) 185 { 186 EHCISysBusState *s = SYS_BUS_EHCI(o); 187 188 s->ehci.companion_enable = true; 189 } 190 191 static void ehci_ppc4xx_class_init(ObjectClass *oc, void *data) 192 { 193 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); 194 DeviceClass *dc = DEVICE_CLASS(oc); 195 196 sec->capsbase = 0x0; 197 sec->opregbase = 0x10; 198 set_bit(DEVICE_CATEGORY_USB, dc->categories); 199 } 200 201 static const TypeInfo ehci_ppc4xx_type_info = { 202 .name = TYPE_PPC4xx_EHCI, 203 .parent = TYPE_SYS_BUS_EHCI, 204 .class_init = ehci_ppc4xx_class_init, 205 .instance_init = ehci_ppc4xx_init, 206 }; 207 208 /* 209 * Faraday FUSBH200 USB 2.0 EHCI 210 */ 211 212 /** 213 * FUSBH200EHCIRegs: 214 * @FUSBH200_REG_EOF_ASTR: EOF/Async. Sleep Timer Register 215 * @FUSBH200_REG_BMCSR: Bus Monitor Control/Status Register 216 */ 217 enum FUSBH200EHCIRegs { 218 FUSBH200_REG_EOF_ASTR = 0x34, 219 FUSBH200_REG_BMCSR = 0x40, 220 }; 221 222 static uint64_t fusbh200_ehci_read(void *opaque, hwaddr addr, unsigned size) 223 { 224 EHCIState *s = opaque; 225 hwaddr off = s->opregbase + s->portscbase + 4 * s->portnr + addr; 226 227 switch (off) { 228 case FUSBH200_REG_EOF_ASTR: 229 return 0x00000041; 230 case FUSBH200_REG_BMCSR: 231 /* High-Speed, VBUS valid, interrupt level-high active */ 232 return (2 << 9) | (1 << 8) | (1 << 3); 233 } 234 235 return 0; 236 } 237 238 static void fusbh200_ehci_write(void *opaque, hwaddr addr, uint64_t val, 239 unsigned size) 240 { 241 } 242 243 static const MemoryRegionOps fusbh200_ehci_mmio_ops = { 244 .read = fusbh200_ehci_read, 245 .write = fusbh200_ehci_write, 246 .valid.min_access_size = 4, 247 .valid.max_access_size = 4, 248 .endianness = DEVICE_LITTLE_ENDIAN, 249 }; 250 251 static void fusbh200_ehci_init(Object *obj) 252 { 253 EHCISysBusState *i = SYS_BUS_EHCI(obj); 254 FUSBH200EHCIState *f = FUSBH200_EHCI(obj); 255 EHCIState *s = &i->ehci; 256 257 memory_region_init_io(&f->mem_vendor, OBJECT(f), &fusbh200_ehci_mmio_ops, s, 258 "fusbh200", 0x4c); 259 memory_region_add_subregion(&s->mem, 260 s->opregbase + s->portscbase + 4 * s->portnr, 261 &f->mem_vendor); 262 } 263 264 static void fusbh200_ehci_class_init(ObjectClass *oc, void *data) 265 { 266 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); 267 DeviceClass *dc = DEVICE_CLASS(oc); 268 269 sec->capsbase = 0x0; 270 sec->opregbase = 0x10; 271 sec->portscbase = 0x20; 272 sec->portnr = 1; 273 set_bit(DEVICE_CATEGORY_USB, dc->categories); 274 } 275 276 static const TypeInfo ehci_fusbh200_type_info = { 277 .name = TYPE_FUSBH200_EHCI, 278 .parent = TYPE_SYS_BUS_EHCI, 279 .instance_size = sizeof(FUSBH200EHCIState), 280 .instance_init = fusbh200_ehci_init, 281 .class_init = fusbh200_ehci_class_init, 282 }; 283 284 static void ehci_sysbus_register_types(void) 285 { 286 type_register_static(&ehci_type_info); 287 type_register_static(&ehci_platform_type_info); 288 type_register_static(&ehci_exynos4210_type_info); 289 type_register_static(&ehci_aw_h3_type_info); 290 type_register_static(&ehci_npcm7xx_type_info); 291 type_register_static(&ehci_tegra2_type_info); 292 type_register_static(&ehci_ppc4xx_type_info); 293 type_register_static(&ehci_fusbh200_type_info); 294 } 295 296 type_init(ehci_sysbus_register_types) 297