1 /* 2 * QEMU model of the USB DWC3 host controller emulation. 3 * 4 * This model defines global register space of DWC3 controller. Global 5 * registers control the AXI/AHB interfaces properties, external FIFO support 6 * and event count support. All of which are unimplemented at present. We are 7 * only supporting core reset and read of ID register. 8 * 9 * Copyright (c) 2020 Xilinx Inc. Vikram Garhwal<fnu.vikram@xilinx.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a copy 12 * of this software and associated documentation files (the "Software"), to deal 13 * in the Software without restriction, including without limitation the rights 14 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 15 * copies of the Software, and to permit persons to whom the Software is 16 * furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice shall be included in 19 * all copies or substantial portions of the Software. 20 * 21 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 22 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 23 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 24 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 25 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 26 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 27 * THE SOFTWARE. 28 */ 29 30 #include "qemu/osdep.h" 31 #include "hw/sysbus.h" 32 #include "hw/register.h" 33 #include "qemu/bitops.h" 34 #include "qemu/log.h" 35 #include "qom/object.h" 36 #include "migration/vmstate.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/usb/hcd-dwc3.h" 39 #include "qapi/error.h" 40 41 #ifndef USB_DWC3_ERR_DEBUG 42 #define USB_DWC3_ERR_DEBUG 0 43 #endif 44 45 #define HOST_MODE 1 46 #define FIFO_LEN 0x1000 47 48 REG32(GSBUSCFG0, 0x00) 49 FIELD(GSBUSCFG0, DATRDREQINFO, 28, 4) 50 FIELD(GSBUSCFG0, DESRDREQINFO, 24, 4) 51 FIELD(GSBUSCFG0, DATWRREQINFO, 20, 4) 52 FIELD(GSBUSCFG0, DESWRREQINFO, 16, 4) 53 FIELD(GSBUSCFG0, RESERVED_15_12, 12, 4) 54 FIELD(GSBUSCFG0, DATBIGEND, 11, 1) 55 FIELD(GSBUSCFG0, DESBIGEND, 10, 1) 56 FIELD(GSBUSCFG0, RESERVED_9_8, 8, 2) 57 FIELD(GSBUSCFG0, INCR256BRSTENA, 7, 1) 58 FIELD(GSBUSCFG0, INCR128BRSTENA, 6, 1) 59 FIELD(GSBUSCFG0, INCR64BRSTENA, 5, 1) 60 FIELD(GSBUSCFG0, INCR32BRSTENA, 4, 1) 61 FIELD(GSBUSCFG0, INCR16BRSTENA, 3, 1) 62 FIELD(GSBUSCFG0, INCR8BRSTENA, 2, 1) 63 FIELD(GSBUSCFG0, INCR4BRSTENA, 1, 1) 64 FIELD(GSBUSCFG0, INCRBRSTENA, 0, 1) 65 REG32(GSBUSCFG1, 0x04) 66 FIELD(GSBUSCFG1, RESERVED_31_13, 13, 19) 67 FIELD(GSBUSCFG1, EN1KPAGE, 12, 1) 68 FIELD(GSBUSCFG1, PIPETRANSLIMIT, 8, 4) 69 FIELD(GSBUSCFG1, RESERVED_7_0, 0, 8) 70 REG32(GTXTHRCFG, 0x08) 71 FIELD(GTXTHRCFG, RESERVED_31, 31, 1) 72 FIELD(GTXTHRCFG, RESERVED_30, 30, 1) 73 FIELD(GTXTHRCFG, USBTXPKTCNTSEL, 29, 1) 74 FIELD(GTXTHRCFG, RESERVED_28, 28, 1) 75 FIELD(GTXTHRCFG, USBTXPKTCNT, 24, 4) 76 FIELD(GTXTHRCFG, USBMAXTXBURSTSIZE, 16, 8) 77 FIELD(GTXTHRCFG, RESERVED_15, 15, 1) 78 FIELD(GTXTHRCFG, RESERVED_14, 14, 1) 79 FIELD(GTXTHRCFG, RESERVED_13_11, 11, 3) 80 FIELD(GTXTHRCFG, RESERVED_10_0, 0, 11) 81 REG32(GRXTHRCFG, 0x0c) 82 FIELD(GRXTHRCFG, RESERVED_31_30, 30, 2) 83 FIELD(GRXTHRCFG, USBRXPKTCNTSEL, 29, 1) 84 FIELD(GRXTHRCFG, RESERVED_28, 28, 1) 85 FIELD(GRXTHRCFG, USBRXPKTCNT, 24, 4) 86 FIELD(GRXTHRCFG, USBMAXRXBURSTSIZE, 19, 5) 87 FIELD(GRXTHRCFG, RESERVED_18_16, 16, 3) 88 FIELD(GRXTHRCFG, RESERVED_15, 15, 1) 89 FIELD(GRXTHRCFG, RESERVED_14_13, 13, 2) 90 FIELD(GRXTHRCFG, RESVISOCOUTSPC, 0, 13) 91 REG32(GCTL, 0x10) 92 FIELD(GCTL, PWRDNSCALE, 19, 13) 93 FIELD(GCTL, MASTERFILTBYPASS, 18, 1) 94 FIELD(GCTL, BYPSSETADDR, 17, 1) 95 FIELD(GCTL, U2RSTECN, 16, 1) 96 FIELD(GCTL, FRMSCLDWN, 14, 2) 97 FIELD(GCTL, PRTCAPDIR, 12, 2) 98 FIELD(GCTL, CORESOFTRESET, 11, 1) 99 FIELD(GCTL, U1U2TIMERSCALE, 9, 1) 100 FIELD(GCTL, DEBUGATTACH, 8, 1) 101 FIELD(GCTL, RAMCLKSEL, 6, 2) 102 FIELD(GCTL, SCALEDOWN, 4, 2) 103 FIELD(GCTL, DISSCRAMBLE, 3, 1) 104 FIELD(GCTL, U2EXIT_LFPS, 2, 1) 105 FIELD(GCTL, GBLHIBERNATIONEN, 1, 1) 106 FIELD(GCTL, DSBLCLKGTNG, 0, 1) 107 REG32(GPMSTS, 0x14) 108 REG32(GSTS, 0x18) 109 FIELD(GSTS, CBELT, 20, 12) 110 FIELD(GSTS, RESERVED_19_12, 12, 8) 111 FIELD(GSTS, SSIC_IP, 11, 1) 112 FIELD(GSTS, OTG_IP, 10, 1) 113 FIELD(GSTS, BC_IP, 9, 1) 114 FIELD(GSTS, ADP_IP, 8, 1) 115 FIELD(GSTS, HOST_IP, 7, 1) 116 FIELD(GSTS, DEVICE_IP, 6, 1) 117 FIELD(GSTS, CSRTIMEOUT, 5, 1) 118 FIELD(GSTS, BUSERRADDRVLD, 4, 1) 119 FIELD(GSTS, RESERVED_3_2, 2, 2) 120 FIELD(GSTS, CURMOD, 0, 2) 121 REG32(GUCTL1, 0x1c) 122 FIELD(GUCTL1, RESUME_OPMODE_HS_HOST, 10, 1) 123 REG32(GSNPSID, 0x20) 124 REG32(GGPIO, 0x24) 125 FIELD(GGPIO, GPO, 16, 16) 126 FIELD(GGPIO, GPI, 0, 16) 127 REG32(GUID, 0x28) 128 REG32(GUCTL, 0x2c) 129 FIELD(GUCTL, REFCLKPER, 22, 10) 130 FIELD(GUCTL, NOEXTRDL, 21, 1) 131 FIELD(GUCTL, RESERVED_20_18, 18, 3) 132 FIELD(GUCTL, SPRSCTRLTRANSEN, 17, 1) 133 FIELD(GUCTL, RESBWHSEPS, 16, 1) 134 FIELD(GUCTL, RESERVED_15, 15, 1) 135 FIELD(GUCTL, USBHSTINAUTORETRYEN, 14, 1) 136 FIELD(GUCTL, ENOVERLAPCHK, 13, 1) 137 FIELD(GUCTL, EXTCAPSUPPTEN, 12, 1) 138 FIELD(GUCTL, INSRTEXTRFSBODI, 11, 1) 139 FIELD(GUCTL, DTCT, 9, 2) 140 FIELD(GUCTL, DTFT, 0, 9) 141 REG32(GBUSERRADDRLO, 0x30) 142 REG32(GBUSERRADDRHI, 0x34) 143 REG32(GHWPARAMS0, 0x40) 144 FIELD(GHWPARAMS0, GHWPARAMS0_31_24, 24, 8) 145 FIELD(GHWPARAMS0, GHWPARAMS0_23_16, 16, 8) 146 FIELD(GHWPARAMS0, GHWPARAMS0_15_8, 8, 8) 147 FIELD(GHWPARAMS0, GHWPARAMS0_7_6, 6, 2) 148 FIELD(GHWPARAMS0, GHWPARAMS0_5_3, 3, 3) 149 FIELD(GHWPARAMS0, GHWPARAMS0_2_0, 0, 3) 150 REG32(GHWPARAMS1, 0x44) 151 FIELD(GHWPARAMS1, GHWPARAMS1_31, 31, 1) 152 FIELD(GHWPARAMS1, GHWPARAMS1_30, 30, 1) 153 FIELD(GHWPARAMS1, GHWPARAMS1_29, 29, 1) 154 FIELD(GHWPARAMS1, GHWPARAMS1_28, 28, 1) 155 FIELD(GHWPARAMS1, GHWPARAMS1_27, 27, 1) 156 FIELD(GHWPARAMS1, GHWPARAMS1_26, 26, 1) 157 FIELD(GHWPARAMS1, GHWPARAMS1_25_24, 24, 2) 158 FIELD(GHWPARAMS1, GHWPARAMS1_23, 23, 1) 159 FIELD(GHWPARAMS1, GHWPARAMS1_22_21, 21, 2) 160 FIELD(GHWPARAMS1, GHWPARAMS1_20_15, 15, 6) 161 FIELD(GHWPARAMS1, GHWPARAMS1_14_12, 12, 3) 162 FIELD(GHWPARAMS1, GHWPARAMS1_11_9, 9, 3) 163 FIELD(GHWPARAMS1, GHWPARAMS1_8_6, 6, 3) 164 FIELD(GHWPARAMS1, GHWPARAMS1_5_3, 3, 3) 165 FIELD(GHWPARAMS1, GHWPARAMS1_2_0, 0, 3) 166 REG32(GHWPARAMS2, 0x48) 167 REG32(GHWPARAMS3, 0x4c) 168 FIELD(GHWPARAMS3, GHWPARAMS3_31, 31, 1) 169 FIELD(GHWPARAMS3, GHWPARAMS3_30_23, 23, 8) 170 FIELD(GHWPARAMS3, GHWPARAMS3_22_18, 18, 5) 171 FIELD(GHWPARAMS3, GHWPARAMS3_17_12, 12, 6) 172 FIELD(GHWPARAMS3, GHWPARAMS3_11, 11, 1) 173 FIELD(GHWPARAMS3, GHWPARAMS3_10, 10, 1) 174 FIELD(GHWPARAMS3, GHWPARAMS3_9_8, 8, 2) 175 FIELD(GHWPARAMS3, GHWPARAMS3_7_6, 6, 2) 176 FIELD(GHWPARAMS3, GHWPARAMS3_5_4, 4, 2) 177 FIELD(GHWPARAMS3, GHWPARAMS3_3_2, 2, 2) 178 FIELD(GHWPARAMS3, GHWPARAMS3_1_0, 0, 2) 179 REG32(GHWPARAMS4, 0x50) 180 FIELD(GHWPARAMS4, GHWPARAMS4_31_28, 28, 4) 181 FIELD(GHWPARAMS4, GHWPARAMS4_27_24, 24, 4) 182 FIELD(GHWPARAMS4, GHWPARAMS4_23, 23, 1) 183 FIELD(GHWPARAMS4, GHWPARAMS4_22, 22, 1) 184 FIELD(GHWPARAMS4, GHWPARAMS4_21, 21, 1) 185 FIELD(GHWPARAMS4, GHWPARAMS4_20_17, 17, 4) 186 FIELD(GHWPARAMS4, GHWPARAMS4_16_13, 13, 4) 187 FIELD(GHWPARAMS4, GHWPARAMS4_12, 12, 1) 188 FIELD(GHWPARAMS4, GHWPARAMS4_11, 11, 1) 189 FIELD(GHWPARAMS4, GHWPARAMS4_10_9, 9, 2) 190 FIELD(GHWPARAMS4, GHWPARAMS4_8_7, 7, 2) 191 FIELD(GHWPARAMS4, GHWPARAMS4_6, 6, 1) 192 FIELD(GHWPARAMS4, GHWPARAMS4_5_0, 0, 6) 193 REG32(GHWPARAMS5, 0x54) 194 FIELD(GHWPARAMS5, GHWPARAMS5_31_28, 28, 4) 195 FIELD(GHWPARAMS5, GHWPARAMS5_27_22, 22, 6) 196 FIELD(GHWPARAMS5, GHWPARAMS5_21_16, 16, 6) 197 FIELD(GHWPARAMS5, GHWPARAMS5_15_10, 10, 6) 198 FIELD(GHWPARAMS5, GHWPARAMS5_9_4, 4, 6) 199 FIELD(GHWPARAMS5, GHWPARAMS5_3_0, 0, 4) 200 REG32(GHWPARAMS6, 0x58) 201 FIELD(GHWPARAMS6, GHWPARAMS6_31_16, 16, 16) 202 FIELD(GHWPARAMS6, BUSFLTRSSUPPORT, 15, 1) 203 FIELD(GHWPARAMS6, BCSUPPORT, 14, 1) 204 FIELD(GHWPARAMS6, OTG_SS_SUPPORT, 13, 1) 205 FIELD(GHWPARAMS6, ADPSUPPORT, 12, 1) 206 FIELD(GHWPARAMS6, HNPSUPPORT, 11, 1) 207 FIELD(GHWPARAMS6, SRPSUPPORT, 10, 1) 208 FIELD(GHWPARAMS6, GHWPARAMS6_9_8, 8, 2) 209 FIELD(GHWPARAMS6, GHWPARAMS6_7, 7, 1) 210 FIELD(GHWPARAMS6, GHWPARAMS6_6, 6, 1) 211 FIELD(GHWPARAMS6, GHWPARAMS6_5_0, 0, 6) 212 REG32(GHWPARAMS7, 0x5c) 213 FIELD(GHWPARAMS7, GHWPARAMS7_31_16, 16, 16) 214 FIELD(GHWPARAMS7, GHWPARAMS7_15_0, 0, 16) 215 REG32(GDBGFIFOSPACE, 0x60) 216 FIELD(GDBGFIFOSPACE, SPACE_AVAILABLE, 16, 16) 217 FIELD(GDBGFIFOSPACE, RESERVED_15_9, 9, 7) 218 FIELD(GDBGFIFOSPACE, FIFO_QUEUE_SELECT, 0, 9) 219 REG32(GUCTL2, 0x9c) 220 FIELD(GUCTL2, RESERVED_31_26, 26, 6) 221 FIELD(GUCTL2, EN_HP_PM_TIMER, 19, 7) 222 FIELD(GUCTL2, NOLOWPWRDUR, 15, 4) 223 FIELD(GUCTL2, RST_ACTBITLATER, 14, 1) 224 FIELD(GUCTL2, RESERVED_13, 13, 1) 225 FIELD(GUCTL2, DISABLECFC, 11, 1) 226 REG32(GUSB2PHYCFG, 0x100) 227 FIELD(GUSB2PHYCFG, U2_FREECLK_EXISTS, 30, 1) 228 FIELD(GUSB2PHYCFG, ULPI_LPM_WITH_OPMODE_CHK, 29, 1) 229 FIELD(GUSB2PHYCFG, RESERVED_25, 25, 1) 230 FIELD(GUSB2PHYCFG, LSTRD, 22, 3) 231 FIELD(GUSB2PHYCFG, LSIPD, 19, 3) 232 FIELD(GUSB2PHYCFG, ULPIEXTVBUSINDIACTOR, 18, 1) 233 FIELD(GUSB2PHYCFG, ULPIEXTVBUSDRV, 17, 1) 234 FIELD(GUSB2PHYCFG, RESERVED_16, 16, 1) 235 FIELD(GUSB2PHYCFG, ULPIAUTORES, 15, 1) 236 FIELD(GUSB2PHYCFG, RESERVED_14, 14, 1) 237 FIELD(GUSB2PHYCFG, USBTRDTIM, 10, 4) 238 FIELD(GUSB2PHYCFG, XCVRDLY, 9, 1) 239 FIELD(GUSB2PHYCFG, ENBLSLPM, 8, 1) 240 FIELD(GUSB2PHYCFG, PHYSEL, 7, 1) 241 FIELD(GUSB2PHYCFG, SUSPENDUSB20, 6, 1) 242 FIELD(GUSB2PHYCFG, FSINTF, 5, 1) 243 FIELD(GUSB2PHYCFG, ULPI_UTMI_SEL, 4, 1) 244 FIELD(GUSB2PHYCFG, PHYIF, 3, 1) 245 FIELD(GUSB2PHYCFG, TOUTCAL, 0, 3) 246 REG32(GUSB2I2CCTL, 0x140) 247 REG32(GUSB2PHYACC_ULPI, 0x180) 248 FIELD(GUSB2PHYACC_ULPI, RESERVED_31_27, 27, 5) 249 FIELD(GUSB2PHYACC_ULPI, DISUIPIDRVR, 26, 1) 250 FIELD(GUSB2PHYACC_ULPI, NEWREGREQ, 25, 1) 251 FIELD(GUSB2PHYACC_ULPI, VSTSDONE, 24, 1) 252 FIELD(GUSB2PHYACC_ULPI, VSTSBSY, 23, 1) 253 FIELD(GUSB2PHYACC_ULPI, REGWR, 22, 1) 254 FIELD(GUSB2PHYACC_ULPI, REGADDR, 16, 6) 255 FIELD(GUSB2PHYACC_ULPI, EXTREGADDR, 8, 8) 256 FIELD(GUSB2PHYACC_ULPI, REGDATA, 0, 8) 257 REG32(GTXFIFOSIZ0, 0x200) 258 FIELD(GTXFIFOSIZ0, TXFSTADDR_N, 16, 16) 259 FIELD(GTXFIFOSIZ0, TXFDEP_N, 0, 16) 260 REG32(GTXFIFOSIZ1, 0x204) 261 FIELD(GTXFIFOSIZ1, TXFSTADDR_N, 16, 16) 262 FIELD(GTXFIFOSIZ1, TXFDEP_N, 0, 16) 263 REG32(GTXFIFOSIZ2, 0x208) 264 FIELD(GTXFIFOSIZ2, TXFSTADDR_N, 16, 16) 265 FIELD(GTXFIFOSIZ2, TXFDEP_N, 0, 16) 266 REG32(GTXFIFOSIZ3, 0x20c) 267 FIELD(GTXFIFOSIZ3, TXFSTADDR_N, 16, 16) 268 FIELD(GTXFIFOSIZ3, TXFDEP_N, 0, 16) 269 REG32(GTXFIFOSIZ4, 0x210) 270 FIELD(GTXFIFOSIZ4, TXFSTADDR_N, 16, 16) 271 FIELD(GTXFIFOSIZ4, TXFDEP_N, 0, 16) 272 REG32(GTXFIFOSIZ5, 0x214) 273 FIELD(GTXFIFOSIZ5, TXFSTADDR_N, 16, 16) 274 FIELD(GTXFIFOSIZ5, TXFDEP_N, 0, 16) 275 REG32(GRXFIFOSIZ0, 0x280) 276 FIELD(GRXFIFOSIZ0, RXFSTADDR_N, 16, 16) 277 FIELD(GRXFIFOSIZ0, RXFDEP_N, 0, 16) 278 REG32(GRXFIFOSIZ1, 0x284) 279 FIELD(GRXFIFOSIZ1, RXFSTADDR_N, 16, 16) 280 FIELD(GRXFIFOSIZ1, RXFDEP_N, 0, 16) 281 REG32(GRXFIFOSIZ2, 0x288) 282 FIELD(GRXFIFOSIZ2, RXFSTADDR_N, 16, 16) 283 FIELD(GRXFIFOSIZ2, RXFDEP_N, 0, 16) 284 REG32(GEVNTADRLO_0, 0x300) 285 REG32(GEVNTADRHI_0, 0x304) 286 REG32(GEVNTSIZ_0, 0x308) 287 FIELD(GEVNTSIZ_0, EVNTINTRPTMASK, 31, 1) 288 FIELD(GEVNTSIZ_0, RESERVED_30_16, 16, 15) 289 FIELD(GEVNTSIZ_0, EVENTSIZ, 0, 16) 290 REG32(GEVNTCOUNT_0, 0x30c) 291 FIELD(GEVNTCOUNT_0, EVNT_HANDLER_BUSY, 31, 1) 292 FIELD(GEVNTCOUNT_0, RESERVED_30_16, 16, 15) 293 FIELD(GEVNTCOUNT_0, EVNTCOUNT, 0, 16) 294 REG32(GEVNTADRLO_1, 0x310) 295 REG32(GEVNTADRHI_1, 0x314) 296 REG32(GEVNTSIZ_1, 0x318) 297 FIELD(GEVNTSIZ_1, EVNTINTRPTMASK, 31, 1) 298 FIELD(GEVNTSIZ_1, RESERVED_30_16, 16, 15) 299 FIELD(GEVNTSIZ_1, EVENTSIZ, 0, 16) 300 REG32(GEVNTCOUNT_1, 0x31c) 301 FIELD(GEVNTCOUNT_1, EVNT_HANDLER_BUSY, 31, 1) 302 FIELD(GEVNTCOUNT_1, RESERVED_30_16, 16, 15) 303 FIELD(GEVNTCOUNT_1, EVNTCOUNT, 0, 16) 304 REG32(GEVNTADRLO_2, 0x320) 305 REG32(GEVNTADRHI_2, 0x324) 306 REG32(GEVNTSIZ_2, 0x328) 307 FIELD(GEVNTSIZ_2, EVNTINTRPTMASK, 31, 1) 308 FIELD(GEVNTSIZ_2, RESERVED_30_16, 16, 15) 309 FIELD(GEVNTSIZ_2, EVENTSIZ, 0, 16) 310 REG32(GEVNTCOUNT_2, 0x32c) 311 FIELD(GEVNTCOUNT_2, EVNT_HANDLER_BUSY, 31, 1) 312 FIELD(GEVNTCOUNT_2, RESERVED_30_16, 16, 15) 313 FIELD(GEVNTCOUNT_2, EVNTCOUNT, 0, 16) 314 REG32(GEVNTADRLO_3, 0x330) 315 REG32(GEVNTADRHI_3, 0x334) 316 REG32(GEVNTSIZ_3, 0x338) 317 FIELD(GEVNTSIZ_3, EVNTINTRPTMASK, 31, 1) 318 FIELD(GEVNTSIZ_3, RESERVED_30_16, 16, 15) 319 FIELD(GEVNTSIZ_3, EVENTSIZ, 0, 16) 320 REG32(GEVNTCOUNT_3, 0x33c) 321 FIELD(GEVNTCOUNT_3, EVNT_HANDLER_BUSY, 31, 1) 322 FIELD(GEVNTCOUNT_3, RESERVED_30_16, 16, 15) 323 FIELD(GEVNTCOUNT_3, EVNTCOUNT, 0, 16) 324 REG32(GHWPARAMS8, 0x500) 325 REG32(GTXFIFOPRIDEV, 0x510) 326 FIELD(GTXFIFOPRIDEV, RESERVED_31_N, 6, 26) 327 FIELD(GTXFIFOPRIDEV, GTXFIFOPRIDEV, 0, 6) 328 REG32(GTXFIFOPRIHST, 0x518) 329 FIELD(GTXFIFOPRIHST, RESERVED_31_16, 3, 29) 330 FIELD(GTXFIFOPRIHST, GTXFIFOPRIHST, 0, 3) 331 REG32(GRXFIFOPRIHST, 0x51c) 332 FIELD(GRXFIFOPRIHST, RESERVED_31_16, 3, 29) 333 FIELD(GRXFIFOPRIHST, GRXFIFOPRIHST, 0, 3) 334 REG32(GDMAHLRATIO, 0x524) 335 FIELD(GDMAHLRATIO, RESERVED_31_13, 13, 19) 336 FIELD(GDMAHLRATIO, HSTRXFIFO, 8, 5) 337 FIELD(GDMAHLRATIO, RESERVED_7_5, 5, 3) 338 FIELD(GDMAHLRATIO, HSTTXFIFO, 0, 5) 339 REG32(GFLADJ, 0x530) 340 FIELD(GFLADJ, GFLADJ_REFCLK_240MHZDECR_PLS1, 31, 1) 341 FIELD(GFLADJ, GFLADJ_REFCLK_240MHZ_DECR, 24, 7) 342 FIELD(GFLADJ, GFLADJ_REFCLK_LPM_SEL, 23, 1) 343 FIELD(GFLADJ, RESERVED_22, 22, 1) 344 FIELD(GFLADJ, GFLADJ_REFCLK_FLADJ, 8, 14) 345 FIELD(GFLADJ, GFLADJ_30MHZ_SDBND_SEL, 7, 1) 346 FIELD(GFLADJ, GFLADJ_30MHZ, 0, 6) 347 348 #define DWC3_GLOBAL_OFFSET 0xC100 349 static void reset_csr(USBDWC3 * s) 350 { 351 int i = 0; 352 /* 353 * We reset all CSR regs except GCTL, GUCTL, GSTS, GSNPSID, GGPIO, GUID, 354 * GUSB2PHYCFGn registers and GUSB3PIPECTLn registers. We will skip PHY 355 * register as we don't implement them. 356 */ 357 for (i = 0; i < USB_DWC3_R_MAX; i++) { 358 switch (i) { 359 case R_GCTL: 360 break; 361 case R_GSTS: 362 break; 363 case R_GSNPSID: 364 break; 365 case R_GGPIO: 366 break; 367 case R_GUID: 368 break; 369 case R_GUCTL: 370 break; 371 case R_GHWPARAMS0...R_GHWPARAMS7: 372 break; 373 case R_GHWPARAMS8: 374 break; 375 default: 376 register_reset(&s->regs_info[i]); 377 break; 378 } 379 } 380 381 xhci_sysbus_reset(DEVICE(&s->sysbus_xhci)); 382 } 383 384 static void usb_dwc3_gctl_postw(RegisterInfo *reg, uint64_t val64) 385 { 386 USBDWC3 *s = USB_DWC3(reg->opaque); 387 388 if (ARRAY_FIELD_EX32(s->regs, GCTL, CORESOFTRESET)) { 389 reset_csr(s); 390 } 391 } 392 393 static void usb_dwc3_guid_postw(RegisterInfo *reg, uint64_t val64) 394 { 395 USBDWC3 *s = USB_DWC3(reg->opaque); 396 397 s->regs[R_GUID] = s->cfg.dwc_usb3_user; 398 } 399 400 static const RegisterAccessInfo usb_dwc3_regs_info[] = { 401 { .name = "GSBUSCFG0", .addr = A_GSBUSCFG0, 402 .ro = 0xf300, 403 .unimp = 0xffffffff, 404 },{ .name = "GSBUSCFG1", .addr = A_GSBUSCFG1, 405 .reset = 0x300, 406 .ro = 0xffffe0ff, 407 .unimp = 0xffffffff, 408 },{ .name = "GTXTHRCFG", .addr = A_GTXTHRCFG, 409 .ro = 0xd000ffff, 410 .unimp = 0xffffffff, 411 },{ .name = "GRXTHRCFG", .addr = A_GRXTHRCFG, 412 .ro = 0xd007e000, 413 .unimp = 0xffffffff, 414 },{ .name = "GCTL", .addr = A_GCTL, 415 .reset = 0x30c13004, .post_write = usb_dwc3_gctl_postw, 416 },{ .name = "GPMSTS", .addr = A_GPMSTS, 417 .ro = 0xfffffff, 418 .unimp = 0xffffffff, 419 },{ .name = "GSTS", .addr = A_GSTS, 420 .reset = 0x7e800000, 421 .ro = 0xffffffcf, 422 .w1c = 0x30, 423 .unimp = 0xffffffff, 424 },{ .name = "GUCTL1", .addr = A_GUCTL1, 425 .reset = 0x198a, 426 .ro = 0x7800, 427 .unimp = 0xffffffff, 428 },{ .name = "GSNPSID", .addr = A_GSNPSID, 429 .reset = 0x5533330a, 430 .ro = 0xffffffff, 431 },{ .name = "GGPIO", .addr = A_GGPIO, 432 .ro = 0xffff, 433 .unimp = 0xffffffff, 434 },{ .name = "GUID", .addr = A_GUID, 435 .reset = 0x12345678, .post_write = usb_dwc3_guid_postw, 436 },{ .name = "GUCTL", .addr = A_GUCTL, 437 .reset = 0x0c808010, 438 .ro = 0x1c8000, 439 .unimp = 0xffffffff, 440 },{ .name = "GBUSERRADDRLO", .addr = A_GBUSERRADDRLO, 441 .ro = 0xffffffff, 442 },{ .name = "GBUSERRADDRHI", .addr = A_GBUSERRADDRHI, 443 .ro = 0xffffffff, 444 },{ .name = "GHWPARAMS0", .addr = A_GHWPARAMS0, 445 .ro = 0xffffffff, 446 },{ .name = "GHWPARAMS1", .addr = A_GHWPARAMS1, 447 .ro = 0xffffffff, 448 },{ .name = "GHWPARAMS2", .addr = A_GHWPARAMS2, 449 .ro = 0xffffffff, 450 },{ .name = "GHWPARAMS3", .addr = A_GHWPARAMS3, 451 .ro = 0xffffffff, 452 },{ .name = "GHWPARAMS4", .addr = A_GHWPARAMS4, 453 .ro = 0xffffffff, 454 },{ .name = "GHWPARAMS5", .addr = A_GHWPARAMS5, 455 .ro = 0xffffffff, 456 },{ .name = "GHWPARAMS6", .addr = A_GHWPARAMS6, 457 .ro = 0xffffffff, 458 },{ .name = "GHWPARAMS7", .addr = A_GHWPARAMS7, 459 .ro = 0xffffffff, 460 },{ .name = "GDBGFIFOSPACE", .addr = A_GDBGFIFOSPACE, 461 .reset = 0xa0000, 462 .ro = 0xfffffe00, 463 .unimp = 0xffffffff, 464 },{ .name = "GUCTL2", .addr = A_GUCTL2, 465 .reset = 0x40d, 466 .ro = 0x2000, 467 .unimp = 0xffffffff, 468 },{ .name = "GUSB2PHYCFG", .addr = A_GUSB2PHYCFG, 469 .reset = 0x40102410, 470 .ro = 0x1e014030, 471 .unimp = 0xffffffff, 472 },{ .name = "GUSB2I2CCTL", .addr = A_GUSB2I2CCTL, 473 .ro = 0xffffffff, 474 .unimp = 0xffffffff, 475 },{ .name = "GUSB2PHYACC_ULPI", .addr = A_GUSB2PHYACC_ULPI, 476 .ro = 0xfd000000, 477 .unimp = 0xffffffff, 478 },{ .name = "GTXFIFOSIZ0", .addr = A_GTXFIFOSIZ0, 479 .reset = 0x2c7000a, 480 .unimp = 0xffffffff, 481 },{ .name = "GTXFIFOSIZ1", .addr = A_GTXFIFOSIZ1, 482 .reset = 0x2d10103, 483 .unimp = 0xffffffff, 484 },{ .name = "GTXFIFOSIZ2", .addr = A_GTXFIFOSIZ2, 485 .reset = 0x3d40103, 486 .unimp = 0xffffffff, 487 },{ .name = "GTXFIFOSIZ3", .addr = A_GTXFIFOSIZ3, 488 .reset = 0x4d70083, 489 .unimp = 0xffffffff, 490 },{ .name = "GTXFIFOSIZ4", .addr = A_GTXFIFOSIZ4, 491 .reset = 0x55a0083, 492 .unimp = 0xffffffff, 493 },{ .name = "GTXFIFOSIZ5", .addr = A_GTXFIFOSIZ5, 494 .reset = 0x5dd0083, 495 .unimp = 0xffffffff, 496 },{ .name = "GRXFIFOSIZ0", .addr = A_GRXFIFOSIZ0, 497 .reset = 0x1c20105, 498 .unimp = 0xffffffff, 499 },{ .name = "GRXFIFOSIZ1", .addr = A_GRXFIFOSIZ1, 500 .reset = 0x2c70000, 501 .unimp = 0xffffffff, 502 },{ .name = "GRXFIFOSIZ2", .addr = A_GRXFIFOSIZ2, 503 .reset = 0x2c70000, 504 .unimp = 0xffffffff, 505 },{ .name = "GEVNTADRLO_0", .addr = A_GEVNTADRLO_0, 506 .unimp = 0xffffffff, 507 },{ .name = "GEVNTADRHI_0", .addr = A_GEVNTADRHI_0, 508 .unimp = 0xffffffff, 509 },{ .name = "GEVNTSIZ_0", .addr = A_GEVNTSIZ_0, 510 .ro = 0x7fff0000, 511 .unimp = 0xffffffff, 512 },{ .name = "GEVNTCOUNT_0", .addr = A_GEVNTCOUNT_0, 513 .ro = 0x7fff0000, 514 .unimp = 0xffffffff, 515 },{ .name = "GEVNTADRLO_1", .addr = A_GEVNTADRLO_1, 516 .unimp = 0xffffffff, 517 },{ .name = "GEVNTADRHI_1", .addr = A_GEVNTADRHI_1, 518 .unimp = 0xffffffff, 519 },{ .name = "GEVNTSIZ_1", .addr = A_GEVNTSIZ_1, 520 .ro = 0x7fff0000, 521 .unimp = 0xffffffff, 522 },{ .name = "GEVNTCOUNT_1", .addr = A_GEVNTCOUNT_1, 523 .ro = 0x7fff0000, 524 .unimp = 0xffffffff, 525 },{ .name = "GEVNTADRLO_2", .addr = A_GEVNTADRLO_2, 526 .unimp = 0xffffffff, 527 },{ .name = "GEVNTADRHI_2", .addr = A_GEVNTADRHI_2, 528 .unimp = 0xffffffff, 529 },{ .name = "GEVNTSIZ_2", .addr = A_GEVNTSIZ_2, 530 .ro = 0x7fff0000, 531 .unimp = 0xffffffff, 532 },{ .name = "GEVNTCOUNT_2", .addr = A_GEVNTCOUNT_2, 533 .ro = 0x7fff0000, 534 .unimp = 0xffffffff, 535 },{ .name = "GEVNTADRLO_3", .addr = A_GEVNTADRLO_3, 536 .unimp = 0xffffffff, 537 },{ .name = "GEVNTADRHI_3", .addr = A_GEVNTADRHI_3, 538 .unimp = 0xffffffff, 539 },{ .name = "GEVNTSIZ_3", .addr = A_GEVNTSIZ_3, 540 .ro = 0x7fff0000, 541 .unimp = 0xffffffff, 542 },{ .name = "GEVNTCOUNT_3", .addr = A_GEVNTCOUNT_3, 543 .ro = 0x7fff0000, 544 .unimp = 0xffffffff, 545 },{ .name = "GHWPARAMS8", .addr = A_GHWPARAMS8, 546 .ro = 0xffffffff, 547 },{ .name = "GTXFIFOPRIDEV", .addr = A_GTXFIFOPRIDEV, 548 .ro = 0xffffffc0, 549 .unimp = 0xffffffff, 550 },{ .name = "GTXFIFOPRIHST", .addr = A_GTXFIFOPRIHST, 551 .ro = 0xfffffff8, 552 .unimp = 0xffffffff, 553 },{ .name = "GRXFIFOPRIHST", .addr = A_GRXFIFOPRIHST, 554 .ro = 0xfffffff8, 555 .unimp = 0xffffffff, 556 },{ .name = "GDMAHLRATIO", .addr = A_GDMAHLRATIO, 557 .ro = 0xffffe0e0, 558 .unimp = 0xffffffff, 559 },{ .name = "GFLADJ", .addr = A_GFLADJ, 560 .reset = 0xc83f020, 561 .rsvd = 0x40, 562 .ro = 0x400040, 563 .unimp = 0xffffffff, 564 } 565 }; 566 567 static void usb_dwc3_reset(DeviceState *dev) 568 { 569 USBDWC3 *s = USB_DWC3(dev); 570 unsigned int i; 571 572 for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { 573 switch (i) { 574 case R_GHWPARAMS0...R_GHWPARAMS7: 575 break; 576 case R_GHWPARAMS8: 577 break; 578 default: 579 register_reset(&s->regs_info[i]); 580 }; 581 } 582 583 xhci_sysbus_reset(DEVICE(&s->sysbus_xhci)); 584 } 585 586 static const MemoryRegionOps usb_dwc3_ops = { 587 .read = register_read_memory, 588 .write = register_write_memory, 589 .endianness = DEVICE_LITTLE_ENDIAN, 590 .valid = { 591 .min_access_size = 4, 592 .max_access_size = 4, 593 }, 594 }; 595 596 static void usb_dwc3_realize(DeviceState *dev, Error **errp) 597 { 598 USBDWC3 *s = USB_DWC3(dev); 599 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 600 Error *err = NULL; 601 602 sysbus_realize(SYS_BUS_DEVICE(&s->sysbus_xhci), &err); 603 if (err) { 604 error_propagate(errp, err); 605 return; 606 } 607 608 memory_region_add_subregion(&s->iomem, 0, 609 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sysbus_xhci), 0)); 610 sysbus_init_mmio(sbd, &s->iomem); 611 612 /* 613 * Device Configuration 614 */ 615 s->regs[R_GHWPARAMS0] = 0x40204048 | s->cfg.mode; 616 s->regs[R_GHWPARAMS1] = 0x222493b; 617 s->regs[R_GHWPARAMS2] = 0x12345678; 618 s->regs[R_GHWPARAMS3] = 0x618c088; 619 s->regs[R_GHWPARAMS4] = 0x47822004; 620 s->regs[R_GHWPARAMS5] = 0x4202088; 621 s->regs[R_GHWPARAMS6] = 0x7850c20; 622 s->regs[R_GHWPARAMS7] = 0x0; 623 s->regs[R_GHWPARAMS8] = 0x478; 624 } 625 626 static void usb_dwc3_init(Object *obj) 627 { 628 USBDWC3 *s = USB_DWC3(obj); 629 RegisterInfoArray *reg_array; 630 631 memory_region_init(&s->iomem, obj, TYPE_USB_DWC3, DWC3_SIZE); 632 reg_array = 633 register_init_block32(DEVICE(obj), usb_dwc3_regs_info, 634 ARRAY_SIZE(usb_dwc3_regs_info), 635 s->regs_info, s->regs, 636 &usb_dwc3_ops, 637 USB_DWC3_ERR_DEBUG, 638 USB_DWC3_R_MAX * 4); 639 memory_region_add_subregion(&s->iomem, 640 DWC3_GLOBAL_OFFSET, 641 ®_array->mem); 642 object_initialize_child(obj, "dwc3-xhci", &s->sysbus_xhci, 643 TYPE_XHCI_SYSBUS); 644 qdev_alias_all_properties(DEVICE(&s->sysbus_xhci), obj); 645 646 s->cfg.mode = HOST_MODE; 647 } 648 649 static const VMStateDescription vmstate_usb_dwc3 = { 650 .name = "usb-dwc3", 651 .version_id = 1, 652 .fields = (VMStateField[]) { 653 VMSTATE_UINT32_ARRAY(regs, USBDWC3, USB_DWC3_R_MAX), 654 VMSTATE_UINT8(cfg.mode, USBDWC3), 655 VMSTATE_UINT32(cfg.dwc_usb3_user, USBDWC3), 656 VMSTATE_END_OF_LIST() 657 } 658 }; 659 660 static Property usb_dwc3_properties[] = { 661 DEFINE_PROP_UINT32("DWC_USB3_USERID", USBDWC3, cfg.dwc_usb3_user, 662 0x12345678), 663 DEFINE_PROP_END_OF_LIST(), 664 }; 665 666 static void usb_dwc3_class_init(ObjectClass *klass, void *data) 667 { 668 DeviceClass *dc = DEVICE_CLASS(klass); 669 670 dc->reset = usb_dwc3_reset; 671 dc->realize = usb_dwc3_realize; 672 dc->vmsd = &vmstate_usb_dwc3; 673 device_class_set_props(dc, usb_dwc3_properties); 674 } 675 676 static const TypeInfo usb_dwc3_info = { 677 .name = TYPE_USB_DWC3, 678 .parent = TYPE_SYS_BUS_DEVICE, 679 .instance_size = sizeof(USBDWC3), 680 .class_init = usb_dwc3_class_init, 681 .instance_init = usb_dwc3_init, 682 }; 683 684 static void usb_dwc3_register_types(void) 685 { 686 type_register_static(&usb_dwc3_info); 687 } 688 689 type_init(usb_dwc3_register_types) 690