xref: /openbmc/qemu/hw/usb/hcd-dwc3.c (revision 2068cabd)
1  /*
2   * QEMU model of the USB DWC3 host controller emulation.
3   *
4   * This model defines global register space of DWC3 controller. Global
5   * registers control the AXI/AHB interfaces properties, external FIFO support
6   * and event count support. All of which are unimplemented at present. We are
7   * only supporting core reset and read of ID register.
8   *
9   * Copyright (c) 2020 Xilinx Inc. Vikram Garhwal<fnu.vikram@xilinx.com>
10   *
11   * Permission is hereby granted, free of charge, to any person obtaining a copy
12   * of this software and associated documentation files (the "Software"), to deal
13   * in the Software without restriction, including without limitation the rights
14   * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
15   * copies of the Software, and to permit persons to whom the Software is
16   * furnished to do so, subject to the following conditions:
17   *
18   * The above copyright notice and this permission notice shall be included in
19   * all copies or substantial portions of the Software.
20   *
21   * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
22   * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
23   * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
24   * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
25   * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
26   * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27   * THE SOFTWARE.
28   */
29  
30  #include "qemu/osdep.h"
31  #include "hw/sysbus.h"
32  #include "hw/register.h"
33  #include "qemu/bitops.h"
34  #include "qom/object.h"
35  #include "migration/vmstate.h"
36  #include "hw/qdev-properties.h"
37  #include "hw/usb/hcd-dwc3.h"
38  #include "qapi/error.h"
39  
40  #ifndef USB_DWC3_ERR_DEBUG
41  #define USB_DWC3_ERR_DEBUG 0
42  #endif
43  
44  #define HOST_MODE           1
45  #define FIFO_LEN         0x1000
46  
47  REG32(GSBUSCFG0, 0x00)
48      FIELD(GSBUSCFG0, DATRDREQINFO, 28, 4)
49      FIELD(GSBUSCFG0, DESRDREQINFO, 24, 4)
50      FIELD(GSBUSCFG0, DATWRREQINFO, 20, 4)
51      FIELD(GSBUSCFG0, DESWRREQINFO, 16, 4)
52      FIELD(GSBUSCFG0, RESERVED_15_12, 12, 4)
53      FIELD(GSBUSCFG0, DATBIGEND, 11, 1)
54      FIELD(GSBUSCFG0, DESBIGEND, 10, 1)
55      FIELD(GSBUSCFG0, RESERVED_9_8, 8, 2)
56      FIELD(GSBUSCFG0, INCR256BRSTENA, 7, 1)
57      FIELD(GSBUSCFG0, INCR128BRSTENA, 6, 1)
58      FIELD(GSBUSCFG0, INCR64BRSTENA, 5, 1)
59      FIELD(GSBUSCFG0, INCR32BRSTENA, 4, 1)
60      FIELD(GSBUSCFG0, INCR16BRSTENA, 3, 1)
61      FIELD(GSBUSCFG0, INCR8BRSTENA, 2, 1)
62      FIELD(GSBUSCFG0, INCR4BRSTENA, 1, 1)
63      FIELD(GSBUSCFG0, INCRBRSTENA, 0, 1)
64  REG32(GSBUSCFG1, 0x04)
65      FIELD(GSBUSCFG1, RESERVED_31_13, 13, 19)
66      FIELD(GSBUSCFG1, EN1KPAGE, 12, 1)
67      FIELD(GSBUSCFG1, PIPETRANSLIMIT, 8, 4)
68      FIELD(GSBUSCFG1, RESERVED_7_0, 0, 8)
69  REG32(GTXTHRCFG, 0x08)
70      FIELD(GTXTHRCFG, RESERVED_31, 31, 1)
71      FIELD(GTXTHRCFG, RESERVED_30, 30, 1)
72      FIELD(GTXTHRCFG, USBTXPKTCNTSEL, 29, 1)
73      FIELD(GTXTHRCFG, RESERVED_28, 28, 1)
74      FIELD(GTXTHRCFG, USBTXPKTCNT, 24, 4)
75      FIELD(GTXTHRCFG, USBMAXTXBURSTSIZE, 16, 8)
76      FIELD(GTXTHRCFG, RESERVED_15, 15, 1)
77      FIELD(GTXTHRCFG, RESERVED_14, 14, 1)
78      FIELD(GTXTHRCFG, RESERVED_13_11, 11, 3)
79      FIELD(GTXTHRCFG, RESERVED_10_0, 0, 11)
80  REG32(GRXTHRCFG, 0x0c)
81      FIELD(GRXTHRCFG, RESERVED_31_30, 30, 2)
82      FIELD(GRXTHRCFG, USBRXPKTCNTSEL, 29, 1)
83      FIELD(GRXTHRCFG, RESERVED_28, 28, 1)
84      FIELD(GRXTHRCFG, USBRXPKTCNT, 24, 4)
85      FIELD(GRXTHRCFG, USBMAXRXBURSTSIZE, 19, 5)
86      FIELD(GRXTHRCFG, RESERVED_18_16, 16, 3)
87      FIELD(GRXTHRCFG, RESERVED_15, 15, 1)
88      FIELD(GRXTHRCFG, RESERVED_14_13, 13, 2)
89      FIELD(GRXTHRCFG, RESVISOCOUTSPC, 0, 13)
90  REG32(GCTL, 0x10)
91      FIELD(GCTL, PWRDNSCALE, 19, 13)
92      FIELD(GCTL, MASTERFILTBYPASS, 18, 1)
93      FIELD(GCTL, BYPSSETADDR, 17, 1)
94      FIELD(GCTL, U2RSTECN, 16, 1)
95      FIELD(GCTL, FRMSCLDWN, 14, 2)
96      FIELD(GCTL, PRTCAPDIR, 12, 2)
97      FIELD(GCTL, CORESOFTRESET, 11, 1)
98      FIELD(GCTL, U1U2TIMERSCALE, 9, 1)
99      FIELD(GCTL, DEBUGATTACH, 8, 1)
100      FIELD(GCTL, RAMCLKSEL, 6, 2)
101      FIELD(GCTL, SCALEDOWN, 4, 2)
102      FIELD(GCTL, DISSCRAMBLE, 3, 1)
103      FIELD(GCTL, U2EXIT_LFPS, 2, 1)
104      FIELD(GCTL, GBLHIBERNATIONEN, 1, 1)
105      FIELD(GCTL, DSBLCLKGTNG, 0, 1)
106  REG32(GPMSTS, 0x14)
107  REG32(GSTS, 0x18)
108      FIELD(GSTS, CBELT, 20, 12)
109      FIELD(GSTS, RESERVED_19_12, 12, 8)
110      FIELD(GSTS, SSIC_IP, 11, 1)
111      FIELD(GSTS, OTG_IP, 10, 1)
112      FIELD(GSTS, BC_IP, 9, 1)
113      FIELD(GSTS, ADP_IP, 8, 1)
114      FIELD(GSTS, HOST_IP, 7, 1)
115      FIELD(GSTS, DEVICE_IP, 6, 1)
116      FIELD(GSTS, CSRTIMEOUT, 5, 1)
117      FIELD(GSTS, BUSERRADDRVLD, 4, 1)
118      FIELD(GSTS, RESERVED_3_2, 2, 2)
119      FIELD(GSTS, CURMOD, 0, 2)
120  REG32(GUCTL1, 0x1c)
121      FIELD(GUCTL1, RESUME_OPMODE_HS_HOST, 10, 1)
122  REG32(GSNPSID, 0x20)
123  REG32(GGPIO, 0x24)
124      FIELD(GGPIO, GPO, 16, 16)
125      FIELD(GGPIO, GPI, 0, 16)
126  REG32(GUID, 0x28)
127  REG32(GUCTL, 0x2c)
128      FIELD(GUCTL, REFCLKPER, 22, 10)
129      FIELD(GUCTL, NOEXTRDL, 21, 1)
130      FIELD(GUCTL, RESERVED_20_18, 18, 3)
131      FIELD(GUCTL, SPRSCTRLTRANSEN, 17, 1)
132      FIELD(GUCTL, RESBWHSEPS, 16, 1)
133      FIELD(GUCTL, RESERVED_15, 15, 1)
134      FIELD(GUCTL, USBHSTINAUTORETRYEN, 14, 1)
135      FIELD(GUCTL, ENOVERLAPCHK, 13, 1)
136      FIELD(GUCTL, EXTCAPSUPPTEN, 12, 1)
137      FIELD(GUCTL, INSRTEXTRFSBODI, 11, 1)
138      FIELD(GUCTL, DTCT, 9, 2)
139      FIELD(GUCTL, DTFT, 0, 9)
140  REG32(GBUSERRADDRLO, 0x30)
141  REG32(GBUSERRADDRHI, 0x34)
142  REG32(GHWPARAMS0, 0x40)
143      FIELD(GHWPARAMS0, GHWPARAMS0_31_24, 24, 8)
144      FIELD(GHWPARAMS0, GHWPARAMS0_23_16, 16, 8)
145      FIELD(GHWPARAMS0, GHWPARAMS0_15_8, 8, 8)
146      FIELD(GHWPARAMS0, GHWPARAMS0_7_6, 6, 2)
147      FIELD(GHWPARAMS0, GHWPARAMS0_5_3, 3, 3)
148      FIELD(GHWPARAMS0, GHWPARAMS0_2_0, 0, 3)
149  REG32(GHWPARAMS1, 0x44)
150      FIELD(GHWPARAMS1, GHWPARAMS1_31, 31, 1)
151      FIELD(GHWPARAMS1, GHWPARAMS1_30, 30, 1)
152      FIELD(GHWPARAMS1, GHWPARAMS1_29, 29, 1)
153      FIELD(GHWPARAMS1, GHWPARAMS1_28, 28, 1)
154      FIELD(GHWPARAMS1, GHWPARAMS1_27, 27, 1)
155      FIELD(GHWPARAMS1, GHWPARAMS1_26, 26, 1)
156      FIELD(GHWPARAMS1, GHWPARAMS1_25_24, 24, 2)
157      FIELD(GHWPARAMS1, GHWPARAMS1_23, 23, 1)
158      FIELD(GHWPARAMS1, GHWPARAMS1_22_21, 21, 2)
159      FIELD(GHWPARAMS1, GHWPARAMS1_20_15, 15, 6)
160      FIELD(GHWPARAMS1, GHWPARAMS1_14_12, 12, 3)
161      FIELD(GHWPARAMS1, GHWPARAMS1_11_9, 9, 3)
162      FIELD(GHWPARAMS1, GHWPARAMS1_8_6, 6, 3)
163      FIELD(GHWPARAMS1, GHWPARAMS1_5_3, 3, 3)
164      FIELD(GHWPARAMS1, GHWPARAMS1_2_0, 0, 3)
165  REG32(GHWPARAMS2, 0x48)
166  REG32(GHWPARAMS3, 0x4c)
167      FIELD(GHWPARAMS3, GHWPARAMS3_31, 31, 1)
168      FIELD(GHWPARAMS3, GHWPARAMS3_30_23, 23, 8)
169      FIELD(GHWPARAMS3, GHWPARAMS3_22_18, 18, 5)
170      FIELD(GHWPARAMS3, GHWPARAMS3_17_12, 12, 6)
171      FIELD(GHWPARAMS3, GHWPARAMS3_11, 11, 1)
172      FIELD(GHWPARAMS3, GHWPARAMS3_10, 10, 1)
173      FIELD(GHWPARAMS3, GHWPARAMS3_9_8, 8, 2)
174      FIELD(GHWPARAMS3, GHWPARAMS3_7_6, 6, 2)
175      FIELD(GHWPARAMS3, GHWPARAMS3_5_4, 4, 2)
176      FIELD(GHWPARAMS3, GHWPARAMS3_3_2, 2, 2)
177      FIELD(GHWPARAMS3, GHWPARAMS3_1_0, 0, 2)
178  REG32(GHWPARAMS4, 0x50)
179      FIELD(GHWPARAMS4, GHWPARAMS4_31_28, 28, 4)
180      FIELD(GHWPARAMS4, GHWPARAMS4_27_24, 24, 4)
181      FIELD(GHWPARAMS4, GHWPARAMS4_23, 23, 1)
182      FIELD(GHWPARAMS4, GHWPARAMS4_22, 22, 1)
183      FIELD(GHWPARAMS4, GHWPARAMS4_21, 21, 1)
184      FIELD(GHWPARAMS4, GHWPARAMS4_20_17, 17, 4)
185      FIELD(GHWPARAMS4, GHWPARAMS4_16_13, 13, 4)
186      FIELD(GHWPARAMS4, GHWPARAMS4_12, 12, 1)
187      FIELD(GHWPARAMS4, GHWPARAMS4_11, 11, 1)
188      FIELD(GHWPARAMS4, GHWPARAMS4_10_9, 9, 2)
189      FIELD(GHWPARAMS4, GHWPARAMS4_8_7, 7, 2)
190      FIELD(GHWPARAMS4, GHWPARAMS4_6, 6, 1)
191      FIELD(GHWPARAMS4, GHWPARAMS4_5_0, 0, 6)
192  REG32(GHWPARAMS5, 0x54)
193      FIELD(GHWPARAMS5, GHWPARAMS5_31_28, 28, 4)
194      FIELD(GHWPARAMS5, GHWPARAMS5_27_22, 22, 6)
195      FIELD(GHWPARAMS5, GHWPARAMS5_21_16, 16, 6)
196      FIELD(GHWPARAMS5, GHWPARAMS5_15_10, 10, 6)
197      FIELD(GHWPARAMS5, GHWPARAMS5_9_4, 4, 6)
198      FIELD(GHWPARAMS5, GHWPARAMS5_3_0, 0, 4)
199  REG32(GHWPARAMS6, 0x58)
200      FIELD(GHWPARAMS6, GHWPARAMS6_31_16, 16, 16)
201      FIELD(GHWPARAMS6, BUSFLTRSSUPPORT, 15, 1)
202      FIELD(GHWPARAMS6, BCSUPPORT, 14, 1)
203      FIELD(GHWPARAMS6, OTG_SS_SUPPORT, 13, 1)
204      FIELD(GHWPARAMS6, ADPSUPPORT, 12, 1)
205      FIELD(GHWPARAMS6, HNPSUPPORT, 11, 1)
206      FIELD(GHWPARAMS6, SRPSUPPORT, 10, 1)
207      FIELD(GHWPARAMS6, GHWPARAMS6_9_8, 8, 2)
208      FIELD(GHWPARAMS6, GHWPARAMS6_7, 7, 1)
209      FIELD(GHWPARAMS6, GHWPARAMS6_6, 6, 1)
210      FIELD(GHWPARAMS6, GHWPARAMS6_5_0, 0, 6)
211  REG32(GHWPARAMS7, 0x5c)
212      FIELD(GHWPARAMS7, GHWPARAMS7_31_16, 16, 16)
213      FIELD(GHWPARAMS7, GHWPARAMS7_15_0, 0, 16)
214  REG32(GDBGFIFOSPACE, 0x60)
215      FIELD(GDBGFIFOSPACE, SPACE_AVAILABLE, 16, 16)
216      FIELD(GDBGFIFOSPACE, RESERVED_15_9, 9, 7)
217      FIELD(GDBGFIFOSPACE, FIFO_QUEUE_SELECT, 0, 9)
218  REG32(GUCTL2, 0x9c)
219      FIELD(GUCTL2, RESERVED_31_26, 26, 6)
220      FIELD(GUCTL2, EN_HP_PM_TIMER, 19, 7)
221      FIELD(GUCTL2, NOLOWPWRDUR, 15, 4)
222      FIELD(GUCTL2, RST_ACTBITLATER, 14, 1)
223      FIELD(GUCTL2, RESERVED_13, 13, 1)
224      FIELD(GUCTL2, DISABLECFC, 11, 1)
225  REG32(GUSB2PHYCFG, 0x100)
226      FIELD(GUSB2PHYCFG, U2_FREECLK_EXISTS, 30, 1)
227      FIELD(GUSB2PHYCFG, ULPI_LPM_WITH_OPMODE_CHK, 29, 1)
228      FIELD(GUSB2PHYCFG, RESERVED_25, 25, 1)
229      FIELD(GUSB2PHYCFG, LSTRD, 22, 3)
230      FIELD(GUSB2PHYCFG, LSIPD, 19, 3)
231      FIELD(GUSB2PHYCFG, ULPIEXTVBUSINDIACTOR, 18, 1)
232      FIELD(GUSB2PHYCFG, ULPIEXTVBUSDRV, 17, 1)
233      FIELD(GUSB2PHYCFG, RESERVED_16, 16, 1)
234      FIELD(GUSB2PHYCFG, ULPIAUTORES, 15, 1)
235      FIELD(GUSB2PHYCFG, RESERVED_14, 14, 1)
236      FIELD(GUSB2PHYCFG, USBTRDTIM, 10, 4)
237      FIELD(GUSB2PHYCFG, XCVRDLY, 9, 1)
238      FIELD(GUSB2PHYCFG, ENBLSLPM, 8, 1)
239      FIELD(GUSB2PHYCFG, PHYSEL, 7, 1)
240      FIELD(GUSB2PHYCFG, SUSPENDUSB20, 6, 1)
241      FIELD(GUSB2PHYCFG, FSINTF, 5, 1)
242      FIELD(GUSB2PHYCFG, ULPI_UTMI_SEL, 4, 1)
243      FIELD(GUSB2PHYCFG, PHYIF, 3, 1)
244      FIELD(GUSB2PHYCFG, TOUTCAL, 0, 3)
245  REG32(GUSB2I2CCTL, 0x140)
246  REG32(GUSB2PHYACC_ULPI, 0x180)
247      FIELD(GUSB2PHYACC_ULPI, RESERVED_31_27, 27, 5)
248      FIELD(GUSB2PHYACC_ULPI, DISUIPIDRVR, 26, 1)
249      FIELD(GUSB2PHYACC_ULPI, NEWREGREQ, 25, 1)
250      FIELD(GUSB2PHYACC_ULPI, VSTSDONE, 24, 1)
251      FIELD(GUSB2PHYACC_ULPI, VSTSBSY, 23, 1)
252      FIELD(GUSB2PHYACC_ULPI, REGWR, 22, 1)
253      FIELD(GUSB2PHYACC_ULPI, REGADDR, 16, 6)
254      FIELD(GUSB2PHYACC_ULPI, EXTREGADDR, 8, 8)
255      FIELD(GUSB2PHYACC_ULPI, REGDATA, 0, 8)
256  REG32(GTXFIFOSIZ0, 0x200)
257      FIELD(GTXFIFOSIZ0, TXFSTADDR_N, 16, 16)
258      FIELD(GTXFIFOSIZ0, TXFDEP_N, 0, 16)
259  REG32(GTXFIFOSIZ1, 0x204)
260      FIELD(GTXFIFOSIZ1, TXFSTADDR_N, 16, 16)
261      FIELD(GTXFIFOSIZ1, TXFDEP_N, 0, 16)
262  REG32(GTXFIFOSIZ2, 0x208)
263      FIELD(GTXFIFOSIZ2, TXFSTADDR_N, 16, 16)
264      FIELD(GTXFIFOSIZ2, TXFDEP_N, 0, 16)
265  REG32(GTXFIFOSIZ3, 0x20c)
266      FIELD(GTXFIFOSIZ3, TXFSTADDR_N, 16, 16)
267      FIELD(GTXFIFOSIZ3, TXFDEP_N, 0, 16)
268  REG32(GTXFIFOSIZ4, 0x210)
269      FIELD(GTXFIFOSIZ4, TXFSTADDR_N, 16, 16)
270      FIELD(GTXFIFOSIZ4, TXFDEP_N, 0, 16)
271  REG32(GTXFIFOSIZ5, 0x214)
272      FIELD(GTXFIFOSIZ5, TXFSTADDR_N, 16, 16)
273      FIELD(GTXFIFOSIZ5, TXFDEP_N, 0, 16)
274  REG32(GRXFIFOSIZ0, 0x280)
275      FIELD(GRXFIFOSIZ0, RXFSTADDR_N, 16, 16)
276      FIELD(GRXFIFOSIZ0, RXFDEP_N, 0, 16)
277  REG32(GRXFIFOSIZ1, 0x284)
278      FIELD(GRXFIFOSIZ1, RXFSTADDR_N, 16, 16)
279      FIELD(GRXFIFOSIZ1, RXFDEP_N, 0, 16)
280  REG32(GRXFIFOSIZ2, 0x288)
281      FIELD(GRXFIFOSIZ2, RXFSTADDR_N, 16, 16)
282      FIELD(GRXFIFOSIZ2, RXFDEP_N, 0, 16)
283  REG32(GEVNTADRLO_0, 0x300)
284  REG32(GEVNTADRHI_0, 0x304)
285  REG32(GEVNTSIZ_0, 0x308)
286      FIELD(GEVNTSIZ_0, EVNTINTRPTMASK, 31, 1)
287      FIELD(GEVNTSIZ_0, RESERVED_30_16, 16, 15)
288      FIELD(GEVNTSIZ_0, EVENTSIZ, 0, 16)
289  REG32(GEVNTCOUNT_0, 0x30c)
290      FIELD(GEVNTCOUNT_0, EVNT_HANDLER_BUSY, 31, 1)
291      FIELD(GEVNTCOUNT_0, RESERVED_30_16, 16, 15)
292      FIELD(GEVNTCOUNT_0, EVNTCOUNT, 0, 16)
293  REG32(GEVNTADRLO_1, 0x310)
294  REG32(GEVNTADRHI_1, 0x314)
295  REG32(GEVNTSIZ_1, 0x318)
296      FIELD(GEVNTSIZ_1, EVNTINTRPTMASK, 31, 1)
297      FIELD(GEVNTSIZ_1, RESERVED_30_16, 16, 15)
298      FIELD(GEVNTSIZ_1, EVENTSIZ, 0, 16)
299  REG32(GEVNTCOUNT_1, 0x31c)
300      FIELD(GEVNTCOUNT_1, EVNT_HANDLER_BUSY, 31, 1)
301      FIELD(GEVNTCOUNT_1, RESERVED_30_16, 16, 15)
302      FIELD(GEVNTCOUNT_1, EVNTCOUNT, 0, 16)
303  REG32(GEVNTADRLO_2, 0x320)
304  REG32(GEVNTADRHI_2, 0x324)
305  REG32(GEVNTSIZ_2, 0x328)
306      FIELD(GEVNTSIZ_2, EVNTINTRPTMASK, 31, 1)
307      FIELD(GEVNTSIZ_2, RESERVED_30_16, 16, 15)
308      FIELD(GEVNTSIZ_2, EVENTSIZ, 0, 16)
309  REG32(GEVNTCOUNT_2, 0x32c)
310      FIELD(GEVNTCOUNT_2, EVNT_HANDLER_BUSY, 31, 1)
311      FIELD(GEVNTCOUNT_2, RESERVED_30_16, 16, 15)
312      FIELD(GEVNTCOUNT_2, EVNTCOUNT, 0, 16)
313  REG32(GEVNTADRLO_3, 0x330)
314  REG32(GEVNTADRHI_3, 0x334)
315  REG32(GEVNTSIZ_3, 0x338)
316      FIELD(GEVNTSIZ_3, EVNTINTRPTMASK, 31, 1)
317      FIELD(GEVNTSIZ_3, RESERVED_30_16, 16, 15)
318      FIELD(GEVNTSIZ_3, EVENTSIZ, 0, 16)
319  REG32(GEVNTCOUNT_3, 0x33c)
320      FIELD(GEVNTCOUNT_3, EVNT_HANDLER_BUSY, 31, 1)
321      FIELD(GEVNTCOUNT_3, RESERVED_30_16, 16, 15)
322      FIELD(GEVNTCOUNT_3, EVNTCOUNT, 0, 16)
323  REG32(GHWPARAMS8, 0x500)
324  REG32(GTXFIFOPRIDEV, 0x510)
325      FIELD(GTXFIFOPRIDEV, RESERVED_31_N, 6, 26)
326      FIELD(GTXFIFOPRIDEV, GTXFIFOPRIDEV, 0, 6)
327  REG32(GTXFIFOPRIHST, 0x518)
328      FIELD(GTXFIFOPRIHST, RESERVED_31_16, 3, 29)
329      FIELD(GTXFIFOPRIHST, GTXFIFOPRIHST, 0, 3)
330  REG32(GRXFIFOPRIHST, 0x51c)
331      FIELD(GRXFIFOPRIHST, RESERVED_31_16, 3, 29)
332      FIELD(GRXFIFOPRIHST, GRXFIFOPRIHST, 0, 3)
333  REG32(GDMAHLRATIO, 0x524)
334      FIELD(GDMAHLRATIO, RESERVED_31_13, 13, 19)
335      FIELD(GDMAHLRATIO, HSTRXFIFO, 8, 5)
336      FIELD(GDMAHLRATIO, RESERVED_7_5, 5, 3)
337      FIELD(GDMAHLRATIO, HSTTXFIFO, 0, 5)
338  REG32(GFLADJ, 0x530)
339      FIELD(GFLADJ, GFLADJ_REFCLK_240MHZDECR_PLS1, 31, 1)
340      FIELD(GFLADJ, GFLADJ_REFCLK_240MHZ_DECR, 24, 7)
341      FIELD(GFLADJ, GFLADJ_REFCLK_LPM_SEL, 23, 1)
342      FIELD(GFLADJ, RESERVED_22, 22, 1)
343      FIELD(GFLADJ, GFLADJ_REFCLK_FLADJ, 8, 14)
344      FIELD(GFLADJ, GFLADJ_30MHZ_SDBND_SEL, 7, 1)
345      FIELD(GFLADJ, GFLADJ_30MHZ, 0, 6)
346  
347  #define DWC3_GLOBAL_OFFSET 0xC100
348  static void reset_csr(USBDWC3 * s)
349  {
350      int i = 0;
351      /*
352       * We reset all CSR regs except GCTL, GUCTL, GSTS, GSNPSID, GGPIO, GUID,
353       * GUSB2PHYCFGn registers and GUSB3PIPECTLn registers. We will skip PHY
354       * register as we don't implement them.
355       */
356      for (i = 0; i < USB_DWC3_R_MAX; i++) {
357          switch (i) {
358          case R_GCTL:
359              break;
360          case R_GSTS:
361              break;
362          case R_GSNPSID:
363              break;
364          case R_GGPIO:
365              break;
366          case R_GUID:
367              break;
368          case R_GUCTL:
369              break;
370          case R_GHWPARAMS0...R_GHWPARAMS7:
371              break;
372          case R_GHWPARAMS8:
373              break;
374          default:
375              register_reset(&s->regs_info[i]);
376              break;
377          }
378      }
379  
380      xhci_sysbus_reset(DEVICE(&s->sysbus_xhci));
381  }
382  
383  static void usb_dwc3_gctl_postw(RegisterInfo *reg, uint64_t val64)
384  {
385      USBDWC3 *s = USB_DWC3(reg->opaque);
386  
387      if (ARRAY_FIELD_EX32(s->regs, GCTL, CORESOFTRESET)) {
388          reset_csr(s);
389      }
390  }
391  
392  static void usb_dwc3_guid_postw(RegisterInfo *reg, uint64_t val64)
393  {
394      USBDWC3 *s = USB_DWC3(reg->opaque);
395  
396      s->regs[R_GUID] = s->cfg.dwc_usb3_user;
397  }
398  
399  static const RegisterAccessInfo usb_dwc3_regs_info[] = {
400      {   .name = "GSBUSCFG0",  .addr = A_GSBUSCFG0,
401          .ro = 0xf300,
402          .unimp = 0xffffffff,
403      },{ .name = "GSBUSCFG1",  .addr = A_GSBUSCFG1,
404          .reset = 0x300,
405          .ro = 0xffffe0ff,
406          .unimp = 0xffffffff,
407      },{ .name = "GTXTHRCFG",  .addr = A_GTXTHRCFG,
408          .ro = 0xd000ffff,
409          .unimp = 0xffffffff,
410      },{ .name = "GRXTHRCFG",  .addr = A_GRXTHRCFG,
411          .ro = 0xd007e000,
412          .unimp = 0xffffffff,
413      },{ .name = "GCTL",  .addr = A_GCTL,
414          .reset = 0x30c13004, .post_write = usb_dwc3_gctl_postw,
415      },{ .name = "GPMSTS",  .addr = A_GPMSTS,
416          .ro = 0xfffffff,
417          .unimp = 0xffffffff,
418      },{ .name = "GSTS",  .addr = A_GSTS,
419          .reset = 0x7e800000,
420          .ro = 0xffffffcf,
421          .w1c = 0x30,
422          .unimp = 0xffffffff,
423      },{ .name = "GUCTL1",  .addr = A_GUCTL1,
424          .reset = 0x198a,
425          .ro = 0x7800,
426          .unimp = 0xffffffff,
427      },{ .name = "GSNPSID",  .addr = A_GSNPSID,
428          .reset = 0x5533330a,
429          .ro = 0xffffffff,
430      },{ .name = "GGPIO",  .addr = A_GGPIO,
431          .ro = 0xffff,
432          .unimp = 0xffffffff,
433      },{ .name = "GUID",  .addr = A_GUID,
434          .reset = 0x12345678, .post_write = usb_dwc3_guid_postw,
435      },{ .name = "GUCTL",  .addr = A_GUCTL,
436          .reset = 0x0c808010,
437          .ro = 0x1c8000,
438          .unimp = 0xffffffff,
439      },{ .name = "GBUSERRADDRLO",  .addr = A_GBUSERRADDRLO,
440          .ro = 0xffffffff,
441      },{ .name = "GBUSERRADDRHI",  .addr = A_GBUSERRADDRHI,
442          .ro = 0xffffffff,
443      },{ .name = "GHWPARAMS0",  .addr = A_GHWPARAMS0,
444          .ro = 0xffffffff,
445      },{ .name = "GHWPARAMS1",  .addr = A_GHWPARAMS1,
446          .ro = 0xffffffff,
447      },{ .name = "GHWPARAMS2",  .addr = A_GHWPARAMS2,
448          .ro = 0xffffffff,
449      },{ .name = "GHWPARAMS3",  .addr = A_GHWPARAMS3,
450          .ro = 0xffffffff,
451      },{ .name = "GHWPARAMS4",  .addr = A_GHWPARAMS4,
452          .ro = 0xffffffff,
453      },{ .name = "GHWPARAMS5",  .addr = A_GHWPARAMS5,
454          .ro = 0xffffffff,
455      },{ .name = "GHWPARAMS6",  .addr = A_GHWPARAMS6,
456          .ro = 0xffffffff,
457      },{ .name = "GHWPARAMS7",  .addr = A_GHWPARAMS7,
458          .ro = 0xffffffff,
459      },{ .name = "GDBGFIFOSPACE",  .addr = A_GDBGFIFOSPACE,
460          .reset = 0xa0000,
461          .ro = 0xfffffe00,
462          .unimp = 0xffffffff,
463      },{ .name = "GUCTL2",  .addr = A_GUCTL2,
464          .reset = 0x40d,
465          .ro = 0x2000,
466          .unimp = 0xffffffff,
467      },{ .name = "GUSB2PHYCFG",  .addr = A_GUSB2PHYCFG,
468          .reset = 0x40102410,
469          .ro = 0x1e014030,
470          .unimp = 0xffffffff,
471      },{ .name = "GUSB2I2CCTL",  .addr = A_GUSB2I2CCTL,
472          .ro = 0xffffffff,
473          .unimp = 0xffffffff,
474      },{ .name = "GUSB2PHYACC_ULPI",  .addr = A_GUSB2PHYACC_ULPI,
475          .ro = 0xfd000000,
476          .unimp = 0xffffffff,
477      },{ .name = "GTXFIFOSIZ0",  .addr = A_GTXFIFOSIZ0,
478          .reset = 0x2c7000a,
479          .unimp = 0xffffffff,
480      },{ .name = "GTXFIFOSIZ1",  .addr = A_GTXFIFOSIZ1,
481          .reset = 0x2d10103,
482          .unimp = 0xffffffff,
483      },{ .name = "GTXFIFOSIZ2",  .addr = A_GTXFIFOSIZ2,
484          .reset = 0x3d40103,
485          .unimp = 0xffffffff,
486      },{ .name = "GTXFIFOSIZ3",  .addr = A_GTXFIFOSIZ3,
487          .reset = 0x4d70083,
488          .unimp = 0xffffffff,
489      },{ .name = "GTXFIFOSIZ4",  .addr = A_GTXFIFOSIZ4,
490          .reset = 0x55a0083,
491          .unimp = 0xffffffff,
492      },{ .name = "GTXFIFOSIZ5",  .addr = A_GTXFIFOSIZ5,
493          .reset = 0x5dd0083,
494          .unimp = 0xffffffff,
495      },{ .name = "GRXFIFOSIZ0",  .addr = A_GRXFIFOSIZ0,
496          .reset = 0x1c20105,
497          .unimp = 0xffffffff,
498      },{ .name = "GRXFIFOSIZ1",  .addr = A_GRXFIFOSIZ1,
499          .reset = 0x2c70000,
500          .unimp = 0xffffffff,
501      },{ .name = "GRXFIFOSIZ2",  .addr = A_GRXFIFOSIZ2,
502          .reset = 0x2c70000,
503          .unimp = 0xffffffff,
504      },{ .name = "GEVNTADRLO_0",  .addr = A_GEVNTADRLO_0,
505          .unimp = 0xffffffff,
506      },{ .name = "GEVNTADRHI_0",  .addr = A_GEVNTADRHI_0,
507          .unimp = 0xffffffff,
508      },{ .name = "GEVNTSIZ_0",  .addr = A_GEVNTSIZ_0,
509          .ro = 0x7fff0000,
510          .unimp = 0xffffffff,
511      },{ .name = "GEVNTCOUNT_0",  .addr = A_GEVNTCOUNT_0,
512          .ro = 0x7fff0000,
513          .unimp = 0xffffffff,
514      },{ .name = "GEVNTADRLO_1",  .addr = A_GEVNTADRLO_1,
515          .unimp = 0xffffffff,
516      },{ .name = "GEVNTADRHI_1",  .addr = A_GEVNTADRHI_1,
517          .unimp = 0xffffffff,
518      },{ .name = "GEVNTSIZ_1",  .addr = A_GEVNTSIZ_1,
519          .ro = 0x7fff0000,
520          .unimp = 0xffffffff,
521      },{ .name = "GEVNTCOUNT_1",  .addr = A_GEVNTCOUNT_1,
522          .ro = 0x7fff0000,
523          .unimp = 0xffffffff,
524      },{ .name = "GEVNTADRLO_2",  .addr = A_GEVNTADRLO_2,
525          .unimp = 0xffffffff,
526      },{ .name = "GEVNTADRHI_2",  .addr = A_GEVNTADRHI_2,
527          .unimp = 0xffffffff,
528      },{ .name = "GEVNTSIZ_2",  .addr = A_GEVNTSIZ_2,
529          .ro = 0x7fff0000,
530          .unimp = 0xffffffff,
531      },{ .name = "GEVNTCOUNT_2",  .addr = A_GEVNTCOUNT_2,
532          .ro = 0x7fff0000,
533          .unimp = 0xffffffff,
534      },{ .name = "GEVNTADRLO_3",  .addr = A_GEVNTADRLO_3,
535          .unimp = 0xffffffff,
536      },{ .name = "GEVNTADRHI_3",  .addr = A_GEVNTADRHI_3,
537          .unimp = 0xffffffff,
538      },{ .name = "GEVNTSIZ_3",  .addr = A_GEVNTSIZ_3,
539          .ro = 0x7fff0000,
540          .unimp = 0xffffffff,
541      },{ .name = "GEVNTCOUNT_3",  .addr = A_GEVNTCOUNT_3,
542          .ro = 0x7fff0000,
543          .unimp = 0xffffffff,
544      },{ .name = "GHWPARAMS8",  .addr = A_GHWPARAMS8,
545          .ro = 0xffffffff,
546      },{ .name = "GTXFIFOPRIDEV",  .addr = A_GTXFIFOPRIDEV,
547          .ro = 0xffffffc0,
548          .unimp = 0xffffffff,
549      },{ .name = "GTXFIFOPRIHST",  .addr = A_GTXFIFOPRIHST,
550          .ro = 0xfffffff8,
551          .unimp = 0xffffffff,
552      },{ .name = "GRXFIFOPRIHST",  .addr = A_GRXFIFOPRIHST,
553          .ro = 0xfffffff8,
554          .unimp = 0xffffffff,
555      },{ .name = "GDMAHLRATIO",  .addr = A_GDMAHLRATIO,
556          .ro = 0xffffe0e0,
557          .unimp = 0xffffffff,
558      },{ .name = "GFLADJ",  .addr = A_GFLADJ,
559          .reset = 0xc83f020,
560          .rsvd = 0x40,
561          .ro = 0x400040,
562          .unimp = 0xffffffff,
563      }
564  };
565  
566  static void usb_dwc3_reset(DeviceState *dev)
567  {
568      USBDWC3 *s = USB_DWC3(dev);
569      unsigned int i;
570  
571      for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
572          switch (i) {
573          case R_GHWPARAMS0...R_GHWPARAMS7:
574              break;
575          case R_GHWPARAMS8:
576              break;
577          default:
578              register_reset(&s->regs_info[i]);
579          };
580      }
581  
582      xhci_sysbus_reset(DEVICE(&s->sysbus_xhci));
583  }
584  
585  static const MemoryRegionOps usb_dwc3_ops = {
586      .read = register_read_memory,
587      .write = register_write_memory,
588      .endianness = DEVICE_LITTLE_ENDIAN,
589      .valid = {
590          .min_access_size = 4,
591          .max_access_size = 4,
592      },
593  };
594  
595  static void usb_dwc3_realize(DeviceState *dev, Error **errp)
596  {
597      USBDWC3 *s = USB_DWC3(dev);
598      SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
599      Error *err = NULL;
600  
601      sysbus_realize(SYS_BUS_DEVICE(&s->sysbus_xhci), &err);
602      if (err) {
603          error_propagate(errp, err);
604          return;
605      }
606  
607      memory_region_add_subregion(&s->iomem, 0,
608           sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sysbus_xhci), 0));
609      sysbus_init_mmio(sbd, &s->iomem);
610  
611      /*
612       * Device Configuration
613       */
614      s->regs[R_GHWPARAMS0] = 0x40204048 | s->cfg.mode;
615      s->regs[R_GHWPARAMS1] = 0x222493b;
616      s->regs[R_GHWPARAMS2] = 0x12345678;
617      s->regs[R_GHWPARAMS3] = 0x618c088;
618      s->regs[R_GHWPARAMS4] = 0x47822004;
619      s->regs[R_GHWPARAMS5] = 0x4202088;
620      s->regs[R_GHWPARAMS6] = 0x7850c20;
621      s->regs[R_GHWPARAMS7] = 0x0;
622      s->regs[R_GHWPARAMS8] = 0x478;
623  }
624  
625  static void usb_dwc3_init(Object *obj)
626  {
627      USBDWC3 *s = USB_DWC3(obj);
628      RegisterInfoArray *reg_array;
629  
630      memory_region_init(&s->iomem, obj, TYPE_USB_DWC3, DWC3_SIZE);
631      reg_array =
632          register_init_block32(DEVICE(obj), usb_dwc3_regs_info,
633                                ARRAY_SIZE(usb_dwc3_regs_info),
634                                s->regs_info, s->regs,
635                                &usb_dwc3_ops,
636                                USB_DWC3_ERR_DEBUG,
637                                USB_DWC3_R_MAX * 4);
638      memory_region_add_subregion(&s->iomem,
639                                  DWC3_GLOBAL_OFFSET,
640                                  &reg_array->mem);
641      object_initialize_child(obj, "dwc3-xhci", &s->sysbus_xhci,
642                              TYPE_XHCI_SYSBUS);
643      qdev_alias_all_properties(DEVICE(&s->sysbus_xhci), obj);
644  
645      s->cfg.mode = HOST_MODE;
646  }
647  
648  static const VMStateDescription vmstate_usb_dwc3 = {
649      .name = "usb-dwc3",
650      .version_id = 1,
651      .fields = (VMStateField[]) {
652          VMSTATE_UINT32_ARRAY(regs, USBDWC3, USB_DWC3_R_MAX),
653          VMSTATE_UINT8(cfg.mode, USBDWC3),
654          VMSTATE_UINT32(cfg.dwc_usb3_user, USBDWC3),
655          VMSTATE_END_OF_LIST()
656      }
657  };
658  
659  static Property usb_dwc3_properties[] = {
660      DEFINE_PROP_UINT32("DWC_USB3_USERID", USBDWC3, cfg.dwc_usb3_user,
661                         0x12345678),
662      DEFINE_PROP_END_OF_LIST(),
663  };
664  
665  static void usb_dwc3_class_init(ObjectClass *klass, void *data)
666  {
667      DeviceClass *dc = DEVICE_CLASS(klass);
668  
669      dc->reset = usb_dwc3_reset;
670      dc->realize = usb_dwc3_realize;
671      dc->vmsd = &vmstate_usb_dwc3;
672      device_class_set_props(dc, usb_dwc3_properties);
673  }
674  
675  static const TypeInfo usb_dwc3_info = {
676      .name          = TYPE_USB_DWC3,
677      .parent        = TYPE_SYS_BUS_DEVICE,
678      .instance_size = sizeof(USBDWC3),
679      .class_init    = usb_dwc3_class_init,
680      .instance_init = usb_dwc3_init,
681  };
682  
683  static void usb_dwc3_register_types(void)
684  {
685      type_register_static(&usb_dwc3_info);
686  }
687  
688  type_init(usb_dwc3_register_types)
689