1a24273bbSAndrey Smirnov /*
2a24273bbSAndrey Smirnov * Copyright (c) 2018, Impinj, Inc.
3a24273bbSAndrey Smirnov *
4a24273bbSAndrey Smirnov * Chipidea USB block emulation code
5a24273bbSAndrey Smirnov *
6a24273bbSAndrey Smirnov * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
7a24273bbSAndrey Smirnov *
8a24273bbSAndrey Smirnov * This work is licensed under the terms of the GNU GPL, version 2 or later.
9a24273bbSAndrey Smirnov * See the COPYING file in the top-level directory.
10a24273bbSAndrey Smirnov */
11a24273bbSAndrey Smirnov
12a24273bbSAndrey Smirnov #include "qemu/osdep.h"
13a24273bbSAndrey Smirnov #include "hw/usb/hcd-ehci.h"
14a24273bbSAndrey Smirnov #include "hw/usb/chipidea.h"
15*0b8fa32fSMarkus Armbruster #include "qemu/module.h"
16a24273bbSAndrey Smirnov
17a24273bbSAndrey Smirnov enum {
18a24273bbSAndrey Smirnov CHIPIDEA_USBx_DCIVERSION = 0x000,
19a24273bbSAndrey Smirnov CHIPIDEA_USBx_DCCPARAMS = 0x004,
20a24273bbSAndrey Smirnov CHIPIDEA_USBx_DCCPARAMS_HC = BIT(8),
21a24273bbSAndrey Smirnov };
22a24273bbSAndrey Smirnov
chipidea_read(void * opaque,hwaddr offset,unsigned size)23a24273bbSAndrey Smirnov static uint64_t chipidea_read(void *opaque, hwaddr offset,
24a24273bbSAndrey Smirnov unsigned size)
25a24273bbSAndrey Smirnov {
26a24273bbSAndrey Smirnov return 0;
27a24273bbSAndrey Smirnov }
28a24273bbSAndrey Smirnov
chipidea_write(void * opaque,hwaddr offset,uint64_t value,unsigned size)29a24273bbSAndrey Smirnov static void chipidea_write(void *opaque, hwaddr offset,
30a24273bbSAndrey Smirnov uint64_t value, unsigned size)
31a24273bbSAndrey Smirnov {
32a24273bbSAndrey Smirnov }
33a24273bbSAndrey Smirnov
34a24273bbSAndrey Smirnov static const struct MemoryRegionOps chipidea_ops = {
35a24273bbSAndrey Smirnov .read = chipidea_read,
36a24273bbSAndrey Smirnov .write = chipidea_write,
37a24273bbSAndrey Smirnov .endianness = DEVICE_NATIVE_ENDIAN,
38a24273bbSAndrey Smirnov .impl = {
39a24273bbSAndrey Smirnov /*
40a24273bbSAndrey Smirnov * Our device would not work correctly if the guest was doing
41a24273bbSAndrey Smirnov * unaligned access. This might not be a limitation on the
42a24273bbSAndrey Smirnov * real device but in practice there is no reason for a guest
43a24273bbSAndrey Smirnov * to access this device unaligned.
44a24273bbSAndrey Smirnov */
45a24273bbSAndrey Smirnov .min_access_size = 4,
46a24273bbSAndrey Smirnov .max_access_size = 4,
47a24273bbSAndrey Smirnov .unaligned = false,
48a24273bbSAndrey Smirnov },
49a24273bbSAndrey Smirnov };
50a24273bbSAndrey Smirnov
chipidea_dc_read(void * opaque,hwaddr offset,unsigned size)51a24273bbSAndrey Smirnov static uint64_t chipidea_dc_read(void *opaque, hwaddr offset,
52a24273bbSAndrey Smirnov unsigned size)
53a24273bbSAndrey Smirnov {
54a24273bbSAndrey Smirnov switch (offset) {
55a24273bbSAndrey Smirnov case CHIPIDEA_USBx_DCIVERSION:
56a24273bbSAndrey Smirnov return 0x1;
57a24273bbSAndrey Smirnov case CHIPIDEA_USBx_DCCPARAMS:
58a24273bbSAndrey Smirnov /*
59a24273bbSAndrey Smirnov * Real hardware (at least i.MX7) will also report the
60a24273bbSAndrey Smirnov * controller as "Device Capable" (and 8 supported endpoints),
61a24273bbSAndrey Smirnov * but there doesn't seem to be much point in doing so, since
62a24273bbSAndrey Smirnov * we don't emulate that part.
63a24273bbSAndrey Smirnov */
64a24273bbSAndrey Smirnov return CHIPIDEA_USBx_DCCPARAMS_HC;
65a24273bbSAndrey Smirnov }
66a24273bbSAndrey Smirnov
67a24273bbSAndrey Smirnov return 0;
68a24273bbSAndrey Smirnov }
69a24273bbSAndrey Smirnov
chipidea_dc_write(void * opaque,hwaddr offset,uint64_t value,unsigned size)70a24273bbSAndrey Smirnov static void chipidea_dc_write(void *opaque, hwaddr offset,
71a24273bbSAndrey Smirnov uint64_t value, unsigned size)
72a24273bbSAndrey Smirnov {
73a24273bbSAndrey Smirnov }
74a24273bbSAndrey Smirnov
75a24273bbSAndrey Smirnov static const struct MemoryRegionOps chipidea_dc_ops = {
76a24273bbSAndrey Smirnov .read = chipidea_dc_read,
77a24273bbSAndrey Smirnov .write = chipidea_dc_write,
78a24273bbSAndrey Smirnov .endianness = DEVICE_NATIVE_ENDIAN,
79a24273bbSAndrey Smirnov .impl = {
80a24273bbSAndrey Smirnov /*
81a24273bbSAndrey Smirnov * Our device would not work correctly if the guest was doing
82a24273bbSAndrey Smirnov * unaligned access. This might not be a limitation on the real
83a24273bbSAndrey Smirnov * device but in practice there is no reason for a guest to access
84a24273bbSAndrey Smirnov * this device unaligned.
85a24273bbSAndrey Smirnov */
86a24273bbSAndrey Smirnov .min_access_size = 4,
87a24273bbSAndrey Smirnov .max_access_size = 4,
88a24273bbSAndrey Smirnov .unaligned = false,
89a24273bbSAndrey Smirnov },
90a24273bbSAndrey Smirnov };
91a24273bbSAndrey Smirnov
chipidea_init(Object * obj)92a24273bbSAndrey Smirnov static void chipidea_init(Object *obj)
93a24273bbSAndrey Smirnov {
94a24273bbSAndrey Smirnov EHCIState *ehci = &SYS_BUS_EHCI(obj)->ehci;
95a24273bbSAndrey Smirnov ChipideaState *ci = CHIPIDEA(obj);
96a24273bbSAndrey Smirnov int i;
97a24273bbSAndrey Smirnov
98a24273bbSAndrey Smirnov for (i = 0; i < ARRAY_SIZE(ci->iomem); i++) {
99a24273bbSAndrey Smirnov const struct {
100a24273bbSAndrey Smirnov const char *name;
101a24273bbSAndrey Smirnov hwaddr offset;
102a24273bbSAndrey Smirnov uint64_t size;
103a24273bbSAndrey Smirnov const struct MemoryRegionOps *ops;
104a24273bbSAndrey Smirnov } regions[ARRAY_SIZE(ci->iomem)] = {
105a24273bbSAndrey Smirnov /*
106a24273bbSAndrey Smirnov * Registers located between offsets 0x000 and 0xFC
107a24273bbSAndrey Smirnov */
108a24273bbSAndrey Smirnov {
109a24273bbSAndrey Smirnov .name = TYPE_CHIPIDEA ".misc",
110a24273bbSAndrey Smirnov .offset = 0x000,
111a24273bbSAndrey Smirnov .size = 0x100,
112a24273bbSAndrey Smirnov .ops = &chipidea_ops,
113a24273bbSAndrey Smirnov },
114a24273bbSAndrey Smirnov /*
115a24273bbSAndrey Smirnov * Registers located between offsets 0x1A4 and 0x1DC
116a24273bbSAndrey Smirnov */
117a24273bbSAndrey Smirnov {
118a24273bbSAndrey Smirnov .name = TYPE_CHIPIDEA ".endpoints",
119a24273bbSAndrey Smirnov .offset = 0x1A4,
120a24273bbSAndrey Smirnov .size = 0x1DC - 0x1A4 + 4,
121a24273bbSAndrey Smirnov .ops = &chipidea_ops,
122a24273bbSAndrey Smirnov },
123a24273bbSAndrey Smirnov /*
124a24273bbSAndrey Smirnov * USB_x_DCIVERSION and USB_x_DCCPARAMS
125a24273bbSAndrey Smirnov */
126a24273bbSAndrey Smirnov {
127a24273bbSAndrey Smirnov .name = TYPE_CHIPIDEA ".dc",
128a24273bbSAndrey Smirnov .offset = 0x120,
129a24273bbSAndrey Smirnov .size = 8,
130a24273bbSAndrey Smirnov .ops = &chipidea_dc_ops,
131a24273bbSAndrey Smirnov },
132a24273bbSAndrey Smirnov };
133a24273bbSAndrey Smirnov
134a24273bbSAndrey Smirnov memory_region_init_io(&ci->iomem[i],
135a24273bbSAndrey Smirnov obj,
136a24273bbSAndrey Smirnov regions[i].ops,
137a24273bbSAndrey Smirnov ci,
138a24273bbSAndrey Smirnov regions[i].name,
139a24273bbSAndrey Smirnov regions[i].size);
140a24273bbSAndrey Smirnov
141a24273bbSAndrey Smirnov memory_region_add_subregion(&ehci->mem,
142a24273bbSAndrey Smirnov regions[i].offset,
143a24273bbSAndrey Smirnov &ci->iomem[i]);
144a24273bbSAndrey Smirnov }
145a24273bbSAndrey Smirnov }
146a24273bbSAndrey Smirnov
chipidea_class_init(ObjectClass * klass,void * data)147a24273bbSAndrey Smirnov static void chipidea_class_init(ObjectClass *klass, void *data)
148a24273bbSAndrey Smirnov {
149a24273bbSAndrey Smirnov DeviceClass *dc = DEVICE_CLASS(klass);
150a24273bbSAndrey Smirnov SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(klass);
151a24273bbSAndrey Smirnov
152a24273bbSAndrey Smirnov /*
153a24273bbSAndrey Smirnov * Offsets used were taken from i.MX7Dual Applications Processor
154a24273bbSAndrey Smirnov * Reference Manual, Rev 0.1, p. 3177, Table 11-59
155a24273bbSAndrey Smirnov */
156a24273bbSAndrey Smirnov sec->capsbase = 0x100;
157a24273bbSAndrey Smirnov sec->opregbase = 0x140;
158a24273bbSAndrey Smirnov sec->portnr = 1;
159a24273bbSAndrey Smirnov
160a24273bbSAndrey Smirnov set_bit(DEVICE_CATEGORY_USB, dc->categories);
161a24273bbSAndrey Smirnov dc->desc = "Chipidea USB Module";
162a24273bbSAndrey Smirnov }
163a24273bbSAndrey Smirnov
164a24273bbSAndrey Smirnov static const TypeInfo chipidea_info = {
165a24273bbSAndrey Smirnov .name = TYPE_CHIPIDEA,
166a24273bbSAndrey Smirnov .parent = TYPE_SYS_BUS_EHCI,
167a24273bbSAndrey Smirnov .instance_size = sizeof(ChipideaState),
168a24273bbSAndrey Smirnov .instance_init = chipidea_init,
169a24273bbSAndrey Smirnov .class_init = chipidea_class_init,
170a24273bbSAndrey Smirnov };
171a24273bbSAndrey Smirnov
chipidea_register_type(void)172a24273bbSAndrey Smirnov static void chipidea_register_type(void)
173a24273bbSAndrey Smirnov {
174a24273bbSAndrey Smirnov type_register_static(&chipidea_info);
175a24273bbSAndrey Smirnov }
176a24273bbSAndrey Smirnov type_init(chipidea_register_type)
177