1 /* 2 * Infineon tc27x SoC System emulation. 3 * 4 * Copyright (c) 2020 Andreas Konopik <andreas.konopik@efs-auto.de> 5 * Copyright (c) 2020 David Brenken <david.brenken@efs-auto.de> 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "hw/sysbus.h" 24 #include "hw/boards.h" 25 #include "hw/loader.h" 26 #include "qemu/units.h" 27 #include "hw/misc/unimp.h" 28 #include "exec/address-spaces.h" 29 #include "cpu.h" 30 31 #include "hw/tricore/tc27x_soc.h" 32 #include "hw/tricore/triboard.h" 33 34 const MemmapEntry tc27x_soc_memmap[] = { 35 [TC27XD_DSPR2] = { 0x50000000, 120 * KiB }, 36 [TC27XD_DCACHE2] = { 0x5001E000, 8 * KiB }, 37 [TC27XD_DTAG2] = { 0x500C0000, 0xC00 }, 38 [TC27XD_PSPR2] = { 0x50100000, 32 * KiB }, 39 [TC27XD_PCACHE2] = { 0x50108000, 16 * KiB }, 40 [TC27XD_PTAG2] = { 0x501C0000, 0x1800 }, 41 [TC27XD_DSPR1] = { 0x60000000, 120 * KiB }, 42 [TC27XD_DCACHE1] = { 0x6001E000, 8 * KiB }, 43 [TC27XD_DTAG1] = { 0x600C0000, 0xC00 }, 44 [TC27XD_PSPR1] = { 0x60100000, 32 * KiB }, 45 [TC27XD_PCACHE1] = { 0x60108000, 16 * KiB }, 46 [TC27XD_PTAG1] = { 0x601C0000, 0x1800 }, 47 [TC27XD_DSPR0] = { 0x70000000, 112 * KiB }, 48 [TC27XD_PSPR0] = { 0x70100000, 24 * KiB }, 49 [TC27XD_PCACHE0] = { 0x70106000, 8 * KiB }, 50 [TC27XD_PTAG0] = { 0x701C0000, 0xC00 }, 51 [TC27XD_PFLASH0_C] = { 0x80000000, 2 * MiB }, 52 [TC27XD_PFLASH1_C] = { 0x80200000, 2 * MiB }, 53 [TC27XD_OLDA_C] = { 0x8FE70000, 32 * KiB }, 54 [TC27XD_BROM_C] = { 0x8FFF8000, 32 * KiB }, 55 [TC27XD_LMURAM_C] = { 0x90000000, 32 * KiB }, 56 [TC27XD_EMEM_C] = { 0x9F000000, 1 * MiB }, 57 [TC27XD_PFLASH0_U] = { 0xA0000000, 0x0 }, 58 [TC27XD_PFLASH1_U] = { 0xA0200000, 0x0 }, 59 [TC27XD_DFLASH0] = { 0xAF000000, 1 * MiB + 16 * KiB }, 60 [TC27XD_DFLASH1] = { 0xAF110000, 64 * KiB }, 61 [TC27XD_OLDA_U] = { 0xAFE70000, 0x0 }, 62 [TC27XD_BROM_U] = { 0xAFFF8000, 0x0 }, 63 [TC27XD_LMURAM_U] = { 0xB0000000, 0x0 }, 64 [TC27XD_EMEM_U] = { 0xBF000000, 0x0 }, 65 [TC27XD_PSPRX] = { 0xC0000000, 0x0 }, 66 [TC27XD_DSPRX] = { 0xD0000000, 0x0 }, 67 }; 68 69 /* 70 * Initialize the auxiliary ROM region @mr and map it into 71 * the memory map at @base. 72 */ 73 static void make_rom(MemoryRegion *mr, const char *name, 74 hwaddr base, hwaddr size) 75 { 76 memory_region_init_rom(mr, NULL, name, size, &error_fatal); 77 memory_region_add_subregion(get_system_memory(), base, mr); 78 } 79 80 /* 81 * Initialize the auxiliary RAM region @mr and map it into 82 * the memory map at @base. 83 */ 84 static void make_ram(MemoryRegion *mr, const char *name, 85 hwaddr base, hwaddr size) 86 { 87 memory_region_init_ram(mr, NULL, name, size, &error_fatal); 88 memory_region_add_subregion(get_system_memory(), base, mr); 89 } 90 91 /* 92 * Create an alias of an entire original MemoryRegion @orig 93 * located at @base in the memory map. 94 */ 95 static void make_alias(MemoryRegion *mr, const char *name, 96 MemoryRegion *orig, hwaddr base) 97 { 98 memory_region_init_alias(mr, NULL, name, orig, 0, 99 memory_region_size(orig)); 100 memory_region_add_subregion(get_system_memory(), base, mr); 101 } 102 103 static void tc27x_soc_init_memory_mapping(DeviceState *dev_soc) 104 { 105 TC27XSoCState *s = TC27X_SOC(dev_soc); 106 TC27XSoCClass *sc = TC27X_SOC_GET_CLASS(s); 107 108 make_ram(&s->cpu0mem.dspr, "CPU0.DSPR", 109 sc->memmap[TC27XD_DSPR0].base, sc->memmap[TC27XD_DSPR0].size); 110 make_ram(&s->cpu0mem.pspr, "CPU0.PSPR", 111 sc->memmap[TC27XD_PSPR0].base, sc->memmap[TC27XD_PSPR0].size); 112 make_ram(&s->cpu1mem.dspr, "CPU1.DSPR", 113 sc->memmap[TC27XD_DSPR1].base, sc->memmap[TC27XD_DSPR1].size); 114 make_ram(&s->cpu1mem.pspr, "CPU1.PSPR", 115 sc->memmap[TC27XD_PSPR1].base, sc->memmap[TC27XD_PSPR1].size); 116 make_ram(&s->cpu2mem.dspr, "CPU2.DSPR", 117 sc->memmap[TC27XD_DSPR2].base, sc->memmap[TC27XD_DSPR2].size); 118 make_ram(&s->cpu2mem.pspr, "CPU2.PSPR", 119 sc->memmap[TC27XD_PSPR2].base, sc->memmap[TC27XD_PSPR2].size); 120 121 /* TODO: Control Cache mapping with Memory Test Unit (MTU) */ 122 make_ram(&s->cpu2mem.dcache, "CPU2.DCACHE", 123 sc->memmap[TC27XD_DCACHE2].base, sc->memmap[TC27XD_DCACHE2].size); 124 make_ram(&s->cpu2mem.dtag, "CPU2.DTAG", 125 sc->memmap[TC27XD_DTAG2].base, sc->memmap[TC27XD_DTAG2].size); 126 make_ram(&s->cpu2mem.pcache, "CPU2.PCACHE", 127 sc->memmap[TC27XD_PCACHE2].base, sc->memmap[TC27XD_PCACHE2].size); 128 make_ram(&s->cpu2mem.ptag, "CPU2.PTAG", 129 sc->memmap[TC27XD_PTAG2].base, sc->memmap[TC27XD_PTAG2].size); 130 131 make_ram(&s->cpu1mem.dcache, "CPU1.DCACHE", 132 sc->memmap[TC27XD_DCACHE1].base, sc->memmap[TC27XD_DCACHE1].size); 133 make_ram(&s->cpu1mem.dtag, "CPU1.DTAG", 134 sc->memmap[TC27XD_DTAG1].base, sc->memmap[TC27XD_DTAG1].size); 135 make_ram(&s->cpu1mem.pcache, "CPU1.PCACHE", 136 sc->memmap[TC27XD_PCACHE1].base, sc->memmap[TC27XD_PCACHE1].size); 137 make_ram(&s->cpu1mem.ptag, "CPU1.PTAG", 138 sc->memmap[TC27XD_PTAG1].base, sc->memmap[TC27XD_PTAG1].size); 139 140 make_ram(&s->cpu0mem.pcache, "CPU0.PCACHE", 141 sc->memmap[TC27XD_PCACHE0].base, sc->memmap[TC27XD_PCACHE0].size); 142 make_ram(&s->cpu0mem.ptag, "CPU0.PTAG", 143 sc->memmap[TC27XD_PTAG0].base, sc->memmap[TC27XD_PTAG0].size); 144 145 /* 146 * TriCore QEMU executes CPU0 only, thus it is sufficient to map 147 * LOCAL.PSPR/LOCAL.DSPR exclusively onto PSPR0/DSPR0. 148 */ 149 make_alias(&s->psprX, "LOCAL.PSPR", &s->cpu0mem.pspr, 150 sc->memmap[TC27XD_PSPRX].base); 151 make_alias(&s->dsprX, "LOCAL.DSPR", &s->cpu0mem.dspr, 152 sc->memmap[TC27XD_DSPRX].base); 153 154 make_ram(&s->flashmem.pflash0_c, "PF0", 155 sc->memmap[TC27XD_PFLASH0_C].base, sc->memmap[TC27XD_PFLASH0_C].size); 156 make_ram(&s->flashmem.pflash1_c, "PF1", 157 sc->memmap[TC27XD_PFLASH1_C].base, sc->memmap[TC27XD_PFLASH1_C].size); 158 make_ram(&s->flashmem.dflash0, "DF0", 159 sc->memmap[TC27XD_DFLASH0].base, sc->memmap[TC27XD_DFLASH0].size); 160 make_ram(&s->flashmem.dflash1, "DF1", 161 sc->memmap[TC27XD_DFLASH1].base, sc->memmap[TC27XD_DFLASH1].size); 162 make_ram(&s->flashmem.olda_c, "OLDA", 163 sc->memmap[TC27XD_OLDA_C].base, sc->memmap[TC27XD_OLDA_C].size); 164 make_rom(&s->flashmem.brom_c, "BROM", 165 sc->memmap[TC27XD_BROM_C].base, sc->memmap[TC27XD_BROM_C].size); 166 make_ram(&s->flashmem.lmuram_c, "LMURAM", 167 sc->memmap[TC27XD_LMURAM_C].base, sc->memmap[TC27XD_LMURAM_C].size); 168 make_ram(&s->flashmem.emem_c, "EMEM", 169 sc->memmap[TC27XD_EMEM_C].base, sc->memmap[TC27XD_EMEM_C].size); 170 171 make_alias(&s->flashmem.pflash0_u, "PF0.U", &s->flashmem.pflash0_c, 172 sc->memmap[TC27XD_PFLASH0_U].base); 173 make_alias(&s->flashmem.pflash1_u, "PF1.U", &s->flashmem.pflash1_c, 174 sc->memmap[TC27XD_PFLASH1_U].base); 175 make_alias(&s->flashmem.olda_u, "OLDA.U", &s->flashmem.olda_c, 176 sc->memmap[TC27XD_OLDA_U].base); 177 make_alias(&s->flashmem.brom_u, "BROM.U", &s->flashmem.brom_c, 178 sc->memmap[TC27XD_BROM_U].base); 179 make_alias(&s->flashmem.lmuram_u, "LMURAM.U", &s->flashmem.lmuram_c, 180 sc->memmap[TC27XD_LMURAM_U].base); 181 make_alias(&s->flashmem.emem_u, "EMEM.U", &s->flashmem.emem_c, 182 sc->memmap[TC27XD_EMEM_U].base); 183 } 184 185 static void tc27x_soc_realize(DeviceState *dev_soc, Error **errp) 186 { 187 TC27XSoCState *s = TC27X_SOC(dev_soc); 188 Error *err = NULL; 189 190 qdev_realize(DEVICE(&s->cpu), NULL, &err); 191 if (err) { 192 error_propagate(errp, err); 193 return; 194 } 195 196 tc27x_soc_init_memory_mapping(dev_soc); 197 } 198 199 static void tc27x_soc_init(Object *obj) 200 { 201 TC27XSoCState *s = TC27X_SOC(obj); 202 TC27XSoCClass *sc = TC27X_SOC_GET_CLASS(s); 203 204 object_initialize_child(obj, "tc27x", &s->cpu, sc->cpu_type); 205 } 206 207 static Property tc27x_soc_properties[] = { 208 DEFINE_PROP_END_OF_LIST(), 209 }; 210 211 static void tc27x_soc_class_init(ObjectClass *klass, void *data) 212 { 213 DeviceClass *dc = DEVICE_CLASS(klass); 214 215 dc->realize = tc27x_soc_realize; 216 device_class_set_props(dc, tc27x_soc_properties); 217 } 218 219 static void tc277d_soc_class_init(ObjectClass *oc, void *data) 220 { 221 TC27XSoCClass *sc = TC27X_SOC_CLASS(oc); 222 223 sc->name = "tc277d-soc"; 224 sc->cpu_type = TRICORE_CPU_TYPE_NAME("tc27x"); 225 sc->memmap = tc27x_soc_memmap; 226 sc->num_cpus = 1; 227 } 228 229 static const TypeInfo tc27x_soc_types[] = { 230 { 231 .name = "tc277d-soc", 232 .parent = TYPE_TC27X_SOC, 233 .class_init = tc277d_soc_class_init, 234 }, { 235 .name = TYPE_TC27X_SOC, 236 .parent = TYPE_SYS_BUS_DEVICE, 237 .instance_size = sizeof(TC27XSoCState), 238 .instance_init = tc27x_soc_init, 239 .class_size = sizeof(TC27XSoCClass), 240 .class_init = tc27x_soc_class_init, 241 .abstract = true, 242 }, 243 }; 244 245 DEFINE_TYPES(tc27x_soc_types) 246