1 /* 2 * tpm_crb.c - QEMU's TPM CRB interface emulator 3 * 4 * Copyright (c) 2018 Red Hat, Inc. 5 * 6 * Authors: 7 * Marc-André Lureau <marcandre.lureau@redhat.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or later. 10 * See the COPYING file in the top-level directory. 11 * 12 * tpm_crb is a device for TPM 2.0 Command Response Buffer (CRB) Interface 13 * as defined in TCG PC Client Platform TPM Profile (PTP) Specification 14 * Family “2.0” Level 00 Revision 01.03 v22 15 */ 16 17 #include "qemu/osdep.h" 18 19 #include "qemu-common.h" 20 #include "qapi/error.h" 21 #include "exec/address-spaces.h" 22 23 #include "hw/qdev-core.h" 24 #include "hw/qdev-properties.h" 25 #include "hw/pci/pci_ids.h" 26 #include "hw/acpi/tpm.h" 27 #include "migration/vmstate.h" 28 #include "sysemu/tpm_backend.h" 29 #include "tpm_int.h" 30 #include "tpm_util.h" 31 32 typedef struct CRBState { 33 DeviceState parent_obj; 34 35 TPMBackend *tpmbe; 36 TPMBackendCmd cmd; 37 uint32_t regs[TPM_CRB_R_MAX]; 38 MemoryRegion mmio; 39 MemoryRegion cmdmem; 40 41 size_t be_buffer_size; 42 } CRBState; 43 44 #define CRB(obj) OBJECT_CHECK(CRBState, (obj), TYPE_TPM_CRB) 45 46 #define DEBUG_CRB 0 47 48 #define DPRINTF(fmt, ...) do { \ 49 if (DEBUG_CRB) { \ 50 printf(fmt, ## __VA_ARGS__); \ 51 } \ 52 } while (0) 53 54 #define CRB_INTF_TYPE_CRB_ACTIVE 0b1 55 #define CRB_INTF_VERSION_CRB 0b1 56 #define CRB_INTF_CAP_LOCALITY_0_ONLY 0b0 57 #define CRB_INTF_CAP_IDLE_FAST 0b0 58 #define CRB_INTF_CAP_XFER_SIZE_64 0b11 59 #define CRB_INTF_CAP_FIFO_NOT_SUPPORTED 0b0 60 #define CRB_INTF_CAP_CRB_SUPPORTED 0b1 61 #define CRB_INTF_IF_SELECTOR_CRB 0b1 62 63 #define CRB_CTRL_CMD_SIZE (TPM_CRB_ADDR_SIZE - A_CRB_DATA_BUFFER) 64 65 enum crb_loc_ctrl { 66 CRB_LOC_CTRL_REQUEST_ACCESS = BIT(0), 67 CRB_LOC_CTRL_RELINQUISH = BIT(1), 68 CRB_LOC_CTRL_SEIZE = BIT(2), 69 CRB_LOC_CTRL_RESET_ESTABLISHMENT_BIT = BIT(3), 70 }; 71 72 enum crb_ctrl_req { 73 CRB_CTRL_REQ_CMD_READY = BIT(0), 74 CRB_CTRL_REQ_GO_IDLE = BIT(1), 75 }; 76 77 enum crb_start { 78 CRB_START_INVOKE = BIT(0), 79 }; 80 81 enum crb_cancel { 82 CRB_CANCEL_INVOKE = BIT(0), 83 }; 84 85 static uint64_t tpm_crb_mmio_read(void *opaque, hwaddr addr, 86 unsigned size) 87 { 88 CRBState *s = CRB(opaque); 89 void *regs = (void *)&s->regs + (addr & ~3); 90 unsigned offset = addr & 3; 91 uint32_t val = *(uint32_t *)regs >> (8 * offset); 92 93 DPRINTF("CRB read 0x" TARGET_FMT_plx " len:%u val: 0x%" PRIx32 "\n", 94 addr, size, val); 95 return val; 96 } 97 98 static void tpm_crb_mmio_write(void *opaque, hwaddr addr, 99 uint64_t val, unsigned size) 100 { 101 CRBState *s = CRB(opaque); 102 DPRINTF("CRB write 0x" TARGET_FMT_plx " len:%u val: 0x%" PRIx64 "\n", 103 addr, size, val); 104 105 switch (addr) { 106 case A_CRB_CTRL_REQ: 107 switch (val) { 108 case CRB_CTRL_REQ_CMD_READY: 109 ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, 110 tpmIdle, 0); 111 break; 112 case CRB_CTRL_REQ_GO_IDLE: 113 ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, 114 tpmIdle, 1); 115 break; 116 } 117 break; 118 case A_CRB_CTRL_CANCEL: 119 if (val == CRB_CANCEL_INVOKE && 120 s->regs[R_CRB_CTRL_START] & CRB_START_INVOKE) { 121 tpm_backend_cancel_cmd(s->tpmbe); 122 } 123 break; 124 case A_CRB_CTRL_START: 125 if (val == CRB_START_INVOKE && 126 !(s->regs[R_CRB_CTRL_START] & CRB_START_INVOKE)) { 127 void *mem = memory_region_get_ram_ptr(&s->cmdmem); 128 129 s->regs[R_CRB_CTRL_START] |= CRB_START_INVOKE; 130 s->cmd = (TPMBackendCmd) { 131 .in = mem, 132 .in_len = MIN(tpm_cmd_get_size(mem), s->be_buffer_size), 133 .out = mem, 134 .out_len = s->be_buffer_size, 135 }; 136 137 tpm_backend_deliver_request(s->tpmbe, &s->cmd); 138 } 139 break; 140 case A_CRB_LOC_CTRL: 141 switch (val) { 142 case CRB_LOC_CTRL_RESET_ESTABLISHMENT_BIT: 143 /* not loc 3 or 4 */ 144 break; 145 case CRB_LOC_CTRL_RELINQUISH: 146 break; 147 case CRB_LOC_CTRL_REQUEST_ACCESS: 148 ARRAY_FIELD_DP32(s->regs, CRB_LOC_STS, 149 Granted, 1); 150 ARRAY_FIELD_DP32(s->regs, CRB_LOC_STS, 151 beenSeized, 0); 152 ARRAY_FIELD_DP32(s->regs, CRB_LOC_STATE, 153 locAssigned, 1); 154 ARRAY_FIELD_DP32(s->regs, CRB_LOC_STATE, 155 tpmRegValidSts, 1); 156 break; 157 } 158 break; 159 } 160 } 161 162 static const MemoryRegionOps tpm_crb_memory_ops = { 163 .read = tpm_crb_mmio_read, 164 .write = tpm_crb_mmio_write, 165 .endianness = DEVICE_LITTLE_ENDIAN, 166 .valid = { 167 .min_access_size = 1, 168 .max_access_size = 4, 169 }, 170 }; 171 172 static void tpm_crb_request_completed(TPMIf *ti, int ret) 173 { 174 CRBState *s = CRB(ti); 175 176 s->regs[R_CRB_CTRL_START] &= ~CRB_START_INVOKE; 177 if (ret != 0) { 178 ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, 179 tpmSts, 1); /* fatal error */ 180 } 181 } 182 183 static enum TPMVersion tpm_crb_get_version(TPMIf *ti) 184 { 185 CRBState *s = CRB(ti); 186 187 return tpm_backend_get_tpm_version(s->tpmbe); 188 } 189 190 static int tpm_crb_pre_save(void *opaque) 191 { 192 CRBState *s = opaque; 193 194 tpm_backend_finish_sync(s->tpmbe); 195 196 return 0; 197 } 198 199 static const VMStateDescription vmstate_tpm_crb = { 200 .name = "tpm-crb", 201 .pre_save = tpm_crb_pre_save, 202 .fields = (VMStateField[]) { 203 VMSTATE_UINT32_ARRAY(regs, CRBState, TPM_CRB_R_MAX), 204 VMSTATE_END_OF_LIST(), 205 } 206 }; 207 208 static Property tpm_crb_properties[] = { 209 DEFINE_PROP_TPMBE("tpmdev", CRBState, tpmbe), 210 DEFINE_PROP_END_OF_LIST(), 211 }; 212 213 static void tpm_crb_realize(DeviceState *dev, Error **errp) 214 { 215 CRBState *s = CRB(dev); 216 217 if (!tpm_find()) { 218 error_setg(errp, "at most one TPM device is permitted"); 219 return; 220 } 221 if (!s->tpmbe) { 222 error_setg(errp, "'tpmdev' property is required"); 223 return; 224 } 225 226 memory_region_init_io(&s->mmio, OBJECT(s), &tpm_crb_memory_ops, s, 227 "tpm-crb-mmio", sizeof(s->regs)); 228 memory_region_init_ram(&s->cmdmem, OBJECT(s), 229 "tpm-crb-cmd", CRB_CTRL_CMD_SIZE, errp); 230 231 memory_region_add_subregion(get_system_memory(), 232 TPM_CRB_ADDR_BASE, &s->mmio); 233 memory_region_add_subregion(get_system_memory(), 234 TPM_CRB_ADDR_BASE + sizeof(s->regs), &s->cmdmem); 235 236 tpm_backend_reset(s->tpmbe); 237 238 ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, 239 InterfaceType, CRB_INTF_TYPE_CRB_ACTIVE); 240 ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, 241 InterfaceVersion, CRB_INTF_VERSION_CRB); 242 ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, 243 CapLocality, CRB_INTF_CAP_LOCALITY_0_ONLY); 244 ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, 245 CapCRBIdleBypass, CRB_INTF_CAP_IDLE_FAST); 246 ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, 247 CapDataXferSizeSupport, CRB_INTF_CAP_XFER_SIZE_64); 248 ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, 249 CapFIFO, CRB_INTF_CAP_FIFO_NOT_SUPPORTED); 250 ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, 251 CapCRB, CRB_INTF_CAP_CRB_SUPPORTED); 252 ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, 253 InterfaceSelector, CRB_INTF_IF_SELECTOR_CRB); 254 ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, 255 RID, 0b0000); 256 ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID2, 257 VID, PCI_VENDOR_ID_IBM); 258 259 s->regs[R_CRB_CTRL_CMD_SIZE] = CRB_CTRL_CMD_SIZE; 260 s->regs[R_CRB_CTRL_CMD_LADDR] = TPM_CRB_ADDR_BASE + A_CRB_DATA_BUFFER; 261 s->regs[R_CRB_CTRL_RSP_SIZE] = CRB_CTRL_CMD_SIZE; 262 s->regs[R_CRB_CTRL_RSP_ADDR] = TPM_CRB_ADDR_BASE + A_CRB_DATA_BUFFER; 263 264 s->be_buffer_size = MIN(tpm_backend_get_buffer_size(s->tpmbe), 265 CRB_CTRL_CMD_SIZE); 266 267 tpm_backend_startup_tpm(s->tpmbe, s->be_buffer_size); 268 } 269 270 static void tpm_crb_class_init(ObjectClass *klass, void *data) 271 { 272 DeviceClass *dc = DEVICE_CLASS(klass); 273 TPMIfClass *tc = TPM_IF_CLASS(klass); 274 275 dc->realize = tpm_crb_realize; 276 dc->props = tpm_crb_properties; 277 dc->vmsd = &vmstate_tpm_crb; 278 dc->user_creatable = true; 279 tc->model = TPM_MODEL_TPM_CRB; 280 tc->get_version = tpm_crb_get_version; 281 tc->request_completed = tpm_crb_request_completed; 282 283 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 284 } 285 286 static const TypeInfo tpm_crb_info = { 287 .name = TYPE_TPM_CRB, 288 /* could be TYPE_SYS_BUS_DEVICE (or LPC etc) */ 289 .parent = TYPE_DEVICE, 290 .instance_size = sizeof(CRBState), 291 .class_init = tpm_crb_class_init, 292 .interfaces = (InterfaceInfo[]) { 293 { TYPE_TPM_IF }, 294 { } 295 } 296 }; 297 298 static void tpm_crb_register(void) 299 { 300 type_register_static(&tpm_crb_info); 301 } 302 303 type_init(tpm_crb_register) 304