1 /* 2 * QEMU model of the Xilinx timer block. 3 * 4 * Copyright (c) 2009 Edgar E. Iglesias. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/sysbus.h" 27 #include "hw/irq.h" 28 #include "hw/ptimer.h" 29 #include "qemu/log.h" 30 #include "qemu/main-loop.h" 31 #include "qemu/module.h" 32 33 #define D(x) 34 35 #define R_TCSR 0 36 #define R_TLR 1 37 #define R_TCR 2 38 #define R_MAX 4 39 40 #define TCSR_MDT (1<<0) 41 #define TCSR_UDT (1<<1) 42 #define TCSR_GENT (1<<2) 43 #define TCSR_CAPT (1<<3) 44 #define TCSR_ARHT (1<<4) 45 #define TCSR_LOAD (1<<5) 46 #define TCSR_ENIT (1<<6) 47 #define TCSR_ENT (1<<7) 48 #define TCSR_TINT (1<<8) 49 #define TCSR_PWMA (1<<9) 50 #define TCSR_ENALL (1<<10) 51 52 struct xlx_timer 53 { 54 QEMUBH *bh; 55 ptimer_state *ptimer; 56 void *parent; 57 int nr; /* for debug. */ 58 59 unsigned long timer_div; 60 61 uint32_t regs[R_MAX]; 62 }; 63 64 #define TYPE_XILINX_TIMER "xlnx.xps-timer" 65 #define XILINX_TIMER(obj) \ 66 OBJECT_CHECK(struct timerblock, (obj), TYPE_XILINX_TIMER) 67 68 struct timerblock 69 { 70 SysBusDevice parent_obj; 71 72 MemoryRegion mmio; 73 qemu_irq irq; 74 uint8_t one_timer_only; 75 uint32_t freq_hz; 76 struct xlx_timer *timers; 77 }; 78 79 static inline unsigned int num_timers(struct timerblock *t) 80 { 81 return 2 - t->one_timer_only; 82 } 83 84 static inline unsigned int timer_from_addr(hwaddr addr) 85 { 86 /* Timers get a 4x32bit control reg area each. */ 87 return addr >> 2; 88 } 89 90 static void timer_update_irq(struct timerblock *t) 91 { 92 unsigned int i, irq = 0; 93 uint32_t csr; 94 95 for (i = 0; i < num_timers(t); i++) { 96 csr = t->timers[i].regs[R_TCSR]; 97 irq |= (csr & TCSR_TINT) && (csr & TCSR_ENIT); 98 } 99 100 /* All timers within the same slave share a single IRQ line. */ 101 qemu_set_irq(t->irq, !!irq); 102 } 103 104 static uint64_t 105 timer_read(void *opaque, hwaddr addr, unsigned int size) 106 { 107 struct timerblock *t = opaque; 108 struct xlx_timer *xt; 109 uint32_t r = 0; 110 unsigned int timer; 111 112 addr >>= 2; 113 timer = timer_from_addr(addr); 114 xt = &t->timers[timer]; 115 /* Further decoding to address a specific timers reg. */ 116 addr &= 0x3; 117 switch (addr) 118 { 119 case R_TCR: 120 r = ptimer_get_count(xt->ptimer); 121 if (!(xt->regs[R_TCSR] & TCSR_UDT)) 122 r = ~r; 123 D(qemu_log("xlx_timer t=%d read counter=%x udt=%d\n", 124 timer, r, xt->regs[R_TCSR] & TCSR_UDT)); 125 break; 126 default: 127 if (addr < ARRAY_SIZE(xt->regs)) 128 r = xt->regs[addr]; 129 break; 130 131 } 132 D(fprintf(stderr, "%s timer=%d %x=%x\n", __func__, timer, addr * 4, r)); 133 return r; 134 } 135 136 static void timer_enable(struct xlx_timer *xt) 137 { 138 uint64_t count; 139 140 D(fprintf(stderr, "%s timer=%d down=%d\n", __func__, 141 xt->nr, xt->regs[R_TCSR] & TCSR_UDT)); 142 143 ptimer_stop(xt->ptimer); 144 145 if (xt->regs[R_TCSR] & TCSR_UDT) 146 count = xt->regs[R_TLR]; 147 else 148 count = ~0 - xt->regs[R_TLR]; 149 ptimer_set_limit(xt->ptimer, count, 1); 150 ptimer_run(xt->ptimer, 1); 151 } 152 153 static void 154 timer_write(void *opaque, hwaddr addr, 155 uint64_t val64, unsigned int size) 156 { 157 struct timerblock *t = opaque; 158 struct xlx_timer *xt; 159 unsigned int timer; 160 uint32_t value = val64; 161 162 addr >>= 2; 163 timer = timer_from_addr(addr); 164 xt = &t->timers[timer]; 165 D(fprintf(stderr, "%s addr=%x val=%x (timer=%d off=%d)\n", 166 __func__, addr * 4, value, timer, addr & 3)); 167 /* Further decoding to address a specific timers reg. */ 168 addr &= 3; 169 switch (addr) 170 { 171 case R_TCSR: 172 if (value & TCSR_TINT) 173 value &= ~TCSR_TINT; 174 175 xt->regs[addr] = value & 0x7ff; 176 if (value & TCSR_ENT) 177 timer_enable(xt); 178 break; 179 180 default: 181 if (addr < ARRAY_SIZE(xt->regs)) 182 xt->regs[addr] = value; 183 break; 184 } 185 timer_update_irq(t); 186 } 187 188 static const MemoryRegionOps timer_ops = { 189 .read = timer_read, 190 .write = timer_write, 191 .endianness = DEVICE_NATIVE_ENDIAN, 192 .valid = { 193 .min_access_size = 4, 194 .max_access_size = 4 195 } 196 }; 197 198 static void timer_hit(void *opaque) 199 { 200 struct xlx_timer *xt = opaque; 201 struct timerblock *t = xt->parent; 202 D(fprintf(stderr, "%s %d\n", __func__, xt->nr)); 203 xt->regs[R_TCSR] |= TCSR_TINT; 204 205 if (xt->regs[R_TCSR] & TCSR_ARHT) 206 timer_enable(xt); 207 timer_update_irq(t); 208 } 209 210 static void xilinx_timer_realize(DeviceState *dev, Error **errp) 211 { 212 struct timerblock *t = XILINX_TIMER(dev); 213 unsigned int i; 214 215 /* Init all the ptimers. */ 216 t->timers = g_malloc0(sizeof t->timers[0] * num_timers(t)); 217 for (i = 0; i < num_timers(t); i++) { 218 struct xlx_timer *xt = &t->timers[i]; 219 220 xt->parent = t; 221 xt->nr = i; 222 xt->bh = qemu_bh_new(timer_hit, xt); 223 xt->ptimer = ptimer_init(xt->bh, PTIMER_POLICY_DEFAULT); 224 ptimer_set_freq(xt->ptimer, t->freq_hz); 225 } 226 227 memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, "xlnx.xps-timer", 228 R_MAX * 4 * num_timers(t)); 229 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &t->mmio); 230 } 231 232 static void xilinx_timer_init(Object *obj) 233 { 234 struct timerblock *t = XILINX_TIMER(obj); 235 236 /* All timers share a single irq line. */ 237 sysbus_init_irq(SYS_BUS_DEVICE(obj), &t->irq); 238 } 239 240 static Property xilinx_timer_properties[] = { 241 DEFINE_PROP_UINT32("clock-frequency", struct timerblock, freq_hz, 242 62 * 1000000), 243 DEFINE_PROP_UINT8("one-timer-only", struct timerblock, one_timer_only, 0), 244 DEFINE_PROP_END_OF_LIST(), 245 }; 246 247 static void xilinx_timer_class_init(ObjectClass *klass, void *data) 248 { 249 DeviceClass *dc = DEVICE_CLASS(klass); 250 251 dc->realize = xilinx_timer_realize; 252 dc->props = xilinx_timer_properties; 253 } 254 255 static const TypeInfo xilinx_timer_info = { 256 .name = TYPE_XILINX_TIMER, 257 .parent = TYPE_SYS_BUS_DEVICE, 258 .instance_size = sizeof(struct timerblock), 259 .instance_init = xilinx_timer_init, 260 .class_init = xilinx_timer_class_init, 261 }; 262 263 static void xilinx_timer_register_types(void) 264 { 265 type_register_static(&xilinx_timer_info); 266 } 267 268 type_init(xilinx_timer_register_types) 269