xref: /openbmc/qemu/hw/timer/trace-events (revision c3e203f30d4f09879f8cadbc951f5bb7ca55a209)
1*c3e203f3SDaniel P. Berrange# See docs/trace-events.txt for syntax documentation.
2*c3e203f3SDaniel P. Berrange
3*c3e203f3SDaniel P. Berrange# hw/timer/slavio_timer.c
4*c3e203f3SDaniel P. Berrangeslavio_timer_get_out(uint64_t limit, uint32_t counthigh, uint32_t count) "limit %"PRIx64" count %x%08x"
5*c3e203f3SDaniel P. Berrangeslavio_timer_irq(uint32_t counthigh, uint32_t count) "callback: count %x%08x"
6*c3e203f3SDaniel P. Berrangeslavio_timer_mem_readl_invalid(uint64_t addr) "invalid read address %"PRIx64
7*c3e203f3SDaniel P. Berrangeslavio_timer_mem_readl(uint64_t addr, uint32_t ret) "read %"PRIx64" = %08x"
8*c3e203f3SDaniel P. Berrangeslavio_timer_mem_writel(uint64_t addr, uint32_t val) "write %"PRIx64" = %08x"
9*c3e203f3SDaniel P. Berrangeslavio_timer_mem_writel_limit(unsigned int timer_index, uint64_t count) "processor %d user timer set to %016"PRIx64
10*c3e203f3SDaniel P. Berrangeslavio_timer_mem_writel_counter_invalid(void) "not user timer"
11*c3e203f3SDaniel P. Berrangeslavio_timer_mem_writel_status_start(unsigned int timer_index) "processor %d user timer started"
12*c3e203f3SDaniel P. Berrangeslavio_timer_mem_writel_status_stop(unsigned int timer_index) "processor %d user timer stopped"
13*c3e203f3SDaniel P. Berrangeslavio_timer_mem_writel_mode_user(unsigned int timer_index) "processor %d changed from counter to user timer"
14*c3e203f3SDaniel P. Berrangeslavio_timer_mem_writel_mode_counter(unsigned int timer_index) "processor %d changed from user timer to counter"
15*c3e203f3SDaniel P. Berrangeslavio_timer_mem_writel_mode_invalid(void) "not system timer"
16*c3e203f3SDaniel P. Berrangeslavio_timer_mem_writel_invalid(uint64_t addr) "invalid write address %"PRIx64
17*c3e203f3SDaniel P. Berrange
18*c3e203f3SDaniel P. Berrange# hw/timer/grlib_gptimer.c
19*c3e203f3SDaniel P. Berrangegrlib_gptimer_enable(int id, uint32_t count) "timer:%d set count 0x%x and run"
20*c3e203f3SDaniel P. Berrangegrlib_gptimer_disabled(int id, uint32_t config) "timer:%d Timer disable config 0x%x"
21*c3e203f3SDaniel P. Berrangegrlib_gptimer_restart(int id, uint32_t reload) "timer:%d reload val: 0x%x"
22*c3e203f3SDaniel P. Berrangegrlib_gptimer_set_scaler(uint32_t scaler, uint32_t freq) "scaler:0x%x freq: 0x%x"
23*c3e203f3SDaniel P. Berrangegrlib_gptimer_hit(int id) "timer:%d HIT"
24*c3e203f3SDaniel P. Berrangegrlib_gptimer_readl(int id, uint64_t addr, uint32_t val) "timer:%d addr 0x%"PRIx64" 0x%x"
25*c3e203f3SDaniel P. Berrangegrlib_gptimer_writel(int id, uint64_t addr, uint32_t val) "timer:%d addr 0x%"PRIx64" 0x%x"
26*c3e203f3SDaniel P. Berrange
27*c3e203f3SDaniel P. Berrange# hw/timer/lm32_timer.c
28*c3e203f3SDaniel P. Berrangelm32_timer_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
29*c3e203f3SDaniel P. Berrangelm32_timer_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
30*c3e203f3SDaniel P. Berrangelm32_timer_hit(void) "timer hit"
31*c3e203f3SDaniel P. Berrangelm32_timer_irq_state(int level) "irq state %d"
32*c3e203f3SDaniel P. Berrange
33*c3e203f3SDaniel P. Berrange# hw/timer/milkymist-sysctl.c
34*c3e203f3SDaniel P. Berrangemilkymist_sysctl_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x"
35*c3e203f3SDaniel P. Berrangemilkymist_sysctl_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x"
36*c3e203f3SDaniel P. Berrangemilkymist_sysctl_icap_write(uint32_t value) "value %08x"
37*c3e203f3SDaniel P. Berrangemilkymist_sysctl_start_timer0(void) "Start timer0"
38*c3e203f3SDaniel P. Berrangemilkymist_sysctl_stop_timer0(void) "Stop timer0"
39*c3e203f3SDaniel P. Berrangemilkymist_sysctl_start_timer1(void) "Start timer1"
40*c3e203f3SDaniel P. Berrangemilkymist_sysctl_stop_timer1(void) "Stop timer1"
41*c3e203f3SDaniel P. Berrangemilkymist_sysctl_pulse_irq_timer0(void) "Pulse IRQ Timer0"
42*c3e203f3SDaniel P. Berrangemilkymist_sysctl_pulse_irq_timer1(void) "Pulse IRQ Timer1"
43*c3e203f3SDaniel P. Berrange
44*c3e203f3SDaniel P. Berrange# hw/timer/aspeed_timer.c
45*c3e203f3SDaniel P. Berrangeaspeed_timer_ctrl_enable(uint8_t i, bool enable) "Timer %" PRIu8 ": %d"
46*c3e203f3SDaniel P. Berrangeaspeed_timer_ctrl_external_clock(uint8_t i, bool enable) "Timer %" PRIu8 ": %d"
47*c3e203f3SDaniel P. Berrangeaspeed_timer_ctrl_overflow_interrupt(uint8_t i, bool enable) "Timer %" PRIu8 ": %d"
48*c3e203f3SDaniel P. Berrangeaspeed_timer_ctrl_pulse_enable(uint8_t i, bool enable) "Timer %" PRIu8 ": %d"
49*c3e203f3SDaniel P. Berrangeaspeed_timer_set_ctrl2(uint32_t value) "Value: 0x%" PRIx32
50*c3e203f3SDaniel P. Berrangeaspeed_timer_set_value(int timer, int reg, uint32_t value) "Timer %d register %d: 0x%" PRIx32
51*c3e203f3SDaniel P. Berrangeaspeed_timer_read(uint64_t offset, unsigned size, uint64_t value) "From 0x%" PRIx64 ": of size %u: 0x%" PRIx64
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