1 /* 2 * STM32F2XX Timer 3 * 4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "hw/timer/stm32f2xx_timer.h" 26 27 #ifndef STM_TIMER_ERR_DEBUG 28 #define STM_TIMER_ERR_DEBUG 0 29 #endif 30 31 #define DB_PRINT_L(lvl, fmt, args...) do { \ 32 if (STM_TIMER_ERR_DEBUG >= lvl) { \ 33 qemu_log("%s: " fmt, __func__, ## args); \ 34 } \ 35 } while (0); 36 37 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) 38 39 static void stm32f2xx_timer_set_alarm(STM32F2XXTimerState *s, int64_t now); 40 41 static void stm32f2xx_timer_interrupt(void *opaque) 42 { 43 STM32F2XXTimerState *s = opaque; 44 45 DB_PRINT("Interrupt\n"); 46 47 if (s->tim_dier & TIM_DIER_UIE && s->tim_cr1 & TIM_CR1_CEN) { 48 s->tim_sr |= 1; 49 qemu_irq_pulse(s->irq); 50 stm32f2xx_timer_set_alarm(s, s->hit_time); 51 } 52 } 53 54 static inline int64_t stm32f2xx_ns_to_ticks(STM32F2XXTimerState *s, int64_t t) 55 { 56 return muldiv64(t, s->freq_hz, 1000000000ULL) / (s->tim_psc + 1); 57 } 58 59 static void stm32f2xx_timer_set_alarm(STM32F2XXTimerState *s, int64_t now) 60 { 61 uint64_t ticks; 62 int64_t now_ticks; 63 64 if (s->tim_arr == 0) { 65 return; 66 } 67 68 DB_PRINT("Alarm set at: 0x%x\n", s->tim_cr1); 69 70 now_ticks = stm32f2xx_ns_to_ticks(s, now); 71 ticks = s->tim_arr - (now_ticks - s->tick_offset); 72 73 DB_PRINT("Alarm set in %d ticks\n", (int) ticks); 74 75 s->hit_time = muldiv64((ticks + (uint64_t) now_ticks) * (s->tim_psc + 1), 76 1000000000ULL, s->freq_hz); 77 78 timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->hit_time); 79 DB_PRINT("Wait Time: %" PRId64 " ticks\n", s->hit_time); 80 } 81 82 static void stm32f2xx_timer_reset(DeviceState *dev) 83 { 84 STM32F2XXTimerState *s = STM32F2XXTIMER(dev); 85 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 86 87 s->tim_cr1 = 0; 88 s->tim_cr2 = 0; 89 s->tim_smcr = 0; 90 s->tim_dier = 0; 91 s->tim_sr = 0; 92 s->tim_egr = 0; 93 s->tim_ccmr1 = 0; 94 s->tim_ccmr2 = 0; 95 s->tim_ccer = 0; 96 s->tim_psc = 0; 97 s->tim_arr = 0; 98 s->tim_ccr1 = 0; 99 s->tim_ccr2 = 0; 100 s->tim_ccr3 = 0; 101 s->tim_ccr4 = 0; 102 s->tim_dcr = 0; 103 s->tim_dmar = 0; 104 s->tim_or = 0; 105 106 s->tick_offset = stm32f2xx_ns_to_ticks(s, now); 107 } 108 109 static uint64_t stm32f2xx_timer_read(void *opaque, hwaddr offset, 110 unsigned size) 111 { 112 STM32F2XXTimerState *s = opaque; 113 114 DB_PRINT("Read 0x%"HWADDR_PRIx"\n", offset); 115 116 switch (offset) { 117 case TIM_CR1: 118 return s->tim_cr1; 119 case TIM_CR2: 120 return s->tim_cr2; 121 case TIM_SMCR: 122 return s->tim_smcr; 123 case TIM_DIER: 124 return s->tim_dier; 125 case TIM_SR: 126 return s->tim_sr; 127 case TIM_EGR: 128 return s->tim_egr; 129 case TIM_CCMR1: 130 return s->tim_ccmr1; 131 case TIM_CCMR2: 132 return s->tim_ccmr2; 133 case TIM_CCER: 134 return s->tim_ccer; 135 case TIM_CNT: 136 return stm32f2xx_ns_to_ticks(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) - 137 s->tick_offset; 138 case TIM_PSC: 139 return s->tim_psc; 140 case TIM_ARR: 141 return s->tim_arr; 142 case TIM_CCR1: 143 return s->tim_ccr1; 144 case TIM_CCR2: 145 return s->tim_ccr2; 146 case TIM_CCR3: 147 return s->tim_ccr3; 148 case TIM_CCR4: 149 return s->tim_ccr4; 150 case TIM_DCR: 151 return s->tim_dcr; 152 case TIM_DMAR: 153 return s->tim_dmar; 154 case TIM_OR: 155 return s->tim_or; 156 default: 157 qemu_log_mask(LOG_GUEST_ERROR, 158 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, offset); 159 } 160 161 return 0; 162 } 163 164 static void stm32f2xx_timer_write(void *opaque, hwaddr offset, 165 uint64_t val64, unsigned size) 166 { 167 STM32F2XXTimerState *s = opaque; 168 uint32_t value = val64; 169 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 170 uint32_t timer_val = 0; 171 172 DB_PRINT("Write 0x%x, 0x%"HWADDR_PRIx"\n", value, offset); 173 174 switch (offset) { 175 case TIM_CR1: 176 s->tim_cr1 = value; 177 return; 178 case TIM_CR2: 179 s->tim_cr2 = value; 180 return; 181 case TIM_SMCR: 182 s->tim_smcr = value; 183 return; 184 case TIM_DIER: 185 s->tim_dier = value; 186 return; 187 case TIM_SR: 188 /* This is set by hardware and cleared by software */ 189 s->tim_sr &= value; 190 return; 191 case TIM_EGR: 192 s->tim_egr = value; 193 if (s->tim_egr & TIM_EGR_UG) { 194 timer_val = 0; 195 break; 196 } 197 return; 198 case TIM_CCMR1: 199 s->tim_ccmr1 = value; 200 return; 201 case TIM_CCMR2: 202 s->tim_ccmr2 = value; 203 return; 204 case TIM_CCER: 205 s->tim_ccer = value; 206 return; 207 case TIM_PSC: 208 timer_val = stm32f2xx_ns_to_ticks(s, now) - s->tick_offset; 209 s->tim_psc = value; 210 value = timer_val; 211 break; 212 case TIM_CNT: 213 timer_val = value; 214 break; 215 case TIM_ARR: 216 s->tim_arr = value; 217 stm32f2xx_timer_set_alarm(s, now); 218 return; 219 case TIM_CCR1: 220 s->tim_ccr1 = value; 221 return; 222 case TIM_CCR2: 223 s->tim_ccr2 = value; 224 return; 225 case TIM_CCR3: 226 s->tim_ccr3 = value; 227 return; 228 case TIM_CCR4: 229 s->tim_ccr4 = value; 230 return; 231 case TIM_DCR: 232 s->tim_dcr = value; 233 return; 234 case TIM_DMAR: 235 s->tim_dmar = value; 236 return; 237 case TIM_OR: 238 s->tim_or = value; 239 return; 240 default: 241 qemu_log_mask(LOG_GUEST_ERROR, 242 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, offset); 243 return; 244 } 245 246 /* This means that a register write has affected the timer in a way that 247 * requires a refresh of both tick_offset and the alarm. 248 */ 249 s->tick_offset = stm32f2xx_ns_to_ticks(s, now) - timer_val; 250 stm32f2xx_timer_set_alarm(s, now); 251 } 252 253 static const MemoryRegionOps stm32f2xx_timer_ops = { 254 .read = stm32f2xx_timer_read, 255 .write = stm32f2xx_timer_write, 256 .endianness = DEVICE_NATIVE_ENDIAN, 257 }; 258 259 static const VMStateDescription vmstate_stm32f2xx_timer = { 260 .name = TYPE_STM32F2XX_TIMER, 261 .version_id = 1, 262 .minimum_version_id = 1, 263 .fields = (VMStateField[]) { 264 VMSTATE_INT64(tick_offset, STM32F2XXTimerState), 265 VMSTATE_UINT32(tim_cr1, STM32F2XXTimerState), 266 VMSTATE_UINT32(tim_cr2, STM32F2XXTimerState), 267 VMSTATE_UINT32(tim_smcr, STM32F2XXTimerState), 268 VMSTATE_UINT32(tim_dier, STM32F2XXTimerState), 269 VMSTATE_UINT32(tim_sr, STM32F2XXTimerState), 270 VMSTATE_UINT32(tim_egr, STM32F2XXTimerState), 271 VMSTATE_UINT32(tim_ccmr1, STM32F2XXTimerState), 272 VMSTATE_UINT32(tim_ccmr2, STM32F2XXTimerState), 273 VMSTATE_UINT32(tim_ccer, STM32F2XXTimerState), 274 VMSTATE_UINT32(tim_psc, STM32F2XXTimerState), 275 VMSTATE_UINT32(tim_arr, STM32F2XXTimerState), 276 VMSTATE_UINT32(tim_ccr1, STM32F2XXTimerState), 277 VMSTATE_UINT32(tim_ccr2, STM32F2XXTimerState), 278 VMSTATE_UINT32(tim_ccr3, STM32F2XXTimerState), 279 VMSTATE_UINT32(tim_ccr4, STM32F2XXTimerState), 280 VMSTATE_UINT32(tim_dcr, STM32F2XXTimerState), 281 VMSTATE_UINT32(tim_dmar, STM32F2XXTimerState), 282 VMSTATE_UINT32(tim_or, STM32F2XXTimerState), 283 VMSTATE_END_OF_LIST() 284 } 285 }; 286 287 static Property stm32f2xx_timer_properties[] = { 288 DEFINE_PROP_UINT64("clock-frequency", struct STM32F2XXTimerState, 289 freq_hz, 1000000000), 290 DEFINE_PROP_END_OF_LIST(), 291 }; 292 293 static void stm32f2xx_timer_init(Object *obj) 294 { 295 STM32F2XXTimerState *s = STM32F2XXTIMER(obj); 296 297 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); 298 299 memory_region_init_io(&s->iomem, obj, &stm32f2xx_timer_ops, s, 300 "stm32f2xx_timer", 0x4000); 301 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); 302 303 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, stm32f2xx_timer_interrupt, s); 304 } 305 306 static void stm32f2xx_timer_class_init(ObjectClass *klass, void *data) 307 { 308 DeviceClass *dc = DEVICE_CLASS(klass); 309 310 dc->reset = stm32f2xx_timer_reset; 311 dc->props = stm32f2xx_timer_properties; 312 dc->vmsd = &vmstate_stm32f2xx_timer; 313 } 314 315 static const TypeInfo stm32f2xx_timer_info = { 316 .name = TYPE_STM32F2XX_TIMER, 317 .parent = TYPE_SYS_BUS_DEVICE, 318 .instance_size = sizeof(STM32F2XXTimerState), 319 .instance_init = stm32f2xx_timer_init, 320 .class_init = stm32f2xx_timer_class_init, 321 }; 322 323 static void stm32f2xx_timer_register_types(void) 324 { 325 type_register_static(&stm32f2xx_timer_info); 326 } 327 328 type_init(stm32f2xx_timer_register_types) 329