1 /* 2 * STM32F2XX Timer 3 * 4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/irq.h" 27 #include "hw/timer/stm32f2xx_timer.h" 28 #include "qemu/log.h" 29 #include "qemu/module.h" 30 31 #ifndef STM_TIMER_ERR_DEBUG 32 #define STM_TIMER_ERR_DEBUG 0 33 #endif 34 35 #define DB_PRINT_L(lvl, fmt, args...) do { \ 36 if (STM_TIMER_ERR_DEBUG >= lvl) { \ 37 qemu_log("%s: " fmt, __func__, ## args); \ 38 } \ 39 } while (0) 40 41 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) 42 43 static void stm32f2xx_timer_set_alarm(STM32F2XXTimerState *s, int64_t now); 44 45 static void stm32f2xx_timer_interrupt(void *opaque) 46 { 47 STM32F2XXTimerState *s = opaque; 48 49 DB_PRINT("Interrupt\n"); 50 51 if (s->tim_dier & TIM_DIER_UIE && s->tim_cr1 & TIM_CR1_CEN) { 52 s->tim_sr |= 1; 53 qemu_irq_pulse(s->irq); 54 stm32f2xx_timer_set_alarm(s, s->hit_time); 55 } 56 57 if (s->tim_ccmr1 & (TIM_CCMR1_OC2M2 | TIM_CCMR1_OC2M1) && 58 !(s->tim_ccmr1 & TIM_CCMR1_OC2M0) && 59 s->tim_ccmr1 & TIM_CCMR1_OC2PE && 60 s->tim_ccer & TIM_CCER_CC2E) { 61 /* PWM 2 - Mode 1 */ 62 DB_PRINT("PWM2 Duty Cycle: %d%%\n", 63 s->tim_ccr2 / (100 * (s->tim_psc + 1))); 64 } 65 } 66 67 static inline int64_t stm32f2xx_ns_to_ticks(STM32F2XXTimerState *s, int64_t t) 68 { 69 return muldiv64(t, s->freq_hz, 1000000000ULL) / (s->tim_psc + 1); 70 } 71 72 static void stm32f2xx_timer_set_alarm(STM32F2XXTimerState *s, int64_t now) 73 { 74 uint64_t ticks; 75 int64_t now_ticks; 76 77 if (s->tim_arr == 0) { 78 return; 79 } 80 81 DB_PRINT("Alarm set at: 0x%x\n", s->tim_cr1); 82 83 now_ticks = stm32f2xx_ns_to_ticks(s, now); 84 ticks = s->tim_arr - (now_ticks - s->tick_offset); 85 86 DB_PRINT("Alarm set in %d ticks\n", (int) ticks); 87 88 s->hit_time = muldiv64((ticks + (uint64_t) now_ticks) * (s->tim_psc + 1), 89 1000000000ULL, s->freq_hz); 90 91 timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->hit_time); 92 DB_PRINT("Wait Time: %" PRId64 " ticks\n", s->hit_time); 93 } 94 95 static void stm32f2xx_timer_reset(DeviceState *dev) 96 { 97 STM32F2XXTimerState *s = STM32F2XXTIMER(dev); 98 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 99 100 s->tim_cr1 = 0; 101 s->tim_cr2 = 0; 102 s->tim_smcr = 0; 103 s->tim_dier = 0; 104 s->tim_sr = 0; 105 s->tim_egr = 0; 106 s->tim_ccmr1 = 0; 107 s->tim_ccmr2 = 0; 108 s->tim_ccer = 0; 109 s->tim_psc = 0; 110 s->tim_arr = 0; 111 s->tim_ccr1 = 0; 112 s->tim_ccr2 = 0; 113 s->tim_ccr3 = 0; 114 s->tim_ccr4 = 0; 115 s->tim_dcr = 0; 116 s->tim_dmar = 0; 117 s->tim_or = 0; 118 119 s->tick_offset = stm32f2xx_ns_to_ticks(s, now); 120 } 121 122 static uint64_t stm32f2xx_timer_read(void *opaque, hwaddr offset, 123 unsigned size) 124 { 125 STM32F2XXTimerState *s = opaque; 126 127 DB_PRINT("Read 0x%"HWADDR_PRIx"\n", offset); 128 129 switch (offset) { 130 case TIM_CR1: 131 return s->tim_cr1; 132 case TIM_CR2: 133 return s->tim_cr2; 134 case TIM_SMCR: 135 return s->tim_smcr; 136 case TIM_DIER: 137 return s->tim_dier; 138 case TIM_SR: 139 return s->tim_sr; 140 case TIM_EGR: 141 return s->tim_egr; 142 case TIM_CCMR1: 143 return s->tim_ccmr1; 144 case TIM_CCMR2: 145 return s->tim_ccmr2; 146 case TIM_CCER: 147 return s->tim_ccer; 148 case TIM_CNT: 149 return stm32f2xx_ns_to_ticks(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) - 150 s->tick_offset; 151 case TIM_PSC: 152 return s->tim_psc; 153 case TIM_ARR: 154 return s->tim_arr; 155 case TIM_CCR1: 156 return s->tim_ccr1; 157 case TIM_CCR2: 158 return s->tim_ccr2; 159 case TIM_CCR3: 160 return s->tim_ccr3; 161 case TIM_CCR4: 162 return s->tim_ccr4; 163 case TIM_DCR: 164 return s->tim_dcr; 165 case TIM_DMAR: 166 return s->tim_dmar; 167 case TIM_OR: 168 return s->tim_or; 169 default: 170 qemu_log_mask(LOG_GUEST_ERROR, 171 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, offset); 172 } 173 174 return 0; 175 } 176 177 static void stm32f2xx_timer_write(void *opaque, hwaddr offset, 178 uint64_t val64, unsigned size) 179 { 180 STM32F2XXTimerState *s = opaque; 181 uint32_t value = val64; 182 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 183 uint32_t timer_val = 0; 184 185 DB_PRINT("Write 0x%x, 0x%"HWADDR_PRIx"\n", value, offset); 186 187 switch (offset) { 188 case TIM_CR1: 189 s->tim_cr1 = value; 190 return; 191 case TIM_CR2: 192 s->tim_cr2 = value; 193 return; 194 case TIM_SMCR: 195 s->tim_smcr = value; 196 return; 197 case TIM_DIER: 198 s->tim_dier = value; 199 return; 200 case TIM_SR: 201 /* This is set by hardware and cleared by software */ 202 s->tim_sr &= value; 203 return; 204 case TIM_EGR: 205 s->tim_egr = value; 206 if (s->tim_egr & TIM_EGR_UG) { 207 timer_val = 0; 208 break; 209 } 210 return; 211 case TIM_CCMR1: 212 s->tim_ccmr1 = value; 213 return; 214 case TIM_CCMR2: 215 s->tim_ccmr2 = value; 216 return; 217 case TIM_CCER: 218 s->tim_ccer = value; 219 return; 220 case TIM_PSC: 221 timer_val = stm32f2xx_ns_to_ticks(s, now) - s->tick_offset; 222 s->tim_psc = value & 0xFFFF; 223 value = timer_val; 224 break; 225 case TIM_CNT: 226 timer_val = value; 227 break; 228 case TIM_ARR: 229 s->tim_arr = value; 230 stm32f2xx_timer_set_alarm(s, now); 231 return; 232 case TIM_CCR1: 233 s->tim_ccr1 = value; 234 return; 235 case TIM_CCR2: 236 s->tim_ccr2 = value; 237 return; 238 case TIM_CCR3: 239 s->tim_ccr3 = value; 240 return; 241 case TIM_CCR4: 242 s->tim_ccr4 = value; 243 return; 244 case TIM_DCR: 245 s->tim_dcr = value; 246 return; 247 case TIM_DMAR: 248 s->tim_dmar = value; 249 return; 250 case TIM_OR: 251 s->tim_or = value; 252 return; 253 default: 254 qemu_log_mask(LOG_GUEST_ERROR, 255 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, offset); 256 return; 257 } 258 259 /* This means that a register write has affected the timer in a way that 260 * requires a refresh of both tick_offset and the alarm. 261 */ 262 s->tick_offset = stm32f2xx_ns_to_ticks(s, now) - timer_val; 263 stm32f2xx_timer_set_alarm(s, now); 264 } 265 266 static const MemoryRegionOps stm32f2xx_timer_ops = { 267 .read = stm32f2xx_timer_read, 268 .write = stm32f2xx_timer_write, 269 .endianness = DEVICE_NATIVE_ENDIAN, 270 }; 271 272 static const VMStateDescription vmstate_stm32f2xx_timer = { 273 .name = TYPE_STM32F2XX_TIMER, 274 .version_id = 1, 275 .minimum_version_id = 1, 276 .fields = (VMStateField[]) { 277 VMSTATE_INT64(tick_offset, STM32F2XXTimerState), 278 VMSTATE_UINT32(tim_cr1, STM32F2XXTimerState), 279 VMSTATE_UINT32(tim_cr2, STM32F2XXTimerState), 280 VMSTATE_UINT32(tim_smcr, STM32F2XXTimerState), 281 VMSTATE_UINT32(tim_dier, STM32F2XXTimerState), 282 VMSTATE_UINT32(tim_sr, STM32F2XXTimerState), 283 VMSTATE_UINT32(tim_egr, STM32F2XXTimerState), 284 VMSTATE_UINT32(tim_ccmr1, STM32F2XXTimerState), 285 VMSTATE_UINT32(tim_ccmr2, STM32F2XXTimerState), 286 VMSTATE_UINT32(tim_ccer, STM32F2XXTimerState), 287 VMSTATE_UINT32(tim_psc, STM32F2XXTimerState), 288 VMSTATE_UINT32(tim_arr, STM32F2XXTimerState), 289 VMSTATE_UINT32(tim_ccr1, STM32F2XXTimerState), 290 VMSTATE_UINT32(tim_ccr2, STM32F2XXTimerState), 291 VMSTATE_UINT32(tim_ccr3, STM32F2XXTimerState), 292 VMSTATE_UINT32(tim_ccr4, STM32F2XXTimerState), 293 VMSTATE_UINT32(tim_dcr, STM32F2XXTimerState), 294 VMSTATE_UINT32(tim_dmar, STM32F2XXTimerState), 295 VMSTATE_UINT32(tim_or, STM32F2XXTimerState), 296 VMSTATE_END_OF_LIST() 297 } 298 }; 299 300 static Property stm32f2xx_timer_properties[] = { 301 DEFINE_PROP_UINT64("clock-frequency", struct STM32F2XXTimerState, 302 freq_hz, 1000000000), 303 DEFINE_PROP_END_OF_LIST(), 304 }; 305 306 static void stm32f2xx_timer_init(Object *obj) 307 { 308 STM32F2XXTimerState *s = STM32F2XXTIMER(obj); 309 310 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); 311 312 memory_region_init_io(&s->iomem, obj, &stm32f2xx_timer_ops, s, 313 "stm32f2xx_timer", 0x400); 314 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); 315 316 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, stm32f2xx_timer_interrupt, s); 317 } 318 319 static void stm32f2xx_timer_class_init(ObjectClass *klass, void *data) 320 { 321 DeviceClass *dc = DEVICE_CLASS(klass); 322 323 dc->reset = stm32f2xx_timer_reset; 324 dc->props = stm32f2xx_timer_properties; 325 dc->vmsd = &vmstate_stm32f2xx_timer; 326 } 327 328 static const TypeInfo stm32f2xx_timer_info = { 329 .name = TYPE_STM32F2XX_TIMER, 330 .parent = TYPE_SYS_BUS_DEVICE, 331 .instance_size = sizeof(STM32F2XXTimerState), 332 .instance_init = stm32f2xx_timer_init, 333 .class_init = stm32f2xx_timer_class_init, 334 }; 335 336 static void stm32f2xx_timer_register_types(void) 337 { 338 type_register_static(&stm32f2xx_timer_info); 339 } 340 341 type_init(stm32f2xx_timer_register_types) 342