1be284705SAlistair Francis /* 2be284705SAlistair Francis * STM32F2XX Timer 3be284705SAlistair Francis * 4be284705SAlistair Francis * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> 5be284705SAlistair Francis * 6be284705SAlistair Francis * Permission is hereby granted, free of charge, to any person obtaining a copy 7be284705SAlistair Francis * of this software and associated documentation files (the "Software"), to deal 8be284705SAlistair Francis * in the Software without restriction, including without limitation the rights 9be284705SAlistair Francis * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10be284705SAlistair Francis * copies of the Software, and to permit persons to whom the Software is 11be284705SAlistair Francis * furnished to do so, subject to the following conditions: 12be284705SAlistair Francis * 13be284705SAlistair Francis * The above copyright notice and this permission notice shall be included in 14be284705SAlistair Francis * all copies or substantial portions of the Software. 15be284705SAlistair Francis * 16be284705SAlistair Francis * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17be284705SAlistair Francis * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18be284705SAlistair Francis * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19be284705SAlistair Francis * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20be284705SAlistair Francis * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21be284705SAlistair Francis * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22be284705SAlistair Francis * THE SOFTWARE. 23be284705SAlistair Francis */ 24be284705SAlistair Francis 25282bc81eSPeter Maydell #include "qemu/osdep.h" 26be284705SAlistair Francis #include "hw/timer/stm32f2xx_timer.h" 2703dd024fSPaolo Bonzini #include "qemu/log.h" 28be284705SAlistair Francis 29be284705SAlistair Francis #ifndef STM_TIMER_ERR_DEBUG 30be284705SAlistair Francis #define STM_TIMER_ERR_DEBUG 0 31be284705SAlistair Francis #endif 32be284705SAlistair Francis 33be284705SAlistair Francis #define DB_PRINT_L(lvl, fmt, args...) do { \ 34be284705SAlistair Francis if (STM_TIMER_ERR_DEBUG >= lvl) { \ 35be284705SAlistair Francis qemu_log("%s: " fmt, __func__, ## args); \ 36be284705SAlistair Francis } \ 37*2562755eSEric Blake } while (0) 38be284705SAlistair Francis 39be284705SAlistair Francis #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) 40be284705SAlistair Francis 41be284705SAlistair Francis static void stm32f2xx_timer_set_alarm(STM32F2XXTimerState *s, int64_t now); 42be284705SAlistair Francis 43be284705SAlistair Francis static void stm32f2xx_timer_interrupt(void *opaque) 44be284705SAlistair Francis { 45be284705SAlistair Francis STM32F2XXTimerState *s = opaque; 46be284705SAlistair Francis 47be284705SAlistair Francis DB_PRINT("Interrupt\n"); 48be284705SAlistair Francis 49be284705SAlistair Francis if (s->tim_dier & TIM_DIER_UIE && s->tim_cr1 & TIM_CR1_CEN) { 50be284705SAlistair Francis s->tim_sr |= 1; 51be284705SAlistair Francis qemu_irq_pulse(s->irq); 52be284705SAlistair Francis stm32f2xx_timer_set_alarm(s, s->hit_time); 53be284705SAlistair Francis } 54cbcb93e8SAlistair Francis 55cbcb93e8SAlistair Francis if (s->tim_ccmr1 & (TIM_CCMR1_OC2M2 | TIM_CCMR1_OC2M1) && 56cbcb93e8SAlistair Francis !(s->tim_ccmr1 & TIM_CCMR1_OC2M0) && 57cbcb93e8SAlistair Francis s->tim_ccmr1 & TIM_CCMR1_OC2PE && 58cbcb93e8SAlistair Francis s->tim_ccer & TIM_CCER_CC2E) { 59cbcb93e8SAlistair Francis /* PWM 2 - Mode 1 */ 60cbcb93e8SAlistair Francis DB_PRINT("PWM2 Duty Cycle: %d%%\n", 61cbcb93e8SAlistair Francis s->tim_ccr2 / (100 * (s->tim_psc + 1))); 62cbcb93e8SAlistair Francis } 63be284705SAlistair Francis } 64be284705SAlistair Francis 65be284705SAlistair Francis static inline int64_t stm32f2xx_ns_to_ticks(STM32F2XXTimerState *s, int64_t t) 66be284705SAlistair Francis { 67be284705SAlistair Francis return muldiv64(t, s->freq_hz, 1000000000ULL) / (s->tim_psc + 1); 68be284705SAlistair Francis } 69be284705SAlistair Francis 70be284705SAlistair Francis static void stm32f2xx_timer_set_alarm(STM32F2XXTimerState *s, int64_t now) 71be284705SAlistair Francis { 72be284705SAlistair Francis uint64_t ticks; 73be284705SAlistair Francis int64_t now_ticks; 74be284705SAlistair Francis 75be284705SAlistair Francis if (s->tim_arr == 0) { 76be284705SAlistair Francis return; 77be284705SAlistair Francis } 78be284705SAlistair Francis 79be284705SAlistair Francis DB_PRINT("Alarm set at: 0x%x\n", s->tim_cr1); 80be284705SAlistair Francis 81be284705SAlistair Francis now_ticks = stm32f2xx_ns_to_ticks(s, now); 82be284705SAlistair Francis ticks = s->tim_arr - (now_ticks - s->tick_offset); 83be284705SAlistair Francis 84be284705SAlistair Francis DB_PRINT("Alarm set in %d ticks\n", (int) ticks); 85be284705SAlistair Francis 86be284705SAlistair Francis s->hit_time = muldiv64((ticks + (uint64_t) now_ticks) * (s->tim_psc + 1), 87be284705SAlistair Francis 1000000000ULL, s->freq_hz); 88be284705SAlistair Francis 89be284705SAlistair Francis timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->hit_time); 90be284705SAlistair Francis DB_PRINT("Wait Time: %" PRId64 " ticks\n", s->hit_time); 91be284705SAlistair Francis } 92be284705SAlistair Francis 93be284705SAlistair Francis static void stm32f2xx_timer_reset(DeviceState *dev) 94be284705SAlistair Francis { 95be284705SAlistair Francis STM32F2XXTimerState *s = STM32F2XXTIMER(dev); 96be284705SAlistair Francis int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 97be284705SAlistair Francis 98be284705SAlistair Francis s->tim_cr1 = 0; 99be284705SAlistair Francis s->tim_cr2 = 0; 100be284705SAlistair Francis s->tim_smcr = 0; 101be284705SAlistair Francis s->tim_dier = 0; 102be284705SAlistair Francis s->tim_sr = 0; 103be284705SAlistair Francis s->tim_egr = 0; 104be284705SAlistair Francis s->tim_ccmr1 = 0; 105be284705SAlistair Francis s->tim_ccmr2 = 0; 106be284705SAlistair Francis s->tim_ccer = 0; 107be284705SAlistair Francis s->tim_psc = 0; 108be284705SAlistair Francis s->tim_arr = 0; 109be284705SAlistair Francis s->tim_ccr1 = 0; 110be284705SAlistair Francis s->tim_ccr2 = 0; 111be284705SAlistair Francis s->tim_ccr3 = 0; 112be284705SAlistair Francis s->tim_ccr4 = 0; 113be284705SAlistair Francis s->tim_dcr = 0; 114be284705SAlistair Francis s->tim_dmar = 0; 115be284705SAlistair Francis s->tim_or = 0; 116be284705SAlistair Francis 117be284705SAlistair Francis s->tick_offset = stm32f2xx_ns_to_ticks(s, now); 118be284705SAlistair Francis } 119be284705SAlistair Francis 120be284705SAlistair Francis static uint64_t stm32f2xx_timer_read(void *opaque, hwaddr offset, 121be284705SAlistair Francis unsigned size) 122be284705SAlistair Francis { 123be284705SAlistair Francis STM32F2XXTimerState *s = opaque; 124be284705SAlistair Francis 125be284705SAlistair Francis DB_PRINT("Read 0x%"HWADDR_PRIx"\n", offset); 126be284705SAlistair Francis 127be284705SAlistair Francis switch (offset) { 128be284705SAlistair Francis case TIM_CR1: 129be284705SAlistair Francis return s->tim_cr1; 130be284705SAlistair Francis case TIM_CR2: 131be284705SAlistair Francis return s->tim_cr2; 132be284705SAlistair Francis case TIM_SMCR: 133be284705SAlistair Francis return s->tim_smcr; 134be284705SAlistair Francis case TIM_DIER: 135be284705SAlistair Francis return s->tim_dier; 136be284705SAlistair Francis case TIM_SR: 137be284705SAlistair Francis return s->tim_sr; 138be284705SAlistair Francis case TIM_EGR: 139be284705SAlistair Francis return s->tim_egr; 140be284705SAlistair Francis case TIM_CCMR1: 141be284705SAlistair Francis return s->tim_ccmr1; 142be284705SAlistair Francis case TIM_CCMR2: 143be284705SAlistair Francis return s->tim_ccmr2; 144be284705SAlistair Francis case TIM_CCER: 145be284705SAlistair Francis return s->tim_ccer; 146be284705SAlistair Francis case TIM_CNT: 147be284705SAlistair Francis return stm32f2xx_ns_to_ticks(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) - 148be284705SAlistair Francis s->tick_offset; 149be284705SAlistair Francis case TIM_PSC: 150be284705SAlistair Francis return s->tim_psc; 151be284705SAlistair Francis case TIM_ARR: 152be284705SAlistair Francis return s->tim_arr; 153be284705SAlistair Francis case TIM_CCR1: 154be284705SAlistair Francis return s->tim_ccr1; 155be284705SAlistair Francis case TIM_CCR2: 156be284705SAlistair Francis return s->tim_ccr2; 157be284705SAlistair Francis case TIM_CCR3: 158be284705SAlistair Francis return s->tim_ccr3; 159be284705SAlistair Francis case TIM_CCR4: 160be284705SAlistair Francis return s->tim_ccr4; 161be284705SAlistair Francis case TIM_DCR: 162be284705SAlistair Francis return s->tim_dcr; 163be284705SAlistair Francis case TIM_DMAR: 164be284705SAlistair Francis return s->tim_dmar; 165be284705SAlistair Francis case TIM_OR: 166be284705SAlistair Francis return s->tim_or; 167be284705SAlistair Francis default: 168be284705SAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, 169be284705SAlistair Francis "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, offset); 170be284705SAlistair Francis } 171be284705SAlistair Francis 172be284705SAlistair Francis return 0; 173be284705SAlistair Francis } 174be284705SAlistair Francis 175be284705SAlistair Francis static void stm32f2xx_timer_write(void *opaque, hwaddr offset, 176be284705SAlistair Francis uint64_t val64, unsigned size) 177be284705SAlistair Francis { 178be284705SAlistair Francis STM32F2XXTimerState *s = opaque; 179be284705SAlistair Francis uint32_t value = val64; 180be284705SAlistair Francis int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 181be284705SAlistair Francis uint32_t timer_val = 0; 182be284705SAlistair Francis 183be284705SAlistair Francis DB_PRINT("Write 0x%x, 0x%"HWADDR_PRIx"\n", value, offset); 184be284705SAlistair Francis 185be284705SAlistair Francis switch (offset) { 186be284705SAlistair Francis case TIM_CR1: 187be284705SAlistair Francis s->tim_cr1 = value; 188be284705SAlistair Francis return; 189be284705SAlistair Francis case TIM_CR2: 190be284705SAlistair Francis s->tim_cr2 = value; 191be284705SAlistair Francis return; 192be284705SAlistair Francis case TIM_SMCR: 193be284705SAlistair Francis s->tim_smcr = value; 194be284705SAlistair Francis return; 195be284705SAlistair Francis case TIM_DIER: 196be284705SAlistair Francis s->tim_dier = value; 197be284705SAlistair Francis return; 198be284705SAlistair Francis case TIM_SR: 199be284705SAlistair Francis /* This is set by hardware and cleared by software */ 200be284705SAlistair Francis s->tim_sr &= value; 201be284705SAlistair Francis return; 202be284705SAlistair Francis case TIM_EGR: 203be284705SAlistair Francis s->tim_egr = value; 204be284705SAlistair Francis if (s->tim_egr & TIM_EGR_UG) { 205be284705SAlistair Francis timer_val = 0; 206be284705SAlistair Francis break; 207be284705SAlistair Francis } 208be284705SAlistair Francis return; 209be284705SAlistair Francis case TIM_CCMR1: 210be284705SAlistair Francis s->tim_ccmr1 = value; 211be284705SAlistair Francis return; 212be284705SAlistair Francis case TIM_CCMR2: 213be284705SAlistair Francis s->tim_ccmr2 = value; 214be284705SAlistair Francis return; 215be284705SAlistair Francis case TIM_CCER: 216be284705SAlistair Francis s->tim_ccer = value; 217be284705SAlistair Francis return; 218be284705SAlistair Francis case TIM_PSC: 219be284705SAlistair Francis timer_val = stm32f2xx_ns_to_ticks(s, now) - s->tick_offset; 22084da1516SPrasad J Pandit s->tim_psc = value & 0xFFFF; 221be284705SAlistair Francis value = timer_val; 222be284705SAlistair Francis break; 223be284705SAlistair Francis case TIM_CNT: 224be284705SAlistair Francis timer_val = value; 225be284705SAlistair Francis break; 226be284705SAlistair Francis case TIM_ARR: 227be284705SAlistair Francis s->tim_arr = value; 228be284705SAlistair Francis stm32f2xx_timer_set_alarm(s, now); 229be284705SAlistair Francis return; 230be284705SAlistair Francis case TIM_CCR1: 231be284705SAlistair Francis s->tim_ccr1 = value; 232be284705SAlistair Francis return; 233be284705SAlistair Francis case TIM_CCR2: 234be284705SAlistair Francis s->tim_ccr2 = value; 235be284705SAlistair Francis return; 236be284705SAlistair Francis case TIM_CCR3: 237be284705SAlistair Francis s->tim_ccr3 = value; 238be284705SAlistair Francis return; 239be284705SAlistair Francis case TIM_CCR4: 240be284705SAlistair Francis s->tim_ccr4 = value; 241be284705SAlistair Francis return; 242be284705SAlistair Francis case TIM_DCR: 243be284705SAlistair Francis s->tim_dcr = value; 244be284705SAlistair Francis return; 245be284705SAlistair Francis case TIM_DMAR: 246be284705SAlistair Francis s->tim_dmar = value; 247be284705SAlistair Francis return; 248be284705SAlistair Francis case TIM_OR: 249be284705SAlistair Francis s->tim_or = value; 250be284705SAlistair Francis return; 251be284705SAlistair Francis default: 252be284705SAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, 253be284705SAlistair Francis "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, offset); 254be284705SAlistair Francis return; 255be284705SAlistair Francis } 256be284705SAlistair Francis 257be284705SAlistair Francis /* This means that a register write has affected the timer in a way that 258be284705SAlistair Francis * requires a refresh of both tick_offset and the alarm. 259be284705SAlistair Francis */ 260be284705SAlistair Francis s->tick_offset = stm32f2xx_ns_to_ticks(s, now) - timer_val; 261be284705SAlistair Francis stm32f2xx_timer_set_alarm(s, now); 262be284705SAlistair Francis } 263be284705SAlistair Francis 264be284705SAlistair Francis static const MemoryRegionOps stm32f2xx_timer_ops = { 265be284705SAlistair Francis .read = stm32f2xx_timer_read, 266be284705SAlistair Francis .write = stm32f2xx_timer_write, 267be284705SAlistair Francis .endianness = DEVICE_NATIVE_ENDIAN, 268be284705SAlistair Francis }; 269be284705SAlistair Francis 270be284705SAlistair Francis static const VMStateDescription vmstate_stm32f2xx_timer = { 271be284705SAlistair Francis .name = TYPE_STM32F2XX_TIMER, 272be284705SAlistair Francis .version_id = 1, 273be284705SAlistair Francis .minimum_version_id = 1, 274be284705SAlistair Francis .fields = (VMStateField[]) { 275be284705SAlistair Francis VMSTATE_INT64(tick_offset, STM32F2XXTimerState), 276be284705SAlistair Francis VMSTATE_UINT32(tim_cr1, STM32F2XXTimerState), 277be284705SAlistair Francis VMSTATE_UINT32(tim_cr2, STM32F2XXTimerState), 278be284705SAlistair Francis VMSTATE_UINT32(tim_smcr, STM32F2XXTimerState), 279be284705SAlistair Francis VMSTATE_UINT32(tim_dier, STM32F2XXTimerState), 280be284705SAlistair Francis VMSTATE_UINT32(tim_sr, STM32F2XXTimerState), 281be284705SAlistair Francis VMSTATE_UINT32(tim_egr, STM32F2XXTimerState), 282be284705SAlistair Francis VMSTATE_UINT32(tim_ccmr1, STM32F2XXTimerState), 283be284705SAlistair Francis VMSTATE_UINT32(tim_ccmr2, STM32F2XXTimerState), 284be284705SAlistair Francis VMSTATE_UINT32(tim_ccer, STM32F2XXTimerState), 285be284705SAlistair Francis VMSTATE_UINT32(tim_psc, STM32F2XXTimerState), 286be284705SAlistair Francis VMSTATE_UINT32(tim_arr, STM32F2XXTimerState), 287be284705SAlistair Francis VMSTATE_UINT32(tim_ccr1, STM32F2XXTimerState), 288be284705SAlistair Francis VMSTATE_UINT32(tim_ccr2, STM32F2XXTimerState), 289be284705SAlistair Francis VMSTATE_UINT32(tim_ccr3, STM32F2XXTimerState), 290be284705SAlistair Francis VMSTATE_UINT32(tim_ccr4, STM32F2XXTimerState), 291be284705SAlistair Francis VMSTATE_UINT32(tim_dcr, STM32F2XXTimerState), 292be284705SAlistair Francis VMSTATE_UINT32(tim_dmar, STM32F2XXTimerState), 293be284705SAlistair Francis VMSTATE_UINT32(tim_or, STM32F2XXTimerState), 294be284705SAlistair Francis VMSTATE_END_OF_LIST() 295be284705SAlistair Francis } 296be284705SAlistair Francis }; 297be284705SAlistair Francis 298be284705SAlistair Francis static Property stm32f2xx_timer_properties[] = { 299be284705SAlistair Francis DEFINE_PROP_UINT64("clock-frequency", struct STM32F2XXTimerState, 300be284705SAlistair Francis freq_hz, 1000000000), 301be284705SAlistair Francis DEFINE_PROP_END_OF_LIST(), 302be284705SAlistair Francis }; 303be284705SAlistair Francis 304be284705SAlistair Francis static void stm32f2xx_timer_init(Object *obj) 305be284705SAlistair Francis { 306be284705SAlistair Francis STM32F2XXTimerState *s = STM32F2XXTIMER(obj); 307be284705SAlistair Francis 308be284705SAlistair Francis sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); 309be284705SAlistair Francis 310be284705SAlistair Francis memory_region_init_io(&s->iomem, obj, &stm32f2xx_timer_ops, s, 311be284705SAlistair Francis "stm32f2xx_timer", 0x4000); 312be284705SAlistair Francis sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); 313be284705SAlistair Francis 314be284705SAlistair Francis s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, stm32f2xx_timer_interrupt, s); 315be284705SAlistair Francis } 316be284705SAlistair Francis 317be284705SAlistair Francis static void stm32f2xx_timer_class_init(ObjectClass *klass, void *data) 318be284705SAlistair Francis { 319be284705SAlistair Francis DeviceClass *dc = DEVICE_CLASS(klass); 320be284705SAlistair Francis 321be284705SAlistair Francis dc->reset = stm32f2xx_timer_reset; 322be284705SAlistair Francis dc->props = stm32f2xx_timer_properties; 323be284705SAlistair Francis dc->vmsd = &vmstate_stm32f2xx_timer; 324be284705SAlistair Francis } 325be284705SAlistair Francis 326be284705SAlistair Francis static const TypeInfo stm32f2xx_timer_info = { 327be284705SAlistair Francis .name = TYPE_STM32F2XX_TIMER, 328be284705SAlistair Francis .parent = TYPE_SYS_BUS_DEVICE, 329be284705SAlistair Francis .instance_size = sizeof(STM32F2XXTimerState), 330be284705SAlistair Francis .instance_init = stm32f2xx_timer_init, 331be284705SAlistair Francis .class_init = stm32f2xx_timer_class_init, 332be284705SAlistair Francis }; 333be284705SAlistair Francis 334be284705SAlistair Francis static void stm32f2xx_timer_register_types(void) 335be284705SAlistair Francis { 336be284705SAlistair Francis type_register_static(&stm32f2xx_timer_info); 337be284705SAlistair Francis } 338be284705SAlistair Francis 339be284705SAlistair Francis type_init(stm32f2xx_timer_register_types) 340