1be284705SAlistair Francis /* 2be284705SAlistair Francis * STM32F2XX Timer 3be284705SAlistair Francis * 4be284705SAlistair Francis * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> 5be284705SAlistair Francis * 6be284705SAlistair Francis * Permission is hereby granted, free of charge, to any person obtaining a copy 7be284705SAlistair Francis * of this software and associated documentation files (the "Software"), to deal 8be284705SAlistair Francis * in the Software without restriction, including without limitation the rights 9be284705SAlistair Francis * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10be284705SAlistair Francis * copies of the Software, and to permit persons to whom the Software is 11be284705SAlistair Francis * furnished to do so, subject to the following conditions: 12be284705SAlistair Francis * 13be284705SAlistair Francis * The above copyright notice and this permission notice shall be included in 14be284705SAlistair Francis * all copies or substantial portions of the Software. 15be284705SAlistair Francis * 16be284705SAlistair Francis * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17be284705SAlistair Francis * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18be284705SAlistair Francis * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19be284705SAlistair Francis * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20be284705SAlistair Francis * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21be284705SAlistair Francis * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22be284705SAlistair Francis * THE SOFTWARE. 23be284705SAlistair Francis */ 24be284705SAlistair Francis 25282bc81eSPeter Maydell #include "qemu/osdep.h" 26be284705SAlistair Francis #include "hw/timer/stm32f2xx_timer.h" 2703dd024fSPaolo Bonzini #include "qemu/log.h" 28*0b8fa32fSMarkus Armbruster #include "qemu/module.h" 29be284705SAlistair Francis 30be284705SAlistair Francis #ifndef STM_TIMER_ERR_DEBUG 31be284705SAlistair Francis #define STM_TIMER_ERR_DEBUG 0 32be284705SAlistair Francis #endif 33be284705SAlistair Francis 34be284705SAlistair Francis #define DB_PRINT_L(lvl, fmt, args...) do { \ 35be284705SAlistair Francis if (STM_TIMER_ERR_DEBUG >= lvl) { \ 36be284705SAlistair Francis qemu_log("%s: " fmt, __func__, ## args); \ 37be284705SAlistair Francis } \ 382562755eSEric Blake } while (0) 39be284705SAlistair Francis 40be284705SAlistair Francis #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) 41be284705SAlistair Francis 42be284705SAlistair Francis static void stm32f2xx_timer_set_alarm(STM32F2XXTimerState *s, int64_t now); 43be284705SAlistair Francis 44be284705SAlistair Francis static void stm32f2xx_timer_interrupt(void *opaque) 45be284705SAlistair Francis { 46be284705SAlistair Francis STM32F2XXTimerState *s = opaque; 47be284705SAlistair Francis 48be284705SAlistair Francis DB_PRINT("Interrupt\n"); 49be284705SAlistair Francis 50be284705SAlistair Francis if (s->tim_dier & TIM_DIER_UIE && s->tim_cr1 & TIM_CR1_CEN) { 51be284705SAlistair Francis s->tim_sr |= 1; 52be284705SAlistair Francis qemu_irq_pulse(s->irq); 53be284705SAlistair Francis stm32f2xx_timer_set_alarm(s, s->hit_time); 54be284705SAlistair Francis } 55cbcb93e8SAlistair Francis 56cbcb93e8SAlistair Francis if (s->tim_ccmr1 & (TIM_CCMR1_OC2M2 | TIM_CCMR1_OC2M1) && 57cbcb93e8SAlistair Francis !(s->tim_ccmr1 & TIM_CCMR1_OC2M0) && 58cbcb93e8SAlistair Francis s->tim_ccmr1 & TIM_CCMR1_OC2PE && 59cbcb93e8SAlistair Francis s->tim_ccer & TIM_CCER_CC2E) { 60cbcb93e8SAlistair Francis /* PWM 2 - Mode 1 */ 61cbcb93e8SAlistair Francis DB_PRINT("PWM2 Duty Cycle: %d%%\n", 62cbcb93e8SAlistair Francis s->tim_ccr2 / (100 * (s->tim_psc + 1))); 63cbcb93e8SAlistair Francis } 64be284705SAlistair Francis } 65be284705SAlistair Francis 66be284705SAlistair Francis static inline int64_t stm32f2xx_ns_to_ticks(STM32F2XXTimerState *s, int64_t t) 67be284705SAlistair Francis { 68be284705SAlistair Francis return muldiv64(t, s->freq_hz, 1000000000ULL) / (s->tim_psc + 1); 69be284705SAlistair Francis } 70be284705SAlistair Francis 71be284705SAlistair Francis static void stm32f2xx_timer_set_alarm(STM32F2XXTimerState *s, int64_t now) 72be284705SAlistair Francis { 73be284705SAlistair Francis uint64_t ticks; 74be284705SAlistair Francis int64_t now_ticks; 75be284705SAlistair Francis 76be284705SAlistair Francis if (s->tim_arr == 0) { 77be284705SAlistair Francis return; 78be284705SAlistair Francis } 79be284705SAlistair Francis 80be284705SAlistair Francis DB_PRINT("Alarm set at: 0x%x\n", s->tim_cr1); 81be284705SAlistair Francis 82be284705SAlistair Francis now_ticks = stm32f2xx_ns_to_ticks(s, now); 83be284705SAlistair Francis ticks = s->tim_arr - (now_ticks - s->tick_offset); 84be284705SAlistair Francis 85be284705SAlistair Francis DB_PRINT("Alarm set in %d ticks\n", (int) ticks); 86be284705SAlistair Francis 87be284705SAlistair Francis s->hit_time = muldiv64((ticks + (uint64_t) now_ticks) * (s->tim_psc + 1), 88be284705SAlistair Francis 1000000000ULL, s->freq_hz); 89be284705SAlistair Francis 90be284705SAlistair Francis timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->hit_time); 91be284705SAlistair Francis DB_PRINT("Wait Time: %" PRId64 " ticks\n", s->hit_time); 92be284705SAlistair Francis } 93be284705SAlistair Francis 94be284705SAlistair Francis static void stm32f2xx_timer_reset(DeviceState *dev) 95be284705SAlistair Francis { 96be284705SAlistair Francis STM32F2XXTimerState *s = STM32F2XXTIMER(dev); 97be284705SAlistair Francis int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 98be284705SAlistair Francis 99be284705SAlistair Francis s->tim_cr1 = 0; 100be284705SAlistair Francis s->tim_cr2 = 0; 101be284705SAlistair Francis s->tim_smcr = 0; 102be284705SAlistair Francis s->tim_dier = 0; 103be284705SAlistair Francis s->tim_sr = 0; 104be284705SAlistair Francis s->tim_egr = 0; 105be284705SAlistair Francis s->tim_ccmr1 = 0; 106be284705SAlistair Francis s->tim_ccmr2 = 0; 107be284705SAlistair Francis s->tim_ccer = 0; 108be284705SAlistair Francis s->tim_psc = 0; 109be284705SAlistair Francis s->tim_arr = 0; 110be284705SAlistair Francis s->tim_ccr1 = 0; 111be284705SAlistair Francis s->tim_ccr2 = 0; 112be284705SAlistair Francis s->tim_ccr3 = 0; 113be284705SAlistair Francis s->tim_ccr4 = 0; 114be284705SAlistair Francis s->tim_dcr = 0; 115be284705SAlistair Francis s->tim_dmar = 0; 116be284705SAlistair Francis s->tim_or = 0; 117be284705SAlistair Francis 118be284705SAlistair Francis s->tick_offset = stm32f2xx_ns_to_ticks(s, now); 119be284705SAlistair Francis } 120be284705SAlistair Francis 121be284705SAlistair Francis static uint64_t stm32f2xx_timer_read(void *opaque, hwaddr offset, 122be284705SAlistair Francis unsigned size) 123be284705SAlistair Francis { 124be284705SAlistair Francis STM32F2XXTimerState *s = opaque; 125be284705SAlistair Francis 126be284705SAlistair Francis DB_PRINT("Read 0x%"HWADDR_PRIx"\n", offset); 127be284705SAlistair Francis 128be284705SAlistair Francis switch (offset) { 129be284705SAlistair Francis case TIM_CR1: 130be284705SAlistair Francis return s->tim_cr1; 131be284705SAlistair Francis case TIM_CR2: 132be284705SAlistair Francis return s->tim_cr2; 133be284705SAlistair Francis case TIM_SMCR: 134be284705SAlistair Francis return s->tim_smcr; 135be284705SAlistair Francis case TIM_DIER: 136be284705SAlistair Francis return s->tim_dier; 137be284705SAlistair Francis case TIM_SR: 138be284705SAlistair Francis return s->tim_sr; 139be284705SAlistair Francis case TIM_EGR: 140be284705SAlistair Francis return s->tim_egr; 141be284705SAlistair Francis case TIM_CCMR1: 142be284705SAlistair Francis return s->tim_ccmr1; 143be284705SAlistair Francis case TIM_CCMR2: 144be284705SAlistair Francis return s->tim_ccmr2; 145be284705SAlistair Francis case TIM_CCER: 146be284705SAlistair Francis return s->tim_ccer; 147be284705SAlistair Francis case TIM_CNT: 148be284705SAlistair Francis return stm32f2xx_ns_to_ticks(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) - 149be284705SAlistair Francis s->tick_offset; 150be284705SAlistair Francis case TIM_PSC: 151be284705SAlistair Francis return s->tim_psc; 152be284705SAlistair Francis case TIM_ARR: 153be284705SAlistair Francis return s->tim_arr; 154be284705SAlistair Francis case TIM_CCR1: 155be284705SAlistair Francis return s->tim_ccr1; 156be284705SAlistair Francis case TIM_CCR2: 157be284705SAlistair Francis return s->tim_ccr2; 158be284705SAlistair Francis case TIM_CCR3: 159be284705SAlistair Francis return s->tim_ccr3; 160be284705SAlistair Francis case TIM_CCR4: 161be284705SAlistair Francis return s->tim_ccr4; 162be284705SAlistair Francis case TIM_DCR: 163be284705SAlistair Francis return s->tim_dcr; 164be284705SAlistair Francis case TIM_DMAR: 165be284705SAlistair Francis return s->tim_dmar; 166be284705SAlistair Francis case TIM_OR: 167be284705SAlistair Francis return s->tim_or; 168be284705SAlistair Francis default: 169be284705SAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, 170be284705SAlistair Francis "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, offset); 171be284705SAlistair Francis } 172be284705SAlistair Francis 173be284705SAlistair Francis return 0; 174be284705SAlistair Francis } 175be284705SAlistair Francis 176be284705SAlistair Francis static void stm32f2xx_timer_write(void *opaque, hwaddr offset, 177be284705SAlistair Francis uint64_t val64, unsigned size) 178be284705SAlistair Francis { 179be284705SAlistair Francis STM32F2XXTimerState *s = opaque; 180be284705SAlistair Francis uint32_t value = val64; 181be284705SAlistair Francis int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 182be284705SAlistair Francis uint32_t timer_val = 0; 183be284705SAlistair Francis 184be284705SAlistair Francis DB_PRINT("Write 0x%x, 0x%"HWADDR_PRIx"\n", value, offset); 185be284705SAlistair Francis 186be284705SAlistair Francis switch (offset) { 187be284705SAlistair Francis case TIM_CR1: 188be284705SAlistair Francis s->tim_cr1 = value; 189be284705SAlistair Francis return; 190be284705SAlistair Francis case TIM_CR2: 191be284705SAlistair Francis s->tim_cr2 = value; 192be284705SAlistair Francis return; 193be284705SAlistair Francis case TIM_SMCR: 194be284705SAlistair Francis s->tim_smcr = value; 195be284705SAlistair Francis return; 196be284705SAlistair Francis case TIM_DIER: 197be284705SAlistair Francis s->tim_dier = value; 198be284705SAlistair Francis return; 199be284705SAlistair Francis case TIM_SR: 200be284705SAlistair Francis /* This is set by hardware and cleared by software */ 201be284705SAlistair Francis s->tim_sr &= value; 202be284705SAlistair Francis return; 203be284705SAlistair Francis case TIM_EGR: 204be284705SAlistair Francis s->tim_egr = value; 205be284705SAlistair Francis if (s->tim_egr & TIM_EGR_UG) { 206be284705SAlistair Francis timer_val = 0; 207be284705SAlistair Francis break; 208be284705SAlistair Francis } 209be284705SAlistair Francis return; 210be284705SAlistair Francis case TIM_CCMR1: 211be284705SAlistair Francis s->tim_ccmr1 = value; 212be284705SAlistair Francis return; 213be284705SAlistair Francis case TIM_CCMR2: 214be284705SAlistair Francis s->tim_ccmr2 = value; 215be284705SAlistair Francis return; 216be284705SAlistair Francis case TIM_CCER: 217be284705SAlistair Francis s->tim_ccer = value; 218be284705SAlistair Francis return; 219be284705SAlistair Francis case TIM_PSC: 220be284705SAlistair Francis timer_val = stm32f2xx_ns_to_ticks(s, now) - s->tick_offset; 22184da1516SPrasad J Pandit s->tim_psc = value & 0xFFFF; 222be284705SAlistair Francis value = timer_val; 223be284705SAlistair Francis break; 224be284705SAlistair Francis case TIM_CNT: 225be284705SAlistair Francis timer_val = value; 226be284705SAlistair Francis break; 227be284705SAlistair Francis case TIM_ARR: 228be284705SAlistair Francis s->tim_arr = value; 229be284705SAlistair Francis stm32f2xx_timer_set_alarm(s, now); 230be284705SAlistair Francis return; 231be284705SAlistair Francis case TIM_CCR1: 232be284705SAlistair Francis s->tim_ccr1 = value; 233be284705SAlistair Francis return; 234be284705SAlistair Francis case TIM_CCR2: 235be284705SAlistair Francis s->tim_ccr2 = value; 236be284705SAlistair Francis return; 237be284705SAlistair Francis case TIM_CCR3: 238be284705SAlistair Francis s->tim_ccr3 = value; 239be284705SAlistair Francis return; 240be284705SAlistair Francis case TIM_CCR4: 241be284705SAlistair Francis s->tim_ccr4 = value; 242be284705SAlistair Francis return; 243be284705SAlistair Francis case TIM_DCR: 244be284705SAlistair Francis s->tim_dcr = value; 245be284705SAlistair Francis return; 246be284705SAlistair Francis case TIM_DMAR: 247be284705SAlistair Francis s->tim_dmar = value; 248be284705SAlistair Francis return; 249be284705SAlistair Francis case TIM_OR: 250be284705SAlistair Francis s->tim_or = value; 251be284705SAlistair Francis return; 252be284705SAlistair Francis default: 253be284705SAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, 254be284705SAlistair Francis "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, offset); 255be284705SAlistair Francis return; 256be284705SAlistair Francis } 257be284705SAlistair Francis 258be284705SAlistair Francis /* This means that a register write has affected the timer in a way that 259be284705SAlistair Francis * requires a refresh of both tick_offset and the alarm. 260be284705SAlistair Francis */ 261be284705SAlistair Francis s->tick_offset = stm32f2xx_ns_to_ticks(s, now) - timer_val; 262be284705SAlistair Francis stm32f2xx_timer_set_alarm(s, now); 263be284705SAlistair Francis } 264be284705SAlistair Francis 265be284705SAlistair Francis static const MemoryRegionOps stm32f2xx_timer_ops = { 266be284705SAlistair Francis .read = stm32f2xx_timer_read, 267be284705SAlistair Francis .write = stm32f2xx_timer_write, 268be284705SAlistair Francis .endianness = DEVICE_NATIVE_ENDIAN, 269be284705SAlistair Francis }; 270be284705SAlistair Francis 271be284705SAlistair Francis static const VMStateDescription vmstate_stm32f2xx_timer = { 272be284705SAlistair Francis .name = TYPE_STM32F2XX_TIMER, 273be284705SAlistair Francis .version_id = 1, 274be284705SAlistair Francis .minimum_version_id = 1, 275be284705SAlistair Francis .fields = (VMStateField[]) { 276be284705SAlistair Francis VMSTATE_INT64(tick_offset, STM32F2XXTimerState), 277be284705SAlistair Francis VMSTATE_UINT32(tim_cr1, STM32F2XXTimerState), 278be284705SAlistair Francis VMSTATE_UINT32(tim_cr2, STM32F2XXTimerState), 279be284705SAlistair Francis VMSTATE_UINT32(tim_smcr, STM32F2XXTimerState), 280be284705SAlistair Francis VMSTATE_UINT32(tim_dier, STM32F2XXTimerState), 281be284705SAlistair Francis VMSTATE_UINT32(tim_sr, STM32F2XXTimerState), 282be284705SAlistair Francis VMSTATE_UINT32(tim_egr, STM32F2XXTimerState), 283be284705SAlistair Francis VMSTATE_UINT32(tim_ccmr1, STM32F2XXTimerState), 284be284705SAlistair Francis VMSTATE_UINT32(tim_ccmr2, STM32F2XXTimerState), 285be284705SAlistair Francis VMSTATE_UINT32(tim_ccer, STM32F2XXTimerState), 286be284705SAlistair Francis VMSTATE_UINT32(tim_psc, STM32F2XXTimerState), 287be284705SAlistair Francis VMSTATE_UINT32(tim_arr, STM32F2XXTimerState), 288be284705SAlistair Francis VMSTATE_UINT32(tim_ccr1, STM32F2XXTimerState), 289be284705SAlistair Francis VMSTATE_UINT32(tim_ccr2, STM32F2XXTimerState), 290be284705SAlistair Francis VMSTATE_UINT32(tim_ccr3, STM32F2XXTimerState), 291be284705SAlistair Francis VMSTATE_UINT32(tim_ccr4, STM32F2XXTimerState), 292be284705SAlistair Francis VMSTATE_UINT32(tim_dcr, STM32F2XXTimerState), 293be284705SAlistair Francis VMSTATE_UINT32(tim_dmar, STM32F2XXTimerState), 294be284705SAlistair Francis VMSTATE_UINT32(tim_or, STM32F2XXTimerState), 295be284705SAlistair Francis VMSTATE_END_OF_LIST() 296be284705SAlistair Francis } 297be284705SAlistair Francis }; 298be284705SAlistair Francis 299be284705SAlistair Francis static Property stm32f2xx_timer_properties[] = { 300be284705SAlistair Francis DEFINE_PROP_UINT64("clock-frequency", struct STM32F2XXTimerState, 301be284705SAlistair Francis freq_hz, 1000000000), 302be284705SAlistair Francis DEFINE_PROP_END_OF_LIST(), 303be284705SAlistair Francis }; 304be284705SAlistair Francis 305be284705SAlistair Francis static void stm32f2xx_timer_init(Object *obj) 306be284705SAlistair Francis { 307be284705SAlistair Francis STM32F2XXTimerState *s = STM32F2XXTIMER(obj); 308be284705SAlistair Francis 309be284705SAlistair Francis sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); 310be284705SAlistair Francis 311be284705SAlistair Francis memory_region_init_io(&s->iomem, obj, &stm32f2xx_timer_ops, s, 312dd5d693eSSeth Kintigh "stm32f2xx_timer", 0x400); 313be284705SAlistair Francis sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); 314be284705SAlistair Francis 315be284705SAlistair Francis s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, stm32f2xx_timer_interrupt, s); 316be284705SAlistair Francis } 317be284705SAlistair Francis 318be284705SAlistair Francis static void stm32f2xx_timer_class_init(ObjectClass *klass, void *data) 319be284705SAlistair Francis { 320be284705SAlistair Francis DeviceClass *dc = DEVICE_CLASS(klass); 321be284705SAlistair Francis 322be284705SAlistair Francis dc->reset = stm32f2xx_timer_reset; 323be284705SAlistair Francis dc->props = stm32f2xx_timer_properties; 324be284705SAlistair Francis dc->vmsd = &vmstate_stm32f2xx_timer; 325be284705SAlistair Francis } 326be284705SAlistair Francis 327be284705SAlistair Francis static const TypeInfo stm32f2xx_timer_info = { 328be284705SAlistair Francis .name = TYPE_STM32F2XX_TIMER, 329be284705SAlistair Francis .parent = TYPE_SYS_BUS_DEVICE, 330be284705SAlistair Francis .instance_size = sizeof(STM32F2XXTimerState), 331be284705SAlistair Francis .instance_init = stm32f2xx_timer_init, 332be284705SAlistair Francis .class_init = stm32f2xx_timer_class_init, 333be284705SAlistair Francis }; 334be284705SAlistair Francis 335be284705SAlistair Francis static void stm32f2xx_timer_register_types(void) 336be284705SAlistair Francis { 337be284705SAlistair Francis type_register_static(&stm32f2xx_timer_info); 338be284705SAlistair Francis } 339be284705SAlistair Francis 340be284705SAlistair Francis type_init(stm32f2xx_timer_register_types) 341