1 /* 2 * QEMU Sparc SLAVIO timer controller emulation 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/timer.h" 27 #include "hw/irq.h" 28 #include "hw/ptimer.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/sysbus.h" 31 #include "migration/vmstate.h" 32 #include "trace.h" 33 #include "qemu/module.h" 34 #include "qom/object.h" 35 36 /* 37 * Registers of hardware timer in sun4m. 38 * 39 * This is the timer/counter part of chip STP2001 (Slave I/O), also 40 * produced as NCR89C105. See 41 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt 42 * 43 * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0 44 * are zero. Bit 31 is 1 when count has been reached. 45 * 46 * Per-CPU timers interrupt local CPU, system timer uses normal 47 * interrupt routing. 48 * 49 */ 50 51 #define MAX_CPUS 16 52 53 typedef struct CPUTimerState { 54 qemu_irq irq; 55 ptimer_state *timer; 56 uint32_t count, counthigh, reached; 57 /* processor only */ 58 uint32_t run; 59 uint64_t limit; 60 } CPUTimerState; 61 62 #define TYPE_SLAVIO_TIMER "slavio_timer" 63 typedef struct SLAVIO_TIMERState SLAVIO_TIMERState; 64 DECLARE_INSTANCE_CHECKER(SLAVIO_TIMERState, SLAVIO_TIMER, 65 TYPE_SLAVIO_TIMER) 66 67 struct SLAVIO_TIMERState { 68 SysBusDevice parent_obj; 69 70 uint32_t num_cpus; 71 uint32_t cputimer_mode; 72 CPUTimerState cputimer[MAX_CPUS + 1]; 73 }; 74 75 typedef struct TimerContext { 76 MemoryRegion iomem; 77 SLAVIO_TIMERState *s; 78 unsigned int timer_index; /* 0 for system, 1 ... MAX_CPUS for CPU timers */ 79 } TimerContext; 80 81 #define SYS_TIMER_SIZE 0x14 82 #define CPU_TIMER_SIZE 0x10 83 84 #define TIMER_LIMIT 0 85 #define TIMER_COUNTER 1 86 #define TIMER_COUNTER_NORST 2 87 #define TIMER_STATUS 3 88 #define TIMER_MODE 4 89 90 #define TIMER_COUNT_MASK32 0xfffffe00 91 #define TIMER_LIMIT_MASK32 0x7fffffff 92 #define TIMER_MAX_COUNT64 0x7ffffffffffffe00ULL 93 #define TIMER_MAX_COUNT32 0x7ffffe00ULL 94 #define TIMER_REACHED 0x80000000 95 #define TIMER_PERIOD 500ULL // 500ns 96 #define LIMIT_TO_PERIODS(l) (((l) >> 9) - 1) 97 #define PERIODS_TO_LIMIT(l) (((l) + 1) << 9) 98 99 static int slavio_timer_is_user(TimerContext *tc) 100 { 101 SLAVIO_TIMERState *s = tc->s; 102 unsigned int timer_index = tc->timer_index; 103 104 return timer_index != 0 && (s->cputimer_mode & (1 << (timer_index - 1))); 105 } 106 107 // Update count, set irq, update expire_time 108 // Convert from ptimer countdown units 109 static void slavio_timer_get_out(CPUTimerState *t) 110 { 111 uint64_t count, limit; 112 113 if (t->limit == 0) { /* free-run system or processor counter */ 114 limit = TIMER_MAX_COUNT32; 115 } else { 116 limit = t->limit; 117 } 118 count = limit - PERIODS_TO_LIMIT(ptimer_get_count(t->timer)); 119 120 trace_slavio_timer_get_out(t->limit, t->counthigh, t->count); 121 t->count = count & TIMER_COUNT_MASK32; 122 t->counthigh = count >> 32; 123 } 124 125 // timer callback 126 static void slavio_timer_irq(void *opaque) 127 { 128 TimerContext *tc = opaque; 129 SLAVIO_TIMERState *s = tc->s; 130 CPUTimerState *t = &s->cputimer[tc->timer_index]; 131 132 slavio_timer_get_out(t); 133 trace_slavio_timer_irq(t->counthigh, t->count); 134 /* if limit is 0 (free-run), there will be no match */ 135 if (t->limit != 0) { 136 t->reached = TIMER_REACHED; 137 } 138 /* there is no interrupt if user timer or free-run */ 139 if (!slavio_timer_is_user(tc) && t->limit != 0) { 140 qemu_irq_raise(t->irq); 141 } 142 } 143 144 static uint64_t slavio_timer_mem_readl(void *opaque, hwaddr addr, 145 unsigned size) 146 { 147 TimerContext *tc = opaque; 148 SLAVIO_TIMERState *s = tc->s; 149 uint32_t saddr, ret; 150 unsigned int timer_index = tc->timer_index; 151 CPUTimerState *t = &s->cputimer[timer_index]; 152 153 saddr = addr >> 2; 154 switch (saddr) { 155 case TIMER_LIMIT: 156 // read limit (system counter mode) or read most signifying 157 // part of counter (user mode) 158 if (slavio_timer_is_user(tc)) { 159 // read user timer MSW 160 slavio_timer_get_out(t); 161 ret = t->counthigh | t->reached; 162 } else { 163 // read limit 164 // clear irq 165 qemu_irq_lower(t->irq); 166 t->reached = 0; 167 ret = t->limit & TIMER_LIMIT_MASK32; 168 } 169 break; 170 case TIMER_COUNTER: 171 // read counter and reached bit (system mode) or read lsbits 172 // of counter (user mode) 173 slavio_timer_get_out(t); 174 if (slavio_timer_is_user(tc)) { // read user timer LSW 175 ret = t->count & TIMER_MAX_COUNT64; 176 } else { // read limit 177 ret = (t->count & TIMER_MAX_COUNT32) | 178 t->reached; 179 } 180 break; 181 case TIMER_STATUS: 182 // only available in processor counter/timer 183 // read start/stop status 184 if (timer_index > 0) { 185 ret = t->run; 186 } else { 187 ret = 0; 188 } 189 break; 190 case TIMER_MODE: 191 // only available in system counter 192 // read user/system mode 193 ret = s->cputimer_mode; 194 break; 195 default: 196 trace_slavio_timer_mem_readl_invalid(addr); 197 ret = 0; 198 break; 199 } 200 trace_slavio_timer_mem_readl(addr, ret); 201 return ret; 202 } 203 204 static void slavio_timer_mem_writel(void *opaque, hwaddr addr, 205 uint64_t val, unsigned size) 206 { 207 TimerContext *tc = opaque; 208 SLAVIO_TIMERState *s = tc->s; 209 uint32_t saddr; 210 unsigned int timer_index = tc->timer_index; 211 CPUTimerState *t = &s->cputimer[timer_index]; 212 213 trace_slavio_timer_mem_writel(addr, val); 214 saddr = addr >> 2; 215 switch (saddr) { 216 case TIMER_LIMIT: 217 ptimer_transaction_begin(t->timer); 218 if (slavio_timer_is_user(tc)) { 219 uint64_t count; 220 221 // set user counter MSW, reset counter 222 t->limit = TIMER_MAX_COUNT64; 223 t->counthigh = val & (TIMER_MAX_COUNT64 >> 32); 224 t->reached = 0; 225 count = ((uint64_t)t->counthigh << 32) | t->count; 226 trace_slavio_timer_mem_writel_limit(timer_index, count); 227 ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count)); 228 } else { 229 // set limit, reset counter 230 qemu_irq_lower(t->irq); 231 t->limit = val & TIMER_MAX_COUNT32; 232 if (t->limit == 0) { /* free-run */ 233 ptimer_set_limit(t->timer, 234 LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1); 235 } else { 236 ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 1); 237 } 238 } 239 ptimer_transaction_commit(t->timer); 240 break; 241 case TIMER_COUNTER: 242 if (slavio_timer_is_user(tc)) { 243 uint64_t count; 244 245 // set user counter LSW, reset counter 246 t->limit = TIMER_MAX_COUNT64; 247 t->count = val & TIMER_MAX_COUNT64; 248 t->reached = 0; 249 count = ((uint64_t)t->counthigh) << 32 | t->count; 250 trace_slavio_timer_mem_writel_limit(timer_index, count); 251 ptimer_transaction_begin(t->timer); 252 ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count)); 253 ptimer_transaction_commit(t->timer); 254 } else { 255 trace_slavio_timer_mem_writel_counter_invalid(); 256 } 257 break; 258 case TIMER_COUNTER_NORST: 259 // set limit without resetting counter 260 t->limit = val & TIMER_MAX_COUNT32; 261 ptimer_transaction_begin(t->timer); 262 if (t->limit == 0) { /* free-run */ 263 ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0); 264 } else { 265 ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 0); 266 } 267 ptimer_transaction_commit(t->timer); 268 break; 269 case TIMER_STATUS: 270 ptimer_transaction_begin(t->timer); 271 if (slavio_timer_is_user(tc)) { 272 // start/stop user counter 273 if (val & 1) { 274 trace_slavio_timer_mem_writel_status_start(timer_index); 275 ptimer_run(t->timer, 0); 276 } else { 277 trace_slavio_timer_mem_writel_status_stop(timer_index); 278 ptimer_stop(t->timer); 279 } 280 } 281 t->run = val & 1; 282 ptimer_transaction_commit(t->timer); 283 break; 284 case TIMER_MODE: 285 if (timer_index == 0) { 286 unsigned int i; 287 288 for (i = 0; i < s->num_cpus; i++) { 289 unsigned int processor = 1 << i; 290 CPUTimerState *curr_timer = &s->cputimer[i + 1]; 291 292 ptimer_transaction_begin(curr_timer->timer); 293 // check for a change in timer mode for this processor 294 if ((val & processor) != (s->cputimer_mode & processor)) { 295 if (val & processor) { // counter -> user timer 296 qemu_irq_lower(curr_timer->irq); 297 // counters are always running 298 if (!curr_timer->run) { 299 ptimer_stop(curr_timer->timer); 300 } 301 // user timer limit is always the same 302 curr_timer->limit = TIMER_MAX_COUNT64; 303 ptimer_set_limit(curr_timer->timer, 304 LIMIT_TO_PERIODS(curr_timer->limit), 305 1); 306 // set this processors user timer bit in config 307 // register 308 s->cputimer_mode |= processor; 309 trace_slavio_timer_mem_writel_mode_user(timer_index); 310 } else { // user timer -> counter 311 // start the counter 312 ptimer_run(curr_timer->timer, 0); 313 // clear this processors user timer bit in config 314 // register 315 s->cputimer_mode &= ~processor; 316 trace_slavio_timer_mem_writel_mode_counter(timer_index); 317 } 318 } 319 ptimer_transaction_commit(curr_timer->timer); 320 } 321 } else { 322 trace_slavio_timer_mem_writel_mode_invalid(); 323 } 324 break; 325 default: 326 trace_slavio_timer_mem_writel_invalid(addr); 327 break; 328 } 329 } 330 331 static const MemoryRegionOps slavio_timer_mem_ops = { 332 .read = slavio_timer_mem_readl, 333 .write = slavio_timer_mem_writel, 334 .endianness = DEVICE_NATIVE_ENDIAN, 335 .valid = { 336 .min_access_size = 4, 337 .max_access_size = 4, 338 }, 339 }; 340 341 static const VMStateDescription vmstate_timer = { 342 .name ="timer", 343 .version_id = 3, 344 .minimum_version_id = 3, 345 .fields = (VMStateField[]) { 346 VMSTATE_UINT64(limit, CPUTimerState), 347 VMSTATE_UINT32(count, CPUTimerState), 348 VMSTATE_UINT32(counthigh, CPUTimerState), 349 VMSTATE_UINT32(reached, CPUTimerState), 350 VMSTATE_UINT32(run , CPUTimerState), 351 VMSTATE_PTIMER(timer, CPUTimerState), 352 VMSTATE_END_OF_LIST() 353 } 354 }; 355 356 static const VMStateDescription vmstate_slavio_timer = { 357 .name ="slavio_timer", 358 .version_id = 3, 359 .minimum_version_id = 3, 360 .fields = (VMStateField[]) { 361 VMSTATE_STRUCT_ARRAY(cputimer, SLAVIO_TIMERState, MAX_CPUS + 1, 3, 362 vmstate_timer, CPUTimerState), 363 VMSTATE_END_OF_LIST() 364 } 365 }; 366 367 static void slavio_timer_reset(DeviceState *d) 368 { 369 SLAVIO_TIMERState *s = SLAVIO_TIMER(d); 370 unsigned int i; 371 CPUTimerState *curr_timer; 372 373 for (i = 0; i <= MAX_CPUS; i++) { 374 curr_timer = &s->cputimer[i]; 375 curr_timer->limit = 0; 376 curr_timer->count = 0; 377 curr_timer->reached = 0; 378 if (i <= s->num_cpus) { 379 ptimer_transaction_begin(curr_timer->timer); 380 ptimer_set_limit(curr_timer->timer, 381 LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1); 382 ptimer_run(curr_timer->timer, 0); 383 curr_timer->run = 1; 384 ptimer_transaction_commit(curr_timer->timer); 385 } 386 } 387 s->cputimer_mode = 0; 388 } 389 390 static void slavio_timer_init(Object *obj) 391 { 392 SLAVIO_TIMERState *s = SLAVIO_TIMER(obj); 393 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 394 unsigned int i; 395 TimerContext *tc; 396 397 for (i = 0; i <= MAX_CPUS; i++) { 398 uint64_t size; 399 char timer_name[20]; 400 401 tc = g_malloc0(sizeof(TimerContext)); 402 tc->s = s; 403 tc->timer_index = i; 404 405 s->cputimer[i].timer = ptimer_init(slavio_timer_irq, tc, 406 PTIMER_POLICY_DEFAULT); 407 ptimer_transaction_begin(s->cputimer[i].timer); 408 ptimer_set_period(s->cputimer[i].timer, TIMER_PERIOD); 409 ptimer_transaction_commit(s->cputimer[i].timer); 410 411 size = i == 0 ? SYS_TIMER_SIZE : CPU_TIMER_SIZE; 412 snprintf(timer_name, sizeof(timer_name), "timer-%i", i); 413 memory_region_init_io(&tc->iomem, obj, &slavio_timer_mem_ops, tc, 414 timer_name, size); 415 sysbus_init_mmio(dev, &tc->iomem); 416 417 sysbus_init_irq(dev, &s->cputimer[i].irq); 418 } 419 } 420 421 static Property slavio_timer_properties[] = { 422 DEFINE_PROP_UINT32("num_cpus", SLAVIO_TIMERState, num_cpus, 0), 423 DEFINE_PROP_END_OF_LIST(), 424 }; 425 426 static void slavio_timer_class_init(ObjectClass *klass, void *data) 427 { 428 DeviceClass *dc = DEVICE_CLASS(klass); 429 430 dc->reset = slavio_timer_reset; 431 dc->vmsd = &vmstate_slavio_timer; 432 device_class_set_props(dc, slavio_timer_properties); 433 } 434 435 static const TypeInfo slavio_timer_info = { 436 .name = TYPE_SLAVIO_TIMER, 437 .parent = TYPE_SYS_BUS_DEVICE, 438 .instance_size = sizeof(SLAVIO_TIMERState), 439 .instance_init = slavio_timer_init, 440 .class_init = slavio_timer_class_init, 441 }; 442 443 static void slavio_timer_register_types(void) 444 { 445 type_register_static(&slavio_timer_info); 446 } 447 448 type_init(slavio_timer_register_types) 449