1 /* 2 * QEMU Sparc SLAVIO timer controller emulation 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/timer.h" 27 #include "hw/irq.h" 28 #include "hw/ptimer.h" 29 #include "hw/sysbus.h" 30 #include "migration/vmstate.h" 31 #include "trace.h" 32 #include "qemu/main-loop.h" 33 #include "qemu/module.h" 34 35 /* 36 * Registers of hardware timer in sun4m. 37 * 38 * This is the timer/counter part of chip STP2001 (Slave I/O), also 39 * produced as NCR89C105. See 40 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt 41 * 42 * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0 43 * are zero. Bit 31 is 1 when count has been reached. 44 * 45 * Per-CPU timers interrupt local CPU, system timer uses normal 46 * interrupt routing. 47 * 48 */ 49 50 #define MAX_CPUS 16 51 52 typedef struct CPUTimerState { 53 qemu_irq irq; 54 ptimer_state *timer; 55 uint32_t count, counthigh, reached; 56 /* processor only */ 57 uint32_t run; 58 uint64_t limit; 59 } CPUTimerState; 60 61 #define TYPE_SLAVIO_TIMER "slavio_timer" 62 #define SLAVIO_TIMER(obj) \ 63 OBJECT_CHECK(SLAVIO_TIMERState, (obj), TYPE_SLAVIO_TIMER) 64 65 typedef struct SLAVIO_TIMERState { 66 SysBusDevice parent_obj; 67 68 uint32_t num_cpus; 69 uint32_t cputimer_mode; 70 CPUTimerState cputimer[MAX_CPUS + 1]; 71 } SLAVIO_TIMERState; 72 73 typedef struct TimerContext { 74 MemoryRegion iomem; 75 SLAVIO_TIMERState *s; 76 unsigned int timer_index; /* 0 for system, 1 ... MAX_CPUS for CPU timers */ 77 } TimerContext; 78 79 #define SYS_TIMER_SIZE 0x14 80 #define CPU_TIMER_SIZE 0x10 81 82 #define TIMER_LIMIT 0 83 #define TIMER_COUNTER 1 84 #define TIMER_COUNTER_NORST 2 85 #define TIMER_STATUS 3 86 #define TIMER_MODE 4 87 88 #define TIMER_COUNT_MASK32 0xfffffe00 89 #define TIMER_LIMIT_MASK32 0x7fffffff 90 #define TIMER_MAX_COUNT64 0x7ffffffffffffe00ULL 91 #define TIMER_MAX_COUNT32 0x7ffffe00ULL 92 #define TIMER_REACHED 0x80000000 93 #define TIMER_PERIOD 500ULL // 500ns 94 #define LIMIT_TO_PERIODS(l) (((l) >> 9) - 1) 95 #define PERIODS_TO_LIMIT(l) (((l) + 1) << 9) 96 97 static int slavio_timer_is_user(TimerContext *tc) 98 { 99 SLAVIO_TIMERState *s = tc->s; 100 unsigned int timer_index = tc->timer_index; 101 102 return timer_index != 0 && (s->cputimer_mode & (1 << (timer_index - 1))); 103 } 104 105 // Update count, set irq, update expire_time 106 // Convert from ptimer countdown units 107 static void slavio_timer_get_out(CPUTimerState *t) 108 { 109 uint64_t count, limit; 110 111 if (t->limit == 0) { /* free-run system or processor counter */ 112 limit = TIMER_MAX_COUNT32; 113 } else { 114 limit = t->limit; 115 } 116 count = limit - PERIODS_TO_LIMIT(ptimer_get_count(t->timer)); 117 118 trace_slavio_timer_get_out(t->limit, t->counthigh, t->count); 119 t->count = count & TIMER_COUNT_MASK32; 120 t->counthigh = count >> 32; 121 } 122 123 // timer callback 124 static void slavio_timer_irq(void *opaque) 125 { 126 TimerContext *tc = opaque; 127 SLAVIO_TIMERState *s = tc->s; 128 CPUTimerState *t = &s->cputimer[tc->timer_index]; 129 130 slavio_timer_get_out(t); 131 trace_slavio_timer_irq(t->counthigh, t->count); 132 /* if limit is 0 (free-run), there will be no match */ 133 if (t->limit != 0) { 134 t->reached = TIMER_REACHED; 135 } 136 /* there is no interrupt if user timer or free-run */ 137 if (!slavio_timer_is_user(tc) && t->limit != 0) { 138 qemu_irq_raise(t->irq); 139 } 140 } 141 142 static uint64_t slavio_timer_mem_readl(void *opaque, hwaddr addr, 143 unsigned size) 144 { 145 TimerContext *tc = opaque; 146 SLAVIO_TIMERState *s = tc->s; 147 uint32_t saddr, ret; 148 unsigned int timer_index = tc->timer_index; 149 CPUTimerState *t = &s->cputimer[timer_index]; 150 151 saddr = addr >> 2; 152 switch (saddr) { 153 case TIMER_LIMIT: 154 // read limit (system counter mode) or read most signifying 155 // part of counter (user mode) 156 if (slavio_timer_is_user(tc)) { 157 // read user timer MSW 158 slavio_timer_get_out(t); 159 ret = t->counthigh | t->reached; 160 } else { 161 // read limit 162 // clear irq 163 qemu_irq_lower(t->irq); 164 t->reached = 0; 165 ret = t->limit & TIMER_LIMIT_MASK32; 166 } 167 break; 168 case TIMER_COUNTER: 169 // read counter and reached bit (system mode) or read lsbits 170 // of counter (user mode) 171 slavio_timer_get_out(t); 172 if (slavio_timer_is_user(tc)) { // read user timer LSW 173 ret = t->count & TIMER_MAX_COUNT64; 174 } else { // read limit 175 ret = (t->count & TIMER_MAX_COUNT32) | 176 t->reached; 177 } 178 break; 179 case TIMER_STATUS: 180 // only available in processor counter/timer 181 // read start/stop status 182 if (timer_index > 0) { 183 ret = t->run; 184 } else { 185 ret = 0; 186 } 187 break; 188 case TIMER_MODE: 189 // only available in system counter 190 // read user/system mode 191 ret = s->cputimer_mode; 192 break; 193 default: 194 trace_slavio_timer_mem_readl_invalid(addr); 195 ret = 0; 196 break; 197 } 198 trace_slavio_timer_mem_readl(addr, ret); 199 return ret; 200 } 201 202 static void slavio_timer_mem_writel(void *opaque, hwaddr addr, 203 uint64_t val, unsigned size) 204 { 205 TimerContext *tc = opaque; 206 SLAVIO_TIMERState *s = tc->s; 207 uint32_t saddr; 208 unsigned int timer_index = tc->timer_index; 209 CPUTimerState *t = &s->cputimer[timer_index]; 210 211 trace_slavio_timer_mem_writel(addr, val); 212 saddr = addr >> 2; 213 switch (saddr) { 214 case TIMER_LIMIT: 215 if (slavio_timer_is_user(tc)) { 216 uint64_t count; 217 218 // set user counter MSW, reset counter 219 t->limit = TIMER_MAX_COUNT64; 220 t->counthigh = val & (TIMER_MAX_COUNT64 >> 32); 221 t->reached = 0; 222 count = ((uint64_t)t->counthigh << 32) | t->count; 223 trace_slavio_timer_mem_writel_limit(timer_index, count); 224 ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count)); 225 } else { 226 // set limit, reset counter 227 qemu_irq_lower(t->irq); 228 t->limit = val & TIMER_MAX_COUNT32; 229 if (t->timer) { 230 if (t->limit == 0) { /* free-run */ 231 ptimer_set_limit(t->timer, 232 LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1); 233 } else { 234 ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 1); 235 } 236 } 237 } 238 break; 239 case TIMER_COUNTER: 240 if (slavio_timer_is_user(tc)) { 241 uint64_t count; 242 243 // set user counter LSW, reset counter 244 t->limit = TIMER_MAX_COUNT64; 245 t->count = val & TIMER_MAX_COUNT64; 246 t->reached = 0; 247 count = ((uint64_t)t->counthigh) << 32 | t->count; 248 trace_slavio_timer_mem_writel_limit(timer_index, count); 249 ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count)); 250 } else { 251 trace_slavio_timer_mem_writel_counter_invalid(); 252 } 253 break; 254 case TIMER_COUNTER_NORST: 255 // set limit without resetting counter 256 t->limit = val & TIMER_MAX_COUNT32; 257 if (t->limit == 0) { /* free-run */ 258 ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0); 259 } else { 260 ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 0); 261 } 262 break; 263 case TIMER_STATUS: 264 if (slavio_timer_is_user(tc)) { 265 // start/stop user counter 266 if (val & 1) { 267 trace_slavio_timer_mem_writel_status_start(timer_index); 268 ptimer_run(t->timer, 0); 269 } else { 270 trace_slavio_timer_mem_writel_status_stop(timer_index); 271 ptimer_stop(t->timer); 272 } 273 } 274 t->run = val & 1; 275 break; 276 case TIMER_MODE: 277 if (timer_index == 0) { 278 unsigned int i; 279 280 for (i = 0; i < s->num_cpus; i++) { 281 unsigned int processor = 1 << i; 282 CPUTimerState *curr_timer = &s->cputimer[i + 1]; 283 284 // check for a change in timer mode for this processor 285 if ((val & processor) != (s->cputimer_mode & processor)) { 286 if (val & processor) { // counter -> user timer 287 qemu_irq_lower(curr_timer->irq); 288 // counters are always running 289 if (!curr_timer->run) { 290 ptimer_stop(curr_timer->timer); 291 } 292 // user timer limit is always the same 293 curr_timer->limit = TIMER_MAX_COUNT64; 294 ptimer_set_limit(curr_timer->timer, 295 LIMIT_TO_PERIODS(curr_timer->limit), 296 1); 297 // set this processors user timer bit in config 298 // register 299 s->cputimer_mode |= processor; 300 trace_slavio_timer_mem_writel_mode_user(timer_index); 301 } else { // user timer -> counter 302 // start the counter 303 ptimer_run(curr_timer->timer, 0); 304 // clear this processors user timer bit in config 305 // register 306 s->cputimer_mode &= ~processor; 307 trace_slavio_timer_mem_writel_mode_counter(timer_index); 308 } 309 } 310 } 311 } else { 312 trace_slavio_timer_mem_writel_mode_invalid(); 313 } 314 break; 315 default: 316 trace_slavio_timer_mem_writel_invalid(addr); 317 break; 318 } 319 } 320 321 static const MemoryRegionOps slavio_timer_mem_ops = { 322 .read = slavio_timer_mem_readl, 323 .write = slavio_timer_mem_writel, 324 .endianness = DEVICE_NATIVE_ENDIAN, 325 .valid = { 326 .min_access_size = 4, 327 .max_access_size = 4, 328 }, 329 }; 330 331 static const VMStateDescription vmstate_timer = { 332 .name ="timer", 333 .version_id = 3, 334 .minimum_version_id = 3, 335 .fields = (VMStateField[]) { 336 VMSTATE_UINT64(limit, CPUTimerState), 337 VMSTATE_UINT32(count, CPUTimerState), 338 VMSTATE_UINT32(counthigh, CPUTimerState), 339 VMSTATE_UINT32(reached, CPUTimerState), 340 VMSTATE_UINT32(run , CPUTimerState), 341 VMSTATE_PTIMER(timer, CPUTimerState), 342 VMSTATE_END_OF_LIST() 343 } 344 }; 345 346 static const VMStateDescription vmstate_slavio_timer = { 347 .name ="slavio_timer", 348 .version_id = 3, 349 .minimum_version_id = 3, 350 .fields = (VMStateField[]) { 351 VMSTATE_STRUCT_ARRAY(cputimer, SLAVIO_TIMERState, MAX_CPUS + 1, 3, 352 vmstate_timer, CPUTimerState), 353 VMSTATE_END_OF_LIST() 354 } 355 }; 356 357 static void slavio_timer_reset(DeviceState *d) 358 { 359 SLAVIO_TIMERState *s = SLAVIO_TIMER(d); 360 unsigned int i; 361 CPUTimerState *curr_timer; 362 363 for (i = 0; i <= MAX_CPUS; i++) { 364 curr_timer = &s->cputimer[i]; 365 curr_timer->limit = 0; 366 curr_timer->count = 0; 367 curr_timer->reached = 0; 368 if (i <= s->num_cpus) { 369 ptimer_set_limit(curr_timer->timer, 370 LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1); 371 ptimer_run(curr_timer->timer, 0); 372 curr_timer->run = 1; 373 } 374 } 375 s->cputimer_mode = 0; 376 } 377 378 static void slavio_timer_init(Object *obj) 379 { 380 SLAVIO_TIMERState *s = SLAVIO_TIMER(obj); 381 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 382 QEMUBH *bh; 383 unsigned int i; 384 TimerContext *tc; 385 386 for (i = 0; i <= MAX_CPUS; i++) { 387 uint64_t size; 388 char timer_name[20]; 389 390 tc = g_malloc0(sizeof(TimerContext)); 391 tc->s = s; 392 tc->timer_index = i; 393 394 bh = qemu_bh_new(slavio_timer_irq, tc); 395 s->cputimer[i].timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); 396 ptimer_set_period(s->cputimer[i].timer, TIMER_PERIOD); 397 398 size = i == 0 ? SYS_TIMER_SIZE : CPU_TIMER_SIZE; 399 snprintf(timer_name, sizeof(timer_name), "timer-%i", i); 400 memory_region_init_io(&tc->iomem, obj, &slavio_timer_mem_ops, tc, 401 timer_name, size); 402 sysbus_init_mmio(dev, &tc->iomem); 403 404 sysbus_init_irq(dev, &s->cputimer[i].irq); 405 } 406 } 407 408 static Property slavio_timer_properties[] = { 409 DEFINE_PROP_UINT32("num_cpus", SLAVIO_TIMERState, num_cpus, 0), 410 DEFINE_PROP_END_OF_LIST(), 411 }; 412 413 static void slavio_timer_class_init(ObjectClass *klass, void *data) 414 { 415 DeviceClass *dc = DEVICE_CLASS(klass); 416 417 dc->reset = slavio_timer_reset; 418 dc->vmsd = &vmstate_slavio_timer; 419 dc->props = slavio_timer_properties; 420 } 421 422 static const TypeInfo slavio_timer_info = { 423 .name = TYPE_SLAVIO_TIMER, 424 .parent = TYPE_SYS_BUS_DEVICE, 425 .instance_size = sizeof(SLAVIO_TIMERState), 426 .instance_init = slavio_timer_init, 427 .class_init = slavio_timer_class_init, 428 }; 429 430 static void slavio_timer_register_types(void) 431 { 432 type_register_static(&slavio_timer_info); 433 } 434 435 type_init(slavio_timer_register_types) 436