1 /* 2 * QEMU Sparc SLAVIO timer controller emulation 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "hw/sparc/sun4m.h" 26 #include "qemu/timer.h" 27 #include "hw/ptimer.h" 28 #include "hw/sysbus.h" 29 #include "trace.h" 30 31 /* 32 * Registers of hardware timer in sun4m. 33 * 34 * This is the timer/counter part of chip STP2001 (Slave I/O), also 35 * produced as NCR89C105. See 36 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt 37 * 38 * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0 39 * are zero. Bit 31 is 1 when count has been reached. 40 * 41 * Per-CPU timers interrupt local CPU, system timer uses normal 42 * interrupt routing. 43 * 44 */ 45 46 #define MAX_CPUS 16 47 48 typedef struct CPUTimerState { 49 qemu_irq irq; 50 ptimer_state *timer; 51 uint32_t count, counthigh, reached; 52 /* processor only */ 53 uint32_t running; 54 uint64_t limit; 55 } CPUTimerState; 56 57 #define TYPE_SLAVIO_TIMER "slavio_timer" 58 #define SLAVIO_TIMER(obj) \ 59 OBJECT_CHECK(SLAVIO_TIMERState, (obj), TYPE_SLAVIO_TIMER) 60 61 typedef struct SLAVIO_TIMERState { 62 SysBusDevice parent_obj; 63 64 uint32_t num_cpus; 65 uint32_t cputimer_mode; 66 CPUTimerState cputimer[MAX_CPUS + 1]; 67 } SLAVIO_TIMERState; 68 69 typedef struct TimerContext { 70 MemoryRegion iomem; 71 SLAVIO_TIMERState *s; 72 unsigned int timer_index; /* 0 for system, 1 ... MAX_CPUS for CPU timers */ 73 } TimerContext; 74 75 #define SYS_TIMER_SIZE 0x14 76 #define CPU_TIMER_SIZE 0x10 77 78 #define TIMER_LIMIT 0 79 #define TIMER_COUNTER 1 80 #define TIMER_COUNTER_NORST 2 81 #define TIMER_STATUS 3 82 #define TIMER_MODE 4 83 84 #define TIMER_COUNT_MASK32 0xfffffe00 85 #define TIMER_LIMIT_MASK32 0x7fffffff 86 #define TIMER_MAX_COUNT64 0x7ffffffffffffe00ULL 87 #define TIMER_MAX_COUNT32 0x7ffffe00ULL 88 #define TIMER_REACHED 0x80000000 89 #define TIMER_PERIOD 500ULL // 500ns 90 #define LIMIT_TO_PERIODS(l) (((l) >> 9) - 1) 91 #define PERIODS_TO_LIMIT(l) (((l) + 1) << 9) 92 93 static int slavio_timer_is_user(TimerContext *tc) 94 { 95 SLAVIO_TIMERState *s = tc->s; 96 unsigned int timer_index = tc->timer_index; 97 98 return timer_index != 0 && (s->cputimer_mode & (1 << (timer_index - 1))); 99 } 100 101 // Update count, set irq, update expire_time 102 // Convert from ptimer countdown units 103 static void slavio_timer_get_out(CPUTimerState *t) 104 { 105 uint64_t count, limit; 106 107 if (t->limit == 0) { /* free-run system or processor counter */ 108 limit = TIMER_MAX_COUNT32; 109 } else { 110 limit = t->limit; 111 } 112 count = limit - PERIODS_TO_LIMIT(ptimer_get_count(t->timer)); 113 114 trace_slavio_timer_get_out(t->limit, t->counthigh, t->count); 115 t->count = count & TIMER_COUNT_MASK32; 116 t->counthigh = count >> 32; 117 } 118 119 // timer callback 120 static void slavio_timer_irq(void *opaque) 121 { 122 TimerContext *tc = opaque; 123 SLAVIO_TIMERState *s = tc->s; 124 CPUTimerState *t = &s->cputimer[tc->timer_index]; 125 126 slavio_timer_get_out(t); 127 trace_slavio_timer_irq(t->counthigh, t->count); 128 /* if limit is 0 (free-run), there will be no match */ 129 if (t->limit != 0) { 130 t->reached = TIMER_REACHED; 131 } 132 /* there is no interrupt if user timer or free-run */ 133 if (!slavio_timer_is_user(tc) && t->limit != 0) { 134 qemu_irq_raise(t->irq); 135 } 136 } 137 138 static uint64_t slavio_timer_mem_readl(void *opaque, hwaddr addr, 139 unsigned size) 140 { 141 TimerContext *tc = opaque; 142 SLAVIO_TIMERState *s = tc->s; 143 uint32_t saddr, ret; 144 unsigned int timer_index = tc->timer_index; 145 CPUTimerState *t = &s->cputimer[timer_index]; 146 147 saddr = addr >> 2; 148 switch (saddr) { 149 case TIMER_LIMIT: 150 // read limit (system counter mode) or read most signifying 151 // part of counter (user mode) 152 if (slavio_timer_is_user(tc)) { 153 // read user timer MSW 154 slavio_timer_get_out(t); 155 ret = t->counthigh | t->reached; 156 } else { 157 // read limit 158 // clear irq 159 qemu_irq_lower(t->irq); 160 t->reached = 0; 161 ret = t->limit & TIMER_LIMIT_MASK32; 162 } 163 break; 164 case TIMER_COUNTER: 165 // read counter and reached bit (system mode) or read lsbits 166 // of counter (user mode) 167 slavio_timer_get_out(t); 168 if (slavio_timer_is_user(tc)) { // read user timer LSW 169 ret = t->count & TIMER_MAX_COUNT64; 170 } else { // read limit 171 ret = (t->count & TIMER_MAX_COUNT32) | 172 t->reached; 173 } 174 break; 175 case TIMER_STATUS: 176 // only available in processor counter/timer 177 // read start/stop status 178 if (timer_index > 0) { 179 ret = t->running; 180 } else { 181 ret = 0; 182 } 183 break; 184 case TIMER_MODE: 185 // only available in system counter 186 // read user/system mode 187 ret = s->cputimer_mode; 188 break; 189 default: 190 trace_slavio_timer_mem_readl_invalid(addr); 191 ret = 0; 192 break; 193 } 194 trace_slavio_timer_mem_readl(addr, ret); 195 return ret; 196 } 197 198 static void slavio_timer_mem_writel(void *opaque, hwaddr addr, 199 uint64_t val, unsigned size) 200 { 201 TimerContext *tc = opaque; 202 SLAVIO_TIMERState *s = tc->s; 203 uint32_t saddr; 204 unsigned int timer_index = tc->timer_index; 205 CPUTimerState *t = &s->cputimer[timer_index]; 206 207 trace_slavio_timer_mem_writel(addr, val); 208 saddr = addr >> 2; 209 switch (saddr) { 210 case TIMER_LIMIT: 211 if (slavio_timer_is_user(tc)) { 212 uint64_t count; 213 214 // set user counter MSW, reset counter 215 t->limit = TIMER_MAX_COUNT64; 216 t->counthigh = val & (TIMER_MAX_COUNT64 >> 32); 217 t->reached = 0; 218 count = ((uint64_t)t->counthigh << 32) | t->count; 219 trace_slavio_timer_mem_writel_limit(timer_index, count); 220 ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count)); 221 } else { 222 // set limit, reset counter 223 qemu_irq_lower(t->irq); 224 t->limit = val & TIMER_MAX_COUNT32; 225 if (t->timer) { 226 if (t->limit == 0) { /* free-run */ 227 ptimer_set_limit(t->timer, 228 LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1); 229 } else { 230 ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 1); 231 } 232 } 233 } 234 break; 235 case TIMER_COUNTER: 236 if (slavio_timer_is_user(tc)) { 237 uint64_t count; 238 239 // set user counter LSW, reset counter 240 t->limit = TIMER_MAX_COUNT64; 241 t->count = val & TIMER_MAX_COUNT64; 242 t->reached = 0; 243 count = ((uint64_t)t->counthigh) << 32 | t->count; 244 trace_slavio_timer_mem_writel_limit(timer_index, count); 245 ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count)); 246 } else { 247 trace_slavio_timer_mem_writel_counter_invalid(); 248 } 249 break; 250 case TIMER_COUNTER_NORST: 251 // set limit without resetting counter 252 t->limit = val & TIMER_MAX_COUNT32; 253 if (t->limit == 0) { /* free-run */ 254 ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0); 255 } else { 256 ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 0); 257 } 258 break; 259 case TIMER_STATUS: 260 if (slavio_timer_is_user(tc)) { 261 // start/stop user counter 262 if ((val & 1) && !t->running) { 263 trace_slavio_timer_mem_writel_status_start(timer_index); 264 ptimer_run(t->timer, 0); 265 t->running = 1; 266 } else if (!(val & 1) && t->running) { 267 trace_slavio_timer_mem_writel_status_stop(timer_index); 268 ptimer_stop(t->timer); 269 t->running = 0; 270 } 271 } 272 break; 273 case TIMER_MODE: 274 if (timer_index == 0) { 275 unsigned int i; 276 277 for (i = 0; i < s->num_cpus; i++) { 278 unsigned int processor = 1 << i; 279 CPUTimerState *curr_timer = &s->cputimer[i + 1]; 280 281 // check for a change in timer mode for this processor 282 if ((val & processor) != (s->cputimer_mode & processor)) { 283 if (val & processor) { // counter -> user timer 284 qemu_irq_lower(curr_timer->irq); 285 // counters are always running 286 ptimer_stop(curr_timer->timer); 287 curr_timer->running = 0; 288 // user timer limit is always the same 289 curr_timer->limit = TIMER_MAX_COUNT64; 290 ptimer_set_limit(curr_timer->timer, 291 LIMIT_TO_PERIODS(curr_timer->limit), 292 1); 293 // set this processors user timer bit in config 294 // register 295 s->cputimer_mode |= processor; 296 trace_slavio_timer_mem_writel_mode_user(timer_index); 297 } else { // user timer -> counter 298 // stop the user timer if it is running 299 if (curr_timer->running) { 300 ptimer_stop(curr_timer->timer); 301 } 302 // start the counter 303 ptimer_run(curr_timer->timer, 0); 304 curr_timer->running = 1; 305 // clear this processors user timer bit in config 306 // register 307 s->cputimer_mode &= ~processor; 308 trace_slavio_timer_mem_writel_mode_counter(timer_index); 309 } 310 } 311 } 312 } else { 313 trace_slavio_timer_mem_writel_mode_invalid(); 314 } 315 break; 316 default: 317 trace_slavio_timer_mem_writel_invalid(addr); 318 break; 319 } 320 } 321 322 static const MemoryRegionOps slavio_timer_mem_ops = { 323 .read = slavio_timer_mem_readl, 324 .write = slavio_timer_mem_writel, 325 .endianness = DEVICE_NATIVE_ENDIAN, 326 .valid = { 327 .min_access_size = 4, 328 .max_access_size = 4, 329 }, 330 }; 331 332 static const VMStateDescription vmstate_timer = { 333 .name ="timer", 334 .version_id = 3, 335 .minimum_version_id = 3, 336 .minimum_version_id_old = 3, 337 .fields = (VMStateField []) { 338 VMSTATE_UINT64(limit, CPUTimerState), 339 VMSTATE_UINT32(count, CPUTimerState), 340 VMSTATE_UINT32(counthigh, CPUTimerState), 341 VMSTATE_UINT32(reached, CPUTimerState), 342 VMSTATE_UINT32(running, CPUTimerState), 343 VMSTATE_PTIMER(timer, CPUTimerState), 344 VMSTATE_END_OF_LIST() 345 } 346 }; 347 348 static const VMStateDescription vmstate_slavio_timer = { 349 .name ="slavio_timer", 350 .version_id = 3, 351 .minimum_version_id = 3, 352 .minimum_version_id_old = 3, 353 .fields = (VMStateField []) { 354 VMSTATE_STRUCT_ARRAY(cputimer, SLAVIO_TIMERState, MAX_CPUS + 1, 3, 355 vmstate_timer, CPUTimerState), 356 VMSTATE_END_OF_LIST() 357 } 358 }; 359 360 static void slavio_timer_reset(DeviceState *d) 361 { 362 SLAVIO_TIMERState *s = SLAVIO_TIMER(d); 363 unsigned int i; 364 CPUTimerState *curr_timer; 365 366 for (i = 0; i <= MAX_CPUS; i++) { 367 curr_timer = &s->cputimer[i]; 368 curr_timer->limit = 0; 369 curr_timer->count = 0; 370 curr_timer->reached = 0; 371 if (i <= s->num_cpus) { 372 ptimer_set_limit(curr_timer->timer, 373 LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1); 374 ptimer_run(curr_timer->timer, 0); 375 curr_timer->running = 1; 376 } 377 } 378 s->cputimer_mode = 0; 379 } 380 381 static int slavio_timer_init1(SysBusDevice *dev) 382 { 383 SLAVIO_TIMERState *s = SLAVIO_TIMER(dev); 384 QEMUBH *bh; 385 unsigned int i; 386 TimerContext *tc; 387 388 for (i = 0; i <= MAX_CPUS; i++) { 389 uint64_t size; 390 char timer_name[20]; 391 392 tc = g_malloc0(sizeof(TimerContext)); 393 tc->s = s; 394 tc->timer_index = i; 395 396 bh = qemu_bh_new(slavio_timer_irq, tc); 397 s->cputimer[i].timer = ptimer_init(bh); 398 ptimer_set_period(s->cputimer[i].timer, TIMER_PERIOD); 399 400 size = i == 0 ? SYS_TIMER_SIZE : CPU_TIMER_SIZE; 401 snprintf(timer_name, sizeof(timer_name), "timer-%i", i); 402 memory_region_init_io(&tc->iomem, OBJECT(s), &slavio_timer_mem_ops, tc, 403 timer_name, size); 404 sysbus_init_mmio(dev, &tc->iomem); 405 406 sysbus_init_irq(dev, &s->cputimer[i].irq); 407 } 408 409 return 0; 410 } 411 412 static Property slavio_timer_properties[] = { 413 DEFINE_PROP_UINT32("num_cpus", SLAVIO_TIMERState, num_cpus, 0), 414 DEFINE_PROP_END_OF_LIST(), 415 }; 416 417 static void slavio_timer_class_init(ObjectClass *klass, void *data) 418 { 419 DeviceClass *dc = DEVICE_CLASS(klass); 420 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 421 422 k->init = slavio_timer_init1; 423 dc->reset = slavio_timer_reset; 424 dc->vmsd = &vmstate_slavio_timer; 425 dc->props = slavio_timer_properties; 426 } 427 428 static const TypeInfo slavio_timer_info = { 429 .name = TYPE_SLAVIO_TIMER, 430 .parent = TYPE_SYS_BUS_DEVICE, 431 .instance_size = sizeof(SLAVIO_TIMERState), 432 .class_init = slavio_timer_class_init, 433 }; 434 435 static void slavio_timer_register_types(void) 436 { 437 type_register_static(&slavio_timer_info); 438 } 439 440 type_init(slavio_timer_register_types) 441