1 /* 2 * SuperH Timer modules. 3 * 4 * Copyright (c) 2007 Magnus Damm 5 * Based on arm_timer.c by Paul Brook 6 * Copyright (c) 2005-2006 CodeSourcery. 7 * 8 * This code is licensed under the GPL. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "exec/memory.h" 13 #include "hw/hw.h" 14 #include "hw/irq.h" 15 #include "hw/sh4/sh.h" 16 #include "hw/timer/tmu012.h" 17 #include "hw/ptimer.h" 18 19 //#define DEBUG_TIMER 20 21 #define TIMER_TCR_TPSC (7 << 0) 22 #define TIMER_TCR_CKEG (3 << 3) 23 #define TIMER_TCR_UNIE (1 << 5) 24 #define TIMER_TCR_ICPE (3 << 6) 25 #define TIMER_TCR_UNF (1 << 8) 26 #define TIMER_TCR_ICPF (1 << 9) 27 #define TIMER_TCR_RESERVED (0x3f << 10) 28 29 #define TIMER_FEAT_CAPT (1 << 0) 30 #define TIMER_FEAT_EXTCLK (1 << 1) 31 32 #define OFFSET_TCOR 0 33 #define OFFSET_TCNT 1 34 #define OFFSET_TCR 2 35 #define OFFSET_TCPR 3 36 37 typedef struct { 38 ptimer_state *timer; 39 uint32_t tcnt; 40 uint32_t tcor; 41 uint32_t tcr; 42 uint32_t tcpr; 43 int freq; 44 int int_level; 45 int old_level; 46 int feat; 47 int enabled; 48 qemu_irq irq; 49 } sh_timer_state; 50 51 /* Check all active timers, and schedule the next timer interrupt. */ 52 53 static void sh_timer_update(sh_timer_state *s) 54 { 55 int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE); 56 57 if (new_level != s->old_level) 58 qemu_set_irq (s->irq, new_level); 59 60 s->old_level = s->int_level; 61 s->int_level = new_level; 62 } 63 64 static uint32_t sh_timer_read(void *opaque, hwaddr offset) 65 { 66 sh_timer_state *s = (sh_timer_state *)opaque; 67 68 switch (offset >> 2) { 69 case OFFSET_TCOR: 70 return s->tcor; 71 case OFFSET_TCNT: 72 return ptimer_get_count(s->timer); 73 case OFFSET_TCR: 74 return s->tcr | (s->int_level ? TIMER_TCR_UNF : 0); 75 case OFFSET_TCPR: 76 if (s->feat & TIMER_FEAT_CAPT) 77 return s->tcpr; 78 /* fall through */ 79 default: 80 hw_error("sh_timer_read: Bad offset %x\n", (int)offset); 81 return 0; 82 } 83 } 84 85 static void sh_timer_write(void *opaque, hwaddr offset, 86 uint32_t value) 87 { 88 sh_timer_state *s = (sh_timer_state *)opaque; 89 int freq; 90 91 switch (offset >> 2) { 92 case OFFSET_TCOR: 93 s->tcor = value; 94 ptimer_transaction_begin(s->timer); 95 ptimer_set_limit(s->timer, s->tcor, 0); 96 ptimer_transaction_commit(s->timer); 97 break; 98 case OFFSET_TCNT: 99 s->tcnt = value; 100 ptimer_transaction_begin(s->timer); 101 ptimer_set_count(s->timer, s->tcnt); 102 ptimer_transaction_commit(s->timer); 103 break; 104 case OFFSET_TCR: 105 ptimer_transaction_begin(s->timer); 106 if (s->enabled) { 107 /* Pause the timer if it is running. This may cause some 108 inaccuracy dure to rounding, but avoids a whole lot of other 109 messyness. */ 110 ptimer_stop(s->timer); 111 } 112 freq = s->freq; 113 /* ??? Need to recalculate expiry time after changing divisor. */ 114 switch (value & TIMER_TCR_TPSC) { 115 case 0: freq >>= 2; break; 116 case 1: freq >>= 4; break; 117 case 2: freq >>= 6; break; 118 case 3: freq >>= 8; break; 119 case 4: freq >>= 10; break; 120 case 6: 121 case 7: 122 if (s->feat & TIMER_FEAT_EXTCLK) { 123 break; 124 } 125 /* fallthrough */ 126 default: 127 hw_error("sh_timer_write: Reserved TPSC value\n"); 128 } 129 switch ((value & TIMER_TCR_CKEG) >> 3) { 130 case 0: 131 break; 132 case 1: 133 case 2: 134 case 3: 135 if (s->feat & TIMER_FEAT_EXTCLK) { 136 break; 137 } 138 /* fallthrough */ 139 default: 140 hw_error("sh_timer_write: Reserved CKEG value\n"); 141 } 142 switch ((value & TIMER_TCR_ICPE) >> 6) { 143 case 0: 144 break; 145 case 2: 146 case 3: 147 if (s->feat & TIMER_FEAT_CAPT) { 148 break; 149 } 150 /* fallthrough */ 151 default: 152 hw_error("sh_timer_write: Reserved ICPE value\n"); 153 } 154 if ((value & TIMER_TCR_UNF) == 0) { 155 s->int_level = 0; 156 } 157 158 value &= ~TIMER_TCR_UNF; 159 160 if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT))) { 161 hw_error("sh_timer_write: Reserved ICPF value\n"); 162 } 163 164 value &= ~TIMER_TCR_ICPF; /* capture not supported */ 165 166 if (value & TIMER_TCR_RESERVED) { 167 hw_error("sh_timer_write: Reserved TCR bits set\n"); 168 } 169 s->tcr = value; 170 ptimer_set_limit(s->timer, s->tcor, 0); 171 ptimer_set_freq(s->timer, freq); 172 if (s->enabled) { 173 /* Restart the timer if still enabled. */ 174 ptimer_run(s->timer, 0); 175 } 176 ptimer_transaction_commit(s->timer); 177 break; 178 case OFFSET_TCPR: 179 if (s->feat & TIMER_FEAT_CAPT) { 180 s->tcpr = value; 181 break; 182 } 183 /* fallthrough */ 184 default: 185 hw_error("sh_timer_write: Bad offset %x\n", (int)offset); 186 } 187 sh_timer_update(s); 188 } 189 190 static void sh_timer_start_stop(void *opaque, int enable) 191 { 192 sh_timer_state *s = (sh_timer_state *)opaque; 193 194 #ifdef DEBUG_TIMER 195 printf("sh_timer_start_stop %d (%d)\n", enable, s->enabled); 196 #endif 197 198 ptimer_transaction_begin(s->timer); 199 if (s->enabled && !enable) { 200 ptimer_stop(s->timer); 201 } 202 if (!s->enabled && enable) { 203 ptimer_run(s->timer, 0); 204 } 205 ptimer_transaction_commit(s->timer); 206 s->enabled = !!enable; 207 208 #ifdef DEBUG_TIMER 209 printf("sh_timer_start_stop done %d\n", s->enabled); 210 #endif 211 } 212 213 static void sh_timer_tick(void *opaque) 214 { 215 sh_timer_state *s = (sh_timer_state *)opaque; 216 s->int_level = s->enabled; 217 sh_timer_update(s); 218 } 219 220 static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq) 221 { 222 sh_timer_state *s; 223 224 s = (sh_timer_state *)g_malloc0(sizeof(sh_timer_state)); 225 s->freq = freq; 226 s->feat = feat; 227 s->tcor = 0xffffffff; 228 s->tcnt = 0xffffffff; 229 s->tcpr = 0xdeadbeef; 230 s->tcr = 0; 231 s->enabled = 0; 232 s->irq = irq; 233 234 s->timer = ptimer_init(sh_timer_tick, s, PTIMER_POLICY_DEFAULT); 235 236 sh_timer_write(s, OFFSET_TCOR >> 2, s->tcor); 237 sh_timer_write(s, OFFSET_TCNT >> 2, s->tcnt); 238 sh_timer_write(s, OFFSET_TCPR >> 2, s->tcpr); 239 sh_timer_write(s, OFFSET_TCR >> 2, s->tcpr); 240 /* ??? Save/restore. */ 241 return s; 242 } 243 244 typedef struct { 245 MemoryRegion iomem; 246 MemoryRegion iomem_p4; 247 MemoryRegion iomem_a7; 248 void *timer[3]; 249 int level[3]; 250 uint32_t tocr; 251 uint32_t tstr; 252 int feat; 253 } tmu012_state; 254 255 static uint64_t tmu012_read(void *opaque, hwaddr offset, 256 unsigned size) 257 { 258 tmu012_state *s = (tmu012_state *)opaque; 259 260 #ifdef DEBUG_TIMER 261 printf("tmu012_read 0x%lx\n", (unsigned long) offset); 262 #endif 263 264 if (offset >= 0x20) { 265 if (!(s->feat & TMU012_FEAT_3CHAN)) { 266 hw_error("tmu012_write: Bad channel offset %x\n", (int)offset); 267 } 268 return sh_timer_read(s->timer[2], offset - 0x20); 269 } 270 271 if (offset >= 0x14) 272 return sh_timer_read(s->timer[1], offset - 0x14); 273 274 if (offset >= 0x08) 275 return sh_timer_read(s->timer[0], offset - 0x08); 276 277 if (offset == 4) 278 return s->tstr; 279 280 if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) 281 return s->tocr; 282 283 hw_error("tmu012_write: Bad offset %x\n", (int)offset); 284 return 0; 285 } 286 287 static void tmu012_write(void *opaque, hwaddr offset, 288 uint64_t value, unsigned size) 289 { 290 tmu012_state *s = (tmu012_state *)opaque; 291 292 #ifdef DEBUG_TIMER 293 printf("tmu012_write 0x%lx 0x%08x\n", (unsigned long) offset, value); 294 #endif 295 296 if (offset >= 0x20) { 297 if (!(s->feat & TMU012_FEAT_3CHAN)) { 298 hw_error("tmu012_write: Bad channel offset %x\n", (int)offset); 299 } 300 sh_timer_write(s->timer[2], offset - 0x20, value); 301 return; 302 } 303 304 if (offset >= 0x14) { 305 sh_timer_write(s->timer[1], offset - 0x14, value); 306 return; 307 } 308 309 if (offset >= 0x08) { 310 sh_timer_write(s->timer[0], offset - 0x08, value); 311 return; 312 } 313 314 if (offset == 4) { 315 sh_timer_start_stop(s->timer[0], value & (1 << 0)); 316 sh_timer_start_stop(s->timer[1], value & (1 << 1)); 317 if (s->feat & TMU012_FEAT_3CHAN) { 318 sh_timer_start_stop(s->timer[2], value & (1 << 2)); 319 } else { 320 if (value & (1 << 2)) { 321 hw_error("tmu012_write: Bad channel\n"); 322 } 323 } 324 325 s->tstr = value; 326 return; 327 } 328 329 if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) { 330 s->tocr = value & (1 << 0); 331 } 332 } 333 334 static const MemoryRegionOps tmu012_ops = { 335 .read = tmu012_read, 336 .write = tmu012_write, 337 .endianness = DEVICE_NATIVE_ENDIAN, 338 }; 339 340 void tmu012_init(MemoryRegion *sysmem, hwaddr base, 341 int feat, uint32_t freq, 342 qemu_irq ch0_irq, qemu_irq ch1_irq, 343 qemu_irq ch2_irq0, qemu_irq ch2_irq1) 344 { 345 tmu012_state *s; 346 int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0; 347 348 s = (tmu012_state *)g_malloc0(sizeof(tmu012_state)); 349 s->feat = feat; 350 s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq); 351 s->timer[1] = sh_timer_init(freq, timer_feat, ch1_irq); 352 if (feat & TMU012_FEAT_3CHAN) { 353 s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT, 354 ch2_irq0); /* ch2_irq1 not supported */ 355 } 356 357 memory_region_init_io(&s->iomem, NULL, &tmu012_ops, s, 358 "timer", 0x100000000ULL); 359 360 memory_region_init_alias(&s->iomem_p4, NULL, "timer-p4", 361 &s->iomem, 0, 0x1000); 362 memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4); 363 364 memory_region_init_alias(&s->iomem_a7, NULL, "timer-a7", 365 &s->iomem, 0, 0x1000); 366 memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7); 367 /* ??? Save/restore. */ 368 } 369