1 /* 2 * SuperH Timer modules. 3 * 4 * Copyright (c) 2007 Magnus Damm 5 * Based on arm_timer.c by Paul Brook 6 * Copyright (c) 2005-2006 CodeSourcery. 7 * 8 * This code is licensed under the GPL. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "exec/memory.h" 13 #include "hw/hw.h" 14 #include "hw/irq.h" 15 #include "hw/sh4/sh.h" 16 #include "hw/timer/tmu012.h" 17 #include "hw/ptimer.h" 18 #include "trace.h" 19 20 #define TIMER_TCR_TPSC (7 << 0) 21 #define TIMER_TCR_CKEG (3 << 3) 22 #define TIMER_TCR_UNIE (1 << 5) 23 #define TIMER_TCR_ICPE (3 << 6) 24 #define TIMER_TCR_UNF (1 << 8) 25 #define TIMER_TCR_ICPF (1 << 9) 26 #define TIMER_TCR_RESERVED (0x3f << 10) 27 28 #define TIMER_FEAT_CAPT (1 << 0) 29 #define TIMER_FEAT_EXTCLK (1 << 1) 30 31 #define OFFSET_TCOR 0 32 #define OFFSET_TCNT 1 33 #define OFFSET_TCR 2 34 #define OFFSET_TCPR 3 35 36 typedef struct { 37 ptimer_state *timer; 38 uint32_t tcnt; 39 uint32_t tcor; 40 uint32_t tcr; 41 uint32_t tcpr; 42 int freq; 43 int int_level; 44 int old_level; 45 int feat; 46 int enabled; 47 qemu_irq irq; 48 } SHTimerState; 49 50 /* Check all active timers, and schedule the next timer interrupt. */ 51 52 static void sh_timer_update(SHTimerState *s) 53 { 54 int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE); 55 56 if (new_level != s->old_level) { 57 qemu_set_irq(s->irq, new_level); 58 } 59 s->old_level = s->int_level; 60 s->int_level = new_level; 61 } 62 63 static uint32_t sh_timer_read(void *opaque, hwaddr offset) 64 { 65 SHTimerState *s = opaque; 66 67 switch (offset >> 2) { 68 case OFFSET_TCOR: 69 return s->tcor; 70 case OFFSET_TCNT: 71 return ptimer_get_count(s->timer); 72 case OFFSET_TCR: 73 return s->tcr | (s->int_level ? TIMER_TCR_UNF : 0); 74 case OFFSET_TCPR: 75 if (s->feat & TIMER_FEAT_CAPT) { 76 return s->tcpr; 77 } 78 /* fall through */ 79 default: 80 hw_error("sh_timer_read: Bad offset %x\n", (int)offset); 81 return 0; 82 } 83 } 84 85 static void sh_timer_write(void *opaque, hwaddr offset, uint32_t value) 86 { 87 SHTimerState *s = opaque; 88 int freq; 89 90 switch (offset >> 2) { 91 case OFFSET_TCOR: 92 s->tcor = value; 93 ptimer_transaction_begin(s->timer); 94 ptimer_set_limit(s->timer, s->tcor, 0); 95 ptimer_transaction_commit(s->timer); 96 break; 97 case OFFSET_TCNT: 98 s->tcnt = value; 99 ptimer_transaction_begin(s->timer); 100 ptimer_set_count(s->timer, s->tcnt); 101 ptimer_transaction_commit(s->timer); 102 break; 103 case OFFSET_TCR: 104 ptimer_transaction_begin(s->timer); 105 if (s->enabled) { 106 /* 107 * Pause the timer if it is running. This may cause some inaccuracy 108 * due to rounding, but avoids a whole lot of other messiness 109 */ 110 ptimer_stop(s->timer); 111 } 112 freq = s->freq; 113 /* ??? Need to recalculate expiry time after changing divisor. */ 114 switch (value & TIMER_TCR_TPSC) { 115 case 0: 116 freq >>= 2; 117 break; 118 case 1: 119 freq >>= 4; 120 break; 121 case 2: 122 freq >>= 6; 123 break; 124 case 3: 125 freq >>= 8; 126 break; 127 case 4: 128 freq >>= 10; 129 break; 130 case 6: 131 case 7: 132 if (s->feat & TIMER_FEAT_EXTCLK) { 133 break; 134 } 135 /* fallthrough */ 136 default: 137 hw_error("sh_timer_write: Reserved TPSC value\n"); 138 } 139 switch ((value & TIMER_TCR_CKEG) >> 3) { 140 case 0: 141 break; 142 case 1: 143 case 2: 144 case 3: 145 if (s->feat & TIMER_FEAT_EXTCLK) { 146 break; 147 } 148 /* fallthrough */ 149 default: 150 hw_error("sh_timer_write: Reserved CKEG value\n"); 151 } 152 switch ((value & TIMER_TCR_ICPE) >> 6) { 153 case 0: 154 break; 155 case 2: 156 case 3: 157 if (s->feat & TIMER_FEAT_CAPT) { 158 break; 159 } 160 /* fallthrough */ 161 default: 162 hw_error("sh_timer_write: Reserved ICPE value\n"); 163 } 164 if ((value & TIMER_TCR_UNF) == 0) { 165 s->int_level = 0; 166 } 167 168 value &= ~TIMER_TCR_UNF; 169 170 if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT))) { 171 hw_error("sh_timer_write: Reserved ICPF value\n"); 172 } 173 174 value &= ~TIMER_TCR_ICPF; /* capture not supported */ 175 176 if (value & TIMER_TCR_RESERVED) { 177 hw_error("sh_timer_write: Reserved TCR bits set\n"); 178 } 179 s->tcr = value; 180 ptimer_set_limit(s->timer, s->tcor, 0); 181 ptimer_set_freq(s->timer, freq); 182 if (s->enabled) { 183 /* Restart the timer if still enabled. */ 184 ptimer_run(s->timer, 0); 185 } 186 ptimer_transaction_commit(s->timer); 187 break; 188 case OFFSET_TCPR: 189 if (s->feat & TIMER_FEAT_CAPT) { 190 s->tcpr = value; 191 break; 192 } 193 /* fallthrough */ 194 default: 195 hw_error("sh_timer_write: Bad offset %x\n", (int)offset); 196 } 197 sh_timer_update(s); 198 } 199 200 static void sh_timer_start_stop(void *opaque, int enable) 201 { 202 SHTimerState *s = opaque; 203 204 trace_sh_timer_start_stop(enable, s->enabled); 205 ptimer_transaction_begin(s->timer); 206 if (s->enabled && !enable) { 207 ptimer_stop(s->timer); 208 } 209 if (!s->enabled && enable) { 210 ptimer_run(s->timer, 0); 211 } 212 ptimer_transaction_commit(s->timer); 213 s->enabled = !!enable; 214 } 215 216 static void sh_timer_tick(void *opaque) 217 { 218 SHTimerState *s = opaque; 219 s->int_level = s->enabled; 220 sh_timer_update(s); 221 } 222 223 static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq) 224 { 225 SHTimerState *s; 226 227 s = g_malloc0(sizeof(*s)); 228 s->freq = freq; 229 s->feat = feat; 230 s->tcor = 0xffffffff; 231 s->tcnt = 0xffffffff; 232 s->tcpr = 0xdeadbeef; 233 s->tcr = 0; 234 s->enabled = 0; 235 s->irq = irq; 236 237 s->timer = ptimer_init(sh_timer_tick, s, PTIMER_POLICY_DEFAULT); 238 239 sh_timer_write(s, OFFSET_TCOR >> 2, s->tcor); 240 sh_timer_write(s, OFFSET_TCNT >> 2, s->tcnt); 241 sh_timer_write(s, OFFSET_TCPR >> 2, s->tcpr); 242 sh_timer_write(s, OFFSET_TCR >> 2, s->tcpr); 243 /* ??? Save/restore. */ 244 return s; 245 } 246 247 typedef struct { 248 MemoryRegion iomem; 249 MemoryRegion iomem_p4; 250 MemoryRegion iomem_a7; 251 void *timer[3]; 252 int level[3]; 253 uint32_t tocr; 254 uint32_t tstr; 255 int feat; 256 } tmu012_state; 257 258 static uint64_t tmu012_read(void *opaque, hwaddr offset, unsigned size) 259 { 260 tmu012_state *s = opaque; 261 262 trace_sh_timer_read(offset); 263 if (offset >= 0x20) { 264 if (!(s->feat & TMU012_FEAT_3CHAN)) { 265 hw_error("tmu012_write: Bad channel offset %x\n", (int)offset); 266 } 267 return sh_timer_read(s->timer[2], offset - 0x20); 268 } 269 270 if (offset >= 0x14) { 271 return sh_timer_read(s->timer[1], offset - 0x14); 272 } 273 if (offset >= 0x08) { 274 return sh_timer_read(s->timer[0], offset - 0x08); 275 } 276 if (offset == 4) { 277 return s->tstr; 278 } 279 if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) { 280 return s->tocr; 281 } 282 283 hw_error("tmu012_write: Bad offset %x\n", (int)offset); 284 return 0; 285 } 286 287 static void tmu012_write(void *opaque, hwaddr offset, 288 uint64_t value, unsigned size) 289 { 290 tmu012_state *s = opaque; 291 292 trace_sh_timer_write(offset, value); 293 if (offset >= 0x20) { 294 if (!(s->feat & TMU012_FEAT_3CHAN)) { 295 hw_error("tmu012_write: Bad channel offset %x\n", (int)offset); 296 } 297 sh_timer_write(s->timer[2], offset - 0x20, value); 298 return; 299 } 300 301 if (offset >= 0x14) { 302 sh_timer_write(s->timer[1], offset - 0x14, value); 303 return; 304 } 305 306 if (offset >= 0x08) { 307 sh_timer_write(s->timer[0], offset - 0x08, value); 308 return; 309 } 310 311 if (offset == 4) { 312 sh_timer_start_stop(s->timer[0], value & (1 << 0)); 313 sh_timer_start_stop(s->timer[1], value & (1 << 1)); 314 if (s->feat & TMU012_FEAT_3CHAN) { 315 sh_timer_start_stop(s->timer[2], value & (1 << 2)); 316 } else { 317 if (value & (1 << 2)) { 318 hw_error("tmu012_write: Bad channel\n"); 319 } 320 } 321 322 s->tstr = value; 323 return; 324 } 325 326 if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) { 327 s->tocr = value & (1 << 0); 328 } 329 } 330 331 static const MemoryRegionOps tmu012_ops = { 332 .read = tmu012_read, 333 .write = tmu012_write, 334 .endianness = DEVICE_NATIVE_ENDIAN, 335 }; 336 337 void tmu012_init(MemoryRegion *sysmem, hwaddr base, int feat, uint32_t freq, 338 qemu_irq ch0_irq, qemu_irq ch1_irq, 339 qemu_irq ch2_irq0, qemu_irq ch2_irq1) 340 { 341 tmu012_state *s; 342 int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0; 343 344 s = g_malloc0(sizeof(*s)); 345 s->feat = feat; 346 s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq); 347 s->timer[1] = sh_timer_init(freq, timer_feat, ch1_irq); 348 if (feat & TMU012_FEAT_3CHAN) { 349 s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT, 350 ch2_irq0); /* ch2_irq1 not supported */ 351 } 352 353 memory_region_init_io(&s->iomem, NULL, &tmu012_ops, s, "timer", 0x30); 354 355 memory_region_init_alias(&s->iomem_p4, NULL, "timer-p4", 356 &s->iomem, 0, memory_region_size(&s->iomem)); 357 memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4); 358 359 memory_region_init_alias(&s->iomem_a7, NULL, "timer-a7", 360 &s->iomem, 0, memory_region_size(&s->iomem)); 361 memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7); 362 /* ??? Save/restore. */ 363 } 364