1 /* 2 * SuperH Timer modules. 3 * 4 * Copyright (c) 2007 Magnus Damm 5 * Based on arm_timer.c by Paul Brook 6 * Copyright (c) 2005-2006 CodeSourcery. 7 * 8 * This code is licensed under the GPL. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "exec/memory.h" 13 #include "hw/hw.h" 14 #include "hw/irq.h" 15 #include "hw/sh4/sh.h" 16 #include "hw/timer/tmu012.h" 17 #include "hw/ptimer.h" 18 #include "trace.h" 19 20 #define TIMER_TCR_TPSC (7 << 0) 21 #define TIMER_TCR_CKEG (3 << 3) 22 #define TIMER_TCR_UNIE (1 << 5) 23 #define TIMER_TCR_ICPE (3 << 6) 24 #define TIMER_TCR_UNF (1 << 8) 25 #define TIMER_TCR_ICPF (1 << 9) 26 #define TIMER_TCR_RESERVED (0x3f << 10) 27 28 #define TIMER_FEAT_CAPT (1 << 0) 29 #define TIMER_FEAT_EXTCLK (1 << 1) 30 31 #define OFFSET_TCOR 0 32 #define OFFSET_TCNT 1 33 #define OFFSET_TCR 2 34 #define OFFSET_TCPR 3 35 36 typedef struct { 37 ptimer_state *timer; 38 uint32_t tcnt; 39 uint32_t tcor; 40 uint32_t tcr; 41 uint32_t tcpr; 42 int freq; 43 int int_level; 44 int old_level; 45 int feat; 46 int enabled; 47 qemu_irq irq; 48 } SHTimerState; 49 50 /* Check all active timers, and schedule the next timer interrupt. */ 51 52 static void sh_timer_update(SHTimerState *s) 53 { 54 int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE); 55 56 if (new_level != s->old_level) { 57 qemu_set_irq(s->irq, new_level); 58 } 59 s->old_level = s->int_level; 60 s->int_level = new_level; 61 } 62 63 static uint32_t sh_timer_read(void *opaque, hwaddr offset) 64 { 65 SHTimerState *s = opaque; 66 67 switch (offset >> 2) { 68 case OFFSET_TCOR: 69 return s->tcor; 70 case OFFSET_TCNT: 71 return ptimer_get_count(s->timer); 72 case OFFSET_TCR: 73 return s->tcr | (s->int_level ? TIMER_TCR_UNF : 0); 74 case OFFSET_TCPR: 75 if (s->feat & TIMER_FEAT_CAPT) { 76 return s->tcpr; 77 } 78 /* fall through */ 79 default: 80 hw_error("sh_timer_read: Bad offset %x\n", (int)offset); 81 return 0; 82 } 83 } 84 85 static void sh_timer_write(void *opaque, hwaddr offset, 86 uint32_t value) 87 { 88 SHTimerState *s = opaque; 89 int freq; 90 91 switch (offset >> 2) { 92 case OFFSET_TCOR: 93 s->tcor = value; 94 ptimer_transaction_begin(s->timer); 95 ptimer_set_limit(s->timer, s->tcor, 0); 96 ptimer_transaction_commit(s->timer); 97 break; 98 case OFFSET_TCNT: 99 s->tcnt = value; 100 ptimer_transaction_begin(s->timer); 101 ptimer_set_count(s->timer, s->tcnt); 102 ptimer_transaction_commit(s->timer); 103 break; 104 case OFFSET_TCR: 105 ptimer_transaction_begin(s->timer); 106 if (s->enabled) { 107 /* 108 * Pause the timer if it is running. This may cause some inaccuracy 109 * due to rounding, but avoids a whole lot of other messiness 110 */ 111 ptimer_stop(s->timer); 112 } 113 freq = s->freq; 114 /* ??? Need to recalculate expiry time after changing divisor. */ 115 switch (value & TIMER_TCR_TPSC) { 116 case 0: 117 freq >>= 2; 118 break; 119 case 1: 120 freq >>= 4; 121 break; 122 case 2: 123 freq >>= 6; 124 break; 125 case 3: 126 freq >>= 8; 127 break; 128 case 4: 129 freq >>= 10; 130 break; 131 case 6: 132 case 7: 133 if (s->feat & TIMER_FEAT_EXTCLK) { 134 break; 135 } 136 /* fallthrough */ 137 default: 138 hw_error("sh_timer_write: Reserved TPSC value\n"); 139 } 140 switch ((value & TIMER_TCR_CKEG) >> 3) { 141 case 0: 142 break; 143 case 1: 144 case 2: 145 case 3: 146 if (s->feat & TIMER_FEAT_EXTCLK) { 147 break; 148 } 149 /* fallthrough */ 150 default: 151 hw_error("sh_timer_write: Reserved CKEG value\n"); 152 } 153 switch ((value & TIMER_TCR_ICPE) >> 6) { 154 case 0: 155 break; 156 case 2: 157 case 3: 158 if (s->feat & TIMER_FEAT_CAPT) { 159 break; 160 } 161 /* fallthrough */ 162 default: 163 hw_error("sh_timer_write: Reserved ICPE value\n"); 164 } 165 if ((value & TIMER_TCR_UNF) == 0) { 166 s->int_level = 0; 167 } 168 169 value &= ~TIMER_TCR_UNF; 170 171 if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT))) { 172 hw_error("sh_timer_write: Reserved ICPF value\n"); 173 } 174 175 value &= ~TIMER_TCR_ICPF; /* capture not supported */ 176 177 if (value & TIMER_TCR_RESERVED) { 178 hw_error("sh_timer_write: Reserved TCR bits set\n"); 179 } 180 s->tcr = value; 181 ptimer_set_limit(s->timer, s->tcor, 0); 182 ptimer_set_freq(s->timer, freq); 183 if (s->enabled) { 184 /* Restart the timer if still enabled. */ 185 ptimer_run(s->timer, 0); 186 } 187 ptimer_transaction_commit(s->timer); 188 break; 189 case OFFSET_TCPR: 190 if (s->feat & TIMER_FEAT_CAPT) { 191 s->tcpr = value; 192 break; 193 } 194 /* fallthrough */ 195 default: 196 hw_error("sh_timer_write: Bad offset %x\n", (int)offset); 197 } 198 sh_timer_update(s); 199 } 200 201 static void sh_timer_start_stop(void *opaque, int enable) 202 { 203 SHTimerState *s = opaque; 204 205 trace_sh_timer_start_stop(enable, s->enabled); 206 ptimer_transaction_begin(s->timer); 207 if (s->enabled && !enable) { 208 ptimer_stop(s->timer); 209 } 210 if (!s->enabled && enable) { 211 ptimer_run(s->timer, 0); 212 } 213 ptimer_transaction_commit(s->timer); 214 s->enabled = !!enable; 215 } 216 217 static void sh_timer_tick(void *opaque) 218 { 219 SHTimerState *s = opaque; 220 s->int_level = s->enabled; 221 sh_timer_update(s); 222 } 223 224 static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq) 225 { 226 SHTimerState *s; 227 228 s = g_malloc0(sizeof(*s)); 229 s->freq = freq; 230 s->feat = feat; 231 s->tcor = 0xffffffff; 232 s->tcnt = 0xffffffff; 233 s->tcpr = 0xdeadbeef; 234 s->tcr = 0; 235 s->enabled = 0; 236 s->irq = irq; 237 238 s->timer = ptimer_init(sh_timer_tick, s, PTIMER_POLICY_DEFAULT); 239 240 sh_timer_write(s, OFFSET_TCOR >> 2, s->tcor); 241 sh_timer_write(s, OFFSET_TCNT >> 2, s->tcnt); 242 sh_timer_write(s, OFFSET_TCPR >> 2, s->tcpr); 243 sh_timer_write(s, OFFSET_TCR >> 2, s->tcpr); 244 /* ??? Save/restore. */ 245 return s; 246 } 247 248 typedef struct { 249 MemoryRegion iomem; 250 MemoryRegion iomem_p4; 251 MemoryRegion iomem_a7; 252 void *timer[3]; 253 int level[3]; 254 uint32_t tocr; 255 uint32_t tstr; 256 int feat; 257 } tmu012_state; 258 259 static uint64_t tmu012_read(void *opaque, hwaddr offset, 260 unsigned size) 261 { 262 tmu012_state *s = opaque; 263 264 trace_sh_timer_read(offset); 265 if (offset >= 0x20) { 266 if (!(s->feat & TMU012_FEAT_3CHAN)) { 267 hw_error("tmu012_write: Bad channel offset %x\n", (int)offset); 268 } 269 return sh_timer_read(s->timer[2], offset - 0x20); 270 } 271 272 if (offset >= 0x14) { 273 return sh_timer_read(s->timer[1], offset - 0x14); 274 } 275 if (offset >= 0x08) { 276 return sh_timer_read(s->timer[0], offset - 0x08); 277 } 278 if (offset == 4) { 279 return s->tstr; 280 } 281 if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) { 282 return s->tocr; 283 } 284 285 hw_error("tmu012_write: Bad offset %x\n", (int)offset); 286 return 0; 287 } 288 289 static void tmu012_write(void *opaque, hwaddr offset, 290 uint64_t value, unsigned size) 291 { 292 tmu012_state *s = opaque; 293 294 trace_sh_timer_write(offset, value); 295 if (offset >= 0x20) { 296 if (!(s->feat & TMU012_FEAT_3CHAN)) { 297 hw_error("tmu012_write: Bad channel offset %x\n", (int)offset); 298 } 299 sh_timer_write(s->timer[2], offset - 0x20, value); 300 return; 301 } 302 303 if (offset >= 0x14) { 304 sh_timer_write(s->timer[1], offset - 0x14, value); 305 return; 306 } 307 308 if (offset >= 0x08) { 309 sh_timer_write(s->timer[0], offset - 0x08, value); 310 return; 311 } 312 313 if (offset == 4) { 314 sh_timer_start_stop(s->timer[0], value & (1 << 0)); 315 sh_timer_start_stop(s->timer[1], value & (1 << 1)); 316 if (s->feat & TMU012_FEAT_3CHAN) { 317 sh_timer_start_stop(s->timer[2], value & (1 << 2)); 318 } else { 319 if (value & (1 << 2)) { 320 hw_error("tmu012_write: Bad channel\n"); 321 } 322 } 323 324 s->tstr = value; 325 return; 326 } 327 328 if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) { 329 s->tocr = value & (1 << 0); 330 } 331 } 332 333 static const MemoryRegionOps tmu012_ops = { 334 .read = tmu012_read, 335 .write = tmu012_write, 336 .endianness = DEVICE_NATIVE_ENDIAN, 337 }; 338 339 void tmu012_init(MemoryRegion *sysmem, hwaddr base, 340 int feat, uint32_t freq, 341 qemu_irq ch0_irq, qemu_irq ch1_irq, 342 qemu_irq ch2_irq0, qemu_irq ch2_irq1) 343 { 344 tmu012_state *s; 345 int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0; 346 347 s = g_malloc0(sizeof(*s)); 348 s->feat = feat; 349 s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq); 350 s->timer[1] = sh_timer_init(freq, timer_feat, ch1_irq); 351 if (feat & TMU012_FEAT_3CHAN) { 352 s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT, 353 ch2_irq0); /* ch2_irq1 not supported */ 354 } 355 356 memory_region_init_io(&s->iomem, NULL, &tmu012_ops, s, 357 "timer", 0x100000000ULL); 358 359 memory_region_init_alias(&s->iomem_p4, NULL, "timer-p4", 360 &s->iomem, 0, 0x1000); 361 memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4); 362 363 memory_region_init_alias(&s->iomem_a7, NULL, "timer-a7", 364 &s->iomem, 0, 0x1000); 365 memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7); 366 /* ??? Save/restore. */ 367 } 368