1 /* 2 * TI OMAP2 general purpose timers emulation. 3 * 4 * Copyright (C) 2007-2008 Nokia Corporation 5 * Written by Andrzej Zaborowski <andrew@openedhand.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 or 10 * (at your option) any later version of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/hw.h" 23 #include "hw/irq.h" 24 #include "qemu/timer.h" 25 #include "hw/arm/omap.h" 26 27 /* GP timers */ 28 struct omap_gp_timer_s { 29 MemoryRegion iomem; 30 qemu_irq irq; 31 qemu_irq wkup; 32 qemu_irq in; 33 qemu_irq out; 34 omap_clk clk; 35 QEMUTimer *timer; 36 QEMUTimer *match; 37 struct omap_target_agent_s *ta; 38 39 int in_val; 40 int out_val; 41 int64_t time; 42 int64_t rate; 43 int64_t ticks_per_sec; 44 45 int16_t config; 46 int status; 47 int it_ena; 48 int wu_ena; 49 int enable; 50 int inout; 51 int capt2; 52 int pt; 53 enum { 54 gpt_trigger_none, gpt_trigger_overflow, gpt_trigger_both 55 } trigger; 56 enum { 57 gpt_capture_none, gpt_capture_rising, 58 gpt_capture_falling, gpt_capture_both 59 } capture; 60 int scpwm; 61 int ce; 62 int pre; 63 int ptv; 64 int ar; 65 int st; 66 int posted; 67 uint32_t val; 68 uint32_t load_val; 69 uint32_t capture_val[2]; 70 uint32_t match_val; 71 int capt_num; 72 73 uint16_t writeh; /* LSB */ 74 uint16_t readh; /* MSB */ 75 }; 76 77 #define GPT_TCAR_IT (1 << 2) 78 #define GPT_OVF_IT (1 << 1) 79 #define GPT_MAT_IT (1 << 0) 80 81 static inline void omap_gp_timer_intr(struct omap_gp_timer_s *timer, int it) 82 { 83 if (timer->it_ena & it) { 84 if (!timer->status) 85 qemu_irq_raise(timer->irq); 86 87 timer->status |= it; 88 /* Or are the status bits set even when masked? 89 * i.e. is masking applied before or after the status register? */ 90 } 91 92 if (timer->wu_ena & it) 93 qemu_irq_pulse(timer->wkup); 94 } 95 96 static inline void omap_gp_timer_out(struct omap_gp_timer_s *timer, int level) 97 { 98 if (!timer->inout && timer->out_val != level) { 99 timer->out_val = level; 100 qemu_set_irq(timer->out, level); 101 } 102 } 103 104 static inline uint32_t omap_gp_timer_read(struct omap_gp_timer_s *timer) 105 { 106 uint64_t distance; 107 108 if (timer->st && timer->rate) { 109 distance = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->time; 110 distance = muldiv64(distance, timer->rate, timer->ticks_per_sec); 111 112 if (distance >= 0xffffffff - timer->val) 113 return 0xffffffff; 114 else 115 return timer->val + distance; 116 } else 117 return timer->val; 118 } 119 120 static inline void omap_gp_timer_sync(struct omap_gp_timer_s *timer) 121 { 122 if (timer->st) { 123 timer->val = omap_gp_timer_read(timer); 124 timer->time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 125 } 126 } 127 128 static inline void omap_gp_timer_update(struct omap_gp_timer_s *timer) 129 { 130 int64_t expires, matches; 131 132 if (timer->st && timer->rate) { 133 expires = muldiv64(0x100000000ll - timer->val, 134 timer->ticks_per_sec, timer->rate); 135 timer_mod(timer->timer, timer->time + expires); 136 137 if (timer->ce && timer->match_val >= timer->val) { 138 matches = muldiv64(timer->ticks_per_sec, 139 timer->match_val - timer->val, timer->rate); 140 timer_mod(timer->match, timer->time + matches); 141 } else 142 timer_del(timer->match); 143 } else { 144 timer_del(timer->timer); 145 timer_del(timer->match); 146 omap_gp_timer_out(timer, timer->scpwm); 147 } 148 } 149 150 static inline void omap_gp_timer_trigger(struct omap_gp_timer_s *timer) 151 { 152 if (timer->pt) 153 /* TODO in overflow-and-match mode if the first event to 154 * occur is the match, don't toggle. */ 155 omap_gp_timer_out(timer, !timer->out_val); 156 else 157 /* TODO inverted pulse on timer->out_val == 1? */ 158 qemu_irq_pulse(timer->out); 159 } 160 161 static void omap_gp_timer_tick(void *opaque) 162 { 163 struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque; 164 165 if (!timer->ar) { 166 timer->st = 0; 167 timer->val = 0; 168 } else { 169 timer->val = timer->load_val; 170 timer->time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 171 } 172 173 if (timer->trigger == gpt_trigger_overflow || 174 timer->trigger == gpt_trigger_both) 175 omap_gp_timer_trigger(timer); 176 177 omap_gp_timer_intr(timer, GPT_OVF_IT); 178 omap_gp_timer_update(timer); 179 } 180 181 static void omap_gp_timer_match(void *opaque) 182 { 183 struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque; 184 185 if (timer->trigger == gpt_trigger_both) 186 omap_gp_timer_trigger(timer); 187 188 omap_gp_timer_intr(timer, GPT_MAT_IT); 189 } 190 191 static void omap_gp_timer_input(void *opaque, int line, int on) 192 { 193 struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; 194 int trigger; 195 196 switch (s->capture) { 197 default: 198 case gpt_capture_none: 199 trigger = 0; 200 break; 201 case gpt_capture_rising: 202 trigger = !s->in_val && on; 203 break; 204 case gpt_capture_falling: 205 trigger = s->in_val && !on; 206 break; 207 case gpt_capture_both: 208 trigger = (s->in_val == !on); 209 break; 210 } 211 s->in_val = on; 212 213 if (s->inout && trigger && s->capt_num < 2) { 214 s->capture_val[s->capt_num] = omap_gp_timer_read(s); 215 216 if (s->capt2 == s->capt_num ++) 217 omap_gp_timer_intr(s, GPT_TCAR_IT); 218 } 219 } 220 221 static void omap_gp_timer_clk_update(void *opaque, int line, int on) 222 { 223 struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque; 224 225 omap_gp_timer_sync(timer); 226 timer->rate = on ? omap_clk_getrate(timer->clk) : 0; 227 omap_gp_timer_update(timer); 228 } 229 230 static void omap_gp_timer_clk_setup(struct omap_gp_timer_s *timer) 231 { 232 omap_clk_adduser(timer->clk, 233 qemu_allocate_irq(omap_gp_timer_clk_update, timer, 0)); 234 timer->rate = omap_clk_getrate(timer->clk); 235 } 236 237 void omap_gp_timer_reset(struct omap_gp_timer_s *s) 238 { 239 s->config = 0x000; 240 s->status = 0; 241 s->it_ena = 0; 242 s->wu_ena = 0; 243 s->inout = 0; 244 s->capt2 = 0; 245 s->capt_num = 0; 246 s->pt = 0; 247 s->trigger = gpt_trigger_none; 248 s->capture = gpt_capture_none; 249 s->scpwm = 0; 250 s->ce = 0; 251 s->pre = 0; 252 s->ptv = 0; 253 s->ar = 0; 254 s->st = 0; 255 s->posted = 1; 256 s->val = 0x00000000; 257 s->load_val = 0x00000000; 258 s->capture_val[0] = 0x00000000; 259 s->capture_val[1] = 0x00000000; 260 s->match_val = 0x00000000; 261 omap_gp_timer_update(s); 262 } 263 264 static uint32_t omap_gp_timer_readw(void *opaque, hwaddr addr) 265 { 266 struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; 267 268 switch (addr) { 269 case 0x00: /* TIDR */ 270 return 0x21; 271 272 case 0x10: /* TIOCP_CFG */ 273 return s->config; 274 275 case 0x14: /* TISTAT */ 276 /* ??? When's this bit reset? */ 277 return 1; /* RESETDONE */ 278 279 case 0x18: /* TISR */ 280 return s->status; 281 282 case 0x1c: /* TIER */ 283 return s->it_ena; 284 285 case 0x20: /* TWER */ 286 return s->wu_ena; 287 288 case 0x24: /* TCLR */ 289 return (s->inout << 14) | 290 (s->capt2 << 13) | 291 (s->pt << 12) | 292 (s->trigger << 10) | 293 (s->capture << 8) | 294 (s->scpwm << 7) | 295 (s->ce << 6) | 296 (s->pre << 5) | 297 (s->ptv << 2) | 298 (s->ar << 1) | 299 (s->st << 0); 300 301 case 0x28: /* TCRR */ 302 return omap_gp_timer_read(s); 303 304 case 0x2c: /* TLDR */ 305 return s->load_val; 306 307 case 0x30: /* TTGR */ 308 return 0xffffffff; 309 310 case 0x34: /* TWPS */ 311 return 0x00000000; /* No posted writes pending. */ 312 313 case 0x38: /* TMAR */ 314 return s->match_val; 315 316 case 0x3c: /* TCAR1 */ 317 return s->capture_val[0]; 318 319 case 0x40: /* TSICR */ 320 return s->posted << 2; 321 322 case 0x44: /* TCAR2 */ 323 return s->capture_val[1]; 324 } 325 326 OMAP_BAD_REG(addr); 327 return 0; 328 } 329 330 static uint32_t omap_gp_timer_readh(void *opaque, hwaddr addr) 331 { 332 struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; 333 uint32_t ret; 334 335 if (addr & 2) 336 return s->readh; 337 else { 338 ret = omap_gp_timer_readw(opaque, addr); 339 s->readh = ret >> 16; 340 return ret & 0xffff; 341 } 342 } 343 344 static void omap_gp_timer_write(void *opaque, hwaddr addr, 345 uint32_t value) 346 { 347 struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; 348 349 switch (addr) { 350 case 0x00: /* TIDR */ 351 case 0x14: /* TISTAT */ 352 case 0x34: /* TWPS */ 353 case 0x3c: /* TCAR1 */ 354 case 0x44: /* TCAR2 */ 355 OMAP_RO_REG(addr); 356 break; 357 358 case 0x10: /* TIOCP_CFG */ 359 s->config = value & 0x33d; 360 if (((value >> 3) & 3) == 3) /* IDLEMODE */ 361 fprintf(stderr, "%s: illegal IDLEMODE value in TIOCP_CFG\n", 362 __func__); 363 if (value & 2) /* SOFTRESET */ 364 omap_gp_timer_reset(s); 365 break; 366 367 case 0x18: /* TISR */ 368 if (value & GPT_TCAR_IT) 369 s->capt_num = 0; 370 if (s->status && !(s->status &= ~value)) 371 qemu_irq_lower(s->irq); 372 break; 373 374 case 0x1c: /* TIER */ 375 s->it_ena = value & 7; 376 break; 377 378 case 0x20: /* TWER */ 379 s->wu_ena = value & 7; 380 break; 381 382 case 0x24: /* TCLR */ 383 omap_gp_timer_sync(s); 384 s->inout = (value >> 14) & 1; 385 s->capt2 = (value >> 13) & 1; 386 s->pt = (value >> 12) & 1; 387 s->trigger = (value >> 10) & 3; 388 if (s->capture == gpt_capture_none && 389 ((value >> 8) & 3) != gpt_capture_none) 390 s->capt_num = 0; 391 s->capture = (value >> 8) & 3; 392 s->scpwm = (value >> 7) & 1; 393 s->ce = (value >> 6) & 1; 394 s->pre = (value >> 5) & 1; 395 s->ptv = (value >> 2) & 7; 396 s->ar = (value >> 1) & 1; 397 s->st = (value >> 0) & 1; 398 if (s->inout && s->trigger != gpt_trigger_none) 399 fprintf(stderr, "%s: GP timer pin must be an output " 400 "for this trigger mode\n", __func__); 401 if (!s->inout && s->capture != gpt_capture_none) 402 fprintf(stderr, "%s: GP timer pin must be an input " 403 "for this capture mode\n", __func__); 404 if (s->trigger == gpt_trigger_none) 405 omap_gp_timer_out(s, s->scpwm); 406 /* TODO: make sure this doesn't overflow 32-bits */ 407 s->ticks_per_sec = NANOSECONDS_PER_SECOND << (s->pre ? s->ptv + 1 : 0); 408 omap_gp_timer_update(s); 409 break; 410 411 case 0x28: /* TCRR */ 412 s->time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 413 s->val = value; 414 omap_gp_timer_update(s); 415 break; 416 417 case 0x2c: /* TLDR */ 418 s->load_val = value; 419 break; 420 421 case 0x30: /* TTGR */ 422 s->time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 423 s->val = s->load_val; 424 omap_gp_timer_update(s); 425 break; 426 427 case 0x38: /* TMAR */ 428 omap_gp_timer_sync(s); 429 s->match_val = value; 430 omap_gp_timer_update(s); 431 break; 432 433 case 0x40: /* TSICR */ 434 s->posted = (value >> 2) & 1; 435 if (value & 2) /* How much exactly are we supposed to reset? */ 436 omap_gp_timer_reset(s); 437 break; 438 439 default: 440 OMAP_BAD_REG(addr); 441 } 442 } 443 444 static void omap_gp_timer_writeh(void *opaque, hwaddr addr, 445 uint32_t value) 446 { 447 struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; 448 449 if (addr & 2) 450 omap_gp_timer_write(opaque, addr, (value << 16) | s->writeh); 451 else 452 s->writeh = (uint16_t) value; 453 } 454 455 static uint64_t omap_gp_timer_readfn(void *opaque, hwaddr addr, 456 unsigned size) 457 { 458 switch (size) { 459 case 1: 460 return omap_badwidth_read32(opaque, addr); 461 case 2: 462 return omap_gp_timer_readh(opaque, addr); 463 case 4: 464 return omap_gp_timer_readw(opaque, addr); 465 default: 466 g_assert_not_reached(); 467 } 468 } 469 470 static void omap_gp_timer_writefn(void *opaque, hwaddr addr, 471 uint64_t value, unsigned size) 472 { 473 switch (size) { 474 case 1: 475 omap_badwidth_write32(opaque, addr, value); 476 break; 477 case 2: 478 omap_gp_timer_writeh(opaque, addr, value); 479 break; 480 case 4: 481 omap_gp_timer_write(opaque, addr, value); 482 break; 483 default: 484 g_assert_not_reached(); 485 } 486 } 487 488 static const MemoryRegionOps omap_gp_timer_ops = { 489 .read = omap_gp_timer_readfn, 490 .write = omap_gp_timer_writefn, 491 .valid.min_access_size = 1, 492 .valid.max_access_size = 4, 493 .endianness = DEVICE_NATIVE_ENDIAN, 494 }; 495 496 struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta, 497 qemu_irq irq, omap_clk fclk, omap_clk iclk) 498 { 499 struct omap_gp_timer_s *s = g_new0(struct omap_gp_timer_s, 1); 500 501 s->ta = ta; 502 s->irq = irq; 503 s->clk = fclk; 504 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_gp_timer_tick, s); 505 s->match = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_gp_timer_match, s); 506 s->in = qemu_allocate_irq(omap_gp_timer_input, s, 0); 507 omap_gp_timer_reset(s); 508 omap_gp_timer_clk_setup(s); 509 510 memory_region_init_io(&s->iomem, NULL, &omap_gp_timer_ops, s, "omap.gptimer", 511 omap_l4_region_size(ta, 0)); 512 omap_l4_attach(ta, 0, &s->iomem); 513 514 return s; 515 } 516