13bd88451SPaolo Bonzini /*
23bd88451SPaolo Bonzini * TI OMAP2 general purpose timers emulation.
33bd88451SPaolo Bonzini *
43bd88451SPaolo Bonzini * Copyright (C) 2007-2008 Nokia Corporation
53bd88451SPaolo Bonzini * Written by Andrzej Zaborowski <andrew@openedhand.com>
63bd88451SPaolo Bonzini *
73bd88451SPaolo Bonzini * This program is free software; you can redistribute it and/or
83bd88451SPaolo Bonzini * modify it under the terms of the GNU General Public License as
93bd88451SPaolo Bonzini * published by the Free Software Foundation; either version 2 or
103bd88451SPaolo Bonzini * (at your option) any later version of the License.
113bd88451SPaolo Bonzini *
123bd88451SPaolo Bonzini * This program is distributed in the hope that it will be useful,
133bd88451SPaolo Bonzini * but WITHOUT ANY WARRANTY; without even the implied warranty of
143bd88451SPaolo Bonzini * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
153bd88451SPaolo Bonzini * GNU General Public License for more details.
163bd88451SPaolo Bonzini *
173bd88451SPaolo Bonzini * You should have received a copy of the GNU General Public License along
183bd88451SPaolo Bonzini * with this program; if not, see <http://www.gnu.org/licenses/>.
193bd88451SPaolo Bonzini */
2064552b6bSMarkus Armbruster
21282bc81eSPeter Maydell #include "qemu/osdep.h"
2264552b6bSMarkus Armbruster #include "hw/irq.h"
233bd88451SPaolo Bonzini #include "qemu/timer.h"
243bd88451SPaolo Bonzini #include "hw/arm/omap.h"
253bd88451SPaolo Bonzini
263bd88451SPaolo Bonzini /* GP timers */
273bd88451SPaolo Bonzini struct omap_gp_timer_s {
283bd88451SPaolo Bonzini MemoryRegion iomem;
293bd88451SPaolo Bonzini qemu_irq irq;
303bd88451SPaolo Bonzini qemu_irq wkup;
313bd88451SPaolo Bonzini qemu_irq in;
323bd88451SPaolo Bonzini qemu_irq out;
333bd88451SPaolo Bonzini omap_clk clk;
343bd88451SPaolo Bonzini QEMUTimer *timer;
353bd88451SPaolo Bonzini QEMUTimer *match;
363bd88451SPaolo Bonzini struct omap_target_agent_s *ta;
373bd88451SPaolo Bonzini
383bd88451SPaolo Bonzini int in_val;
393bd88451SPaolo Bonzini int out_val;
403bd88451SPaolo Bonzini int64_t time;
413bd88451SPaolo Bonzini int64_t rate;
423bd88451SPaolo Bonzini int64_t ticks_per_sec;
433bd88451SPaolo Bonzini
443bd88451SPaolo Bonzini int16_t config;
453bd88451SPaolo Bonzini int status;
463bd88451SPaolo Bonzini int it_ena;
473bd88451SPaolo Bonzini int wu_ena;
483bd88451SPaolo Bonzini int enable;
493bd88451SPaolo Bonzini int inout;
503bd88451SPaolo Bonzini int capt2;
513bd88451SPaolo Bonzini int pt;
523bd88451SPaolo Bonzini enum {
533bd88451SPaolo Bonzini gpt_trigger_none, gpt_trigger_overflow, gpt_trigger_both
543bd88451SPaolo Bonzini } trigger;
553bd88451SPaolo Bonzini enum {
563bd88451SPaolo Bonzini gpt_capture_none, gpt_capture_rising,
573bd88451SPaolo Bonzini gpt_capture_falling, gpt_capture_both
583bd88451SPaolo Bonzini } capture;
593bd88451SPaolo Bonzini int scpwm;
603bd88451SPaolo Bonzini int ce;
613bd88451SPaolo Bonzini int pre;
623bd88451SPaolo Bonzini int ptv;
633bd88451SPaolo Bonzini int ar;
643bd88451SPaolo Bonzini int st;
653bd88451SPaolo Bonzini int posted;
663bd88451SPaolo Bonzini uint32_t val;
673bd88451SPaolo Bonzini uint32_t load_val;
683bd88451SPaolo Bonzini uint32_t capture_val[2];
693bd88451SPaolo Bonzini uint32_t match_val;
703bd88451SPaolo Bonzini int capt_num;
713bd88451SPaolo Bonzini
723bd88451SPaolo Bonzini uint16_t writeh; /* LSB */
733bd88451SPaolo Bonzini uint16_t readh; /* MSB */
743bd88451SPaolo Bonzini };
753bd88451SPaolo Bonzini
763bd88451SPaolo Bonzini #define GPT_TCAR_IT (1 << 2)
773bd88451SPaolo Bonzini #define GPT_OVF_IT (1 << 1)
783bd88451SPaolo Bonzini #define GPT_MAT_IT (1 << 0)
793bd88451SPaolo Bonzini
omap_gp_timer_intr(struct omap_gp_timer_s * timer,int it)803bd88451SPaolo Bonzini static inline void omap_gp_timer_intr(struct omap_gp_timer_s *timer, int it)
813bd88451SPaolo Bonzini {
823bd88451SPaolo Bonzini if (timer->it_ena & it) {
833bd88451SPaolo Bonzini if (!timer->status)
843bd88451SPaolo Bonzini qemu_irq_raise(timer->irq);
853bd88451SPaolo Bonzini
863bd88451SPaolo Bonzini timer->status |= it;
873bd88451SPaolo Bonzini /* Or are the status bits set even when masked?
883bd88451SPaolo Bonzini * i.e. is masking applied before or after the status register? */
893bd88451SPaolo Bonzini }
903bd88451SPaolo Bonzini
913bd88451SPaolo Bonzini if (timer->wu_ena & it)
923bd88451SPaolo Bonzini qemu_irq_pulse(timer->wkup);
933bd88451SPaolo Bonzini }
943bd88451SPaolo Bonzini
omap_gp_timer_out(struct omap_gp_timer_s * timer,int level)953bd88451SPaolo Bonzini static inline void omap_gp_timer_out(struct omap_gp_timer_s *timer, int level)
963bd88451SPaolo Bonzini {
973bd88451SPaolo Bonzini if (!timer->inout && timer->out_val != level) {
983bd88451SPaolo Bonzini timer->out_val = level;
993bd88451SPaolo Bonzini qemu_set_irq(timer->out, level);
1003bd88451SPaolo Bonzini }
1013bd88451SPaolo Bonzini }
1023bd88451SPaolo Bonzini
omap_gp_timer_read(struct omap_gp_timer_s * timer)1033bd88451SPaolo Bonzini static inline uint32_t omap_gp_timer_read(struct omap_gp_timer_s *timer)
1043bd88451SPaolo Bonzini {
1053bd88451SPaolo Bonzini uint64_t distance;
1063bd88451SPaolo Bonzini
1073bd88451SPaolo Bonzini if (timer->st && timer->rate) {
108bc72ad67SAlex Bligh distance = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->time;
1093bd88451SPaolo Bonzini distance = muldiv64(distance, timer->rate, timer->ticks_per_sec);
1103bd88451SPaolo Bonzini
1113bd88451SPaolo Bonzini if (distance >= 0xffffffff - timer->val)
1123bd88451SPaolo Bonzini return 0xffffffff;
1133bd88451SPaolo Bonzini else
1143bd88451SPaolo Bonzini return timer->val + distance;
1153bd88451SPaolo Bonzini } else
1163bd88451SPaolo Bonzini return timer->val;
1173bd88451SPaolo Bonzini }
1183bd88451SPaolo Bonzini
omap_gp_timer_sync(struct omap_gp_timer_s * timer)1193bd88451SPaolo Bonzini static inline void omap_gp_timer_sync(struct omap_gp_timer_s *timer)
1203bd88451SPaolo Bonzini {
1213bd88451SPaolo Bonzini if (timer->st) {
1223bd88451SPaolo Bonzini timer->val = omap_gp_timer_read(timer);
123bc72ad67SAlex Bligh timer->time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1243bd88451SPaolo Bonzini }
1253bd88451SPaolo Bonzini }
1263bd88451SPaolo Bonzini
omap_gp_timer_update(struct omap_gp_timer_s * timer)1273bd88451SPaolo Bonzini static inline void omap_gp_timer_update(struct omap_gp_timer_s *timer)
1283bd88451SPaolo Bonzini {
1293bd88451SPaolo Bonzini int64_t expires, matches;
1303bd88451SPaolo Bonzini
1313bd88451SPaolo Bonzini if (timer->st && timer->rate) {
1323bd88451SPaolo Bonzini expires = muldiv64(0x100000000ll - timer->val,
1333bd88451SPaolo Bonzini timer->ticks_per_sec, timer->rate);
134bc72ad67SAlex Bligh timer_mod(timer->timer, timer->time + expires);
1353bd88451SPaolo Bonzini
1363bd88451SPaolo Bonzini if (timer->ce && timer->match_val >= timer->val) {
13734986862SLaurent Vivier matches = muldiv64(timer->ticks_per_sec,
13834986862SLaurent Vivier timer->match_val - timer->val, timer->rate);
139bc72ad67SAlex Bligh timer_mod(timer->match, timer->time + matches);
1403bd88451SPaolo Bonzini } else
141bc72ad67SAlex Bligh timer_del(timer->match);
1423bd88451SPaolo Bonzini } else {
143bc72ad67SAlex Bligh timer_del(timer->timer);
144bc72ad67SAlex Bligh timer_del(timer->match);
1453bd88451SPaolo Bonzini omap_gp_timer_out(timer, timer->scpwm);
1463bd88451SPaolo Bonzini }
1473bd88451SPaolo Bonzini }
1483bd88451SPaolo Bonzini
omap_gp_timer_trigger(struct omap_gp_timer_s * timer)1493bd88451SPaolo Bonzini static inline void omap_gp_timer_trigger(struct omap_gp_timer_s *timer)
1503bd88451SPaolo Bonzini {
1513bd88451SPaolo Bonzini if (timer->pt)
1523bd88451SPaolo Bonzini /* TODO in overflow-and-match mode if the first event to
1533bd88451SPaolo Bonzini * occur is the match, don't toggle. */
1543bd88451SPaolo Bonzini omap_gp_timer_out(timer, !timer->out_val);
1553bd88451SPaolo Bonzini else
1563bd88451SPaolo Bonzini /* TODO inverted pulse on timer->out_val == 1? */
1573bd88451SPaolo Bonzini qemu_irq_pulse(timer->out);
1583bd88451SPaolo Bonzini }
1593bd88451SPaolo Bonzini
omap_gp_timer_tick(void * opaque)1603bd88451SPaolo Bonzini static void omap_gp_timer_tick(void *opaque)
1613bd88451SPaolo Bonzini {
162*a75ed3c4SPhilippe Mathieu-Daudé struct omap_gp_timer_s *timer = opaque;
1633bd88451SPaolo Bonzini
1643bd88451SPaolo Bonzini if (!timer->ar) {
1653bd88451SPaolo Bonzini timer->st = 0;
1663bd88451SPaolo Bonzini timer->val = 0;
1673bd88451SPaolo Bonzini } else {
1683bd88451SPaolo Bonzini timer->val = timer->load_val;
169bc72ad67SAlex Bligh timer->time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1703bd88451SPaolo Bonzini }
1713bd88451SPaolo Bonzini
1723bd88451SPaolo Bonzini if (timer->trigger == gpt_trigger_overflow ||
1733bd88451SPaolo Bonzini timer->trigger == gpt_trigger_both)
1743bd88451SPaolo Bonzini omap_gp_timer_trigger(timer);
1753bd88451SPaolo Bonzini
1763bd88451SPaolo Bonzini omap_gp_timer_intr(timer, GPT_OVF_IT);
1773bd88451SPaolo Bonzini omap_gp_timer_update(timer);
1783bd88451SPaolo Bonzini }
1793bd88451SPaolo Bonzini
omap_gp_timer_match(void * opaque)1803bd88451SPaolo Bonzini static void omap_gp_timer_match(void *opaque)
1813bd88451SPaolo Bonzini {
182*a75ed3c4SPhilippe Mathieu-Daudé struct omap_gp_timer_s *timer = opaque;
1833bd88451SPaolo Bonzini
1843bd88451SPaolo Bonzini if (timer->trigger == gpt_trigger_both)
1853bd88451SPaolo Bonzini omap_gp_timer_trigger(timer);
1863bd88451SPaolo Bonzini
1873bd88451SPaolo Bonzini omap_gp_timer_intr(timer, GPT_MAT_IT);
1883bd88451SPaolo Bonzini }
1893bd88451SPaolo Bonzini
omap_gp_timer_input(void * opaque,int line,int on)1903bd88451SPaolo Bonzini static void omap_gp_timer_input(void *opaque, int line, int on)
1913bd88451SPaolo Bonzini {
192*a75ed3c4SPhilippe Mathieu-Daudé struct omap_gp_timer_s *s = opaque;
1933bd88451SPaolo Bonzini int trigger;
1943bd88451SPaolo Bonzini
1953bd88451SPaolo Bonzini switch (s->capture) {
1963bd88451SPaolo Bonzini default:
1973bd88451SPaolo Bonzini case gpt_capture_none:
1983bd88451SPaolo Bonzini trigger = 0;
1993bd88451SPaolo Bonzini break;
2003bd88451SPaolo Bonzini case gpt_capture_rising:
2013bd88451SPaolo Bonzini trigger = !s->in_val && on;
2023bd88451SPaolo Bonzini break;
2033bd88451SPaolo Bonzini case gpt_capture_falling:
2043bd88451SPaolo Bonzini trigger = s->in_val && !on;
2053bd88451SPaolo Bonzini break;
2063bd88451SPaolo Bonzini case gpt_capture_both:
2073bd88451SPaolo Bonzini trigger = (s->in_val == !on);
2083bd88451SPaolo Bonzini break;
2093bd88451SPaolo Bonzini }
2103bd88451SPaolo Bonzini s->in_val = on;
2113bd88451SPaolo Bonzini
2123bd88451SPaolo Bonzini if (s->inout && trigger && s->capt_num < 2) {
2133bd88451SPaolo Bonzini s->capture_val[s->capt_num] = omap_gp_timer_read(s);
2143bd88451SPaolo Bonzini
2153bd88451SPaolo Bonzini if (s->capt2 == s->capt_num ++)
2163bd88451SPaolo Bonzini omap_gp_timer_intr(s, GPT_TCAR_IT);
2173bd88451SPaolo Bonzini }
2183bd88451SPaolo Bonzini }
2193bd88451SPaolo Bonzini
omap_gp_timer_clk_update(void * opaque,int line,int on)2203bd88451SPaolo Bonzini static void omap_gp_timer_clk_update(void *opaque, int line, int on)
2213bd88451SPaolo Bonzini {
222*a75ed3c4SPhilippe Mathieu-Daudé struct omap_gp_timer_s *timer = opaque;
2233bd88451SPaolo Bonzini
2243bd88451SPaolo Bonzini omap_gp_timer_sync(timer);
2253bd88451SPaolo Bonzini timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
2263bd88451SPaolo Bonzini omap_gp_timer_update(timer);
2273bd88451SPaolo Bonzini }
2283bd88451SPaolo Bonzini
omap_gp_timer_clk_setup(struct omap_gp_timer_s * timer)2293bd88451SPaolo Bonzini static void omap_gp_timer_clk_setup(struct omap_gp_timer_s *timer)
2303bd88451SPaolo Bonzini {
2313bd88451SPaolo Bonzini omap_clk_adduser(timer->clk,
232f3c7d038SAndreas Färber qemu_allocate_irq(omap_gp_timer_clk_update, timer, 0));
2333bd88451SPaolo Bonzini timer->rate = omap_clk_getrate(timer->clk);
2343bd88451SPaolo Bonzini }
2353bd88451SPaolo Bonzini
omap_gp_timer_reset(struct omap_gp_timer_s * s)2363bd88451SPaolo Bonzini void omap_gp_timer_reset(struct omap_gp_timer_s *s)
2373bd88451SPaolo Bonzini {
2383bd88451SPaolo Bonzini s->config = 0x000;
2393bd88451SPaolo Bonzini s->status = 0;
2403bd88451SPaolo Bonzini s->it_ena = 0;
2413bd88451SPaolo Bonzini s->wu_ena = 0;
2423bd88451SPaolo Bonzini s->inout = 0;
2433bd88451SPaolo Bonzini s->capt2 = 0;
2443bd88451SPaolo Bonzini s->capt_num = 0;
2453bd88451SPaolo Bonzini s->pt = 0;
2463bd88451SPaolo Bonzini s->trigger = gpt_trigger_none;
2473bd88451SPaolo Bonzini s->capture = gpt_capture_none;
2483bd88451SPaolo Bonzini s->scpwm = 0;
2493bd88451SPaolo Bonzini s->ce = 0;
2503bd88451SPaolo Bonzini s->pre = 0;
2513bd88451SPaolo Bonzini s->ptv = 0;
2523bd88451SPaolo Bonzini s->ar = 0;
2533bd88451SPaolo Bonzini s->st = 0;
2543bd88451SPaolo Bonzini s->posted = 1;
2553bd88451SPaolo Bonzini s->val = 0x00000000;
2563bd88451SPaolo Bonzini s->load_val = 0x00000000;
2573bd88451SPaolo Bonzini s->capture_val[0] = 0x00000000;
2583bd88451SPaolo Bonzini s->capture_val[1] = 0x00000000;
2593bd88451SPaolo Bonzini s->match_val = 0x00000000;
2603bd88451SPaolo Bonzini omap_gp_timer_update(s);
2613bd88451SPaolo Bonzini }
2623bd88451SPaolo Bonzini
omap_gp_timer_readw(void * opaque,hwaddr addr)2633bd88451SPaolo Bonzini static uint32_t omap_gp_timer_readw(void *opaque, hwaddr addr)
2643bd88451SPaolo Bonzini {
265*a75ed3c4SPhilippe Mathieu-Daudé struct omap_gp_timer_s *s = opaque;
2663bd88451SPaolo Bonzini
2673bd88451SPaolo Bonzini switch (addr) {
2683bd88451SPaolo Bonzini case 0x00: /* TIDR */
2693bd88451SPaolo Bonzini return 0x21;
2703bd88451SPaolo Bonzini
2713bd88451SPaolo Bonzini case 0x10: /* TIOCP_CFG */
2723bd88451SPaolo Bonzini return s->config;
2733bd88451SPaolo Bonzini
2743bd88451SPaolo Bonzini case 0x14: /* TISTAT */
2753bd88451SPaolo Bonzini /* ??? When's this bit reset? */
2763bd88451SPaolo Bonzini return 1; /* RESETDONE */
2773bd88451SPaolo Bonzini
2783bd88451SPaolo Bonzini case 0x18: /* TISR */
2793bd88451SPaolo Bonzini return s->status;
2803bd88451SPaolo Bonzini
2813bd88451SPaolo Bonzini case 0x1c: /* TIER */
2823bd88451SPaolo Bonzini return s->it_ena;
2833bd88451SPaolo Bonzini
2843bd88451SPaolo Bonzini case 0x20: /* TWER */
2853bd88451SPaolo Bonzini return s->wu_ena;
2863bd88451SPaolo Bonzini
2873bd88451SPaolo Bonzini case 0x24: /* TCLR */
2883bd88451SPaolo Bonzini return (s->inout << 14) |
2893bd88451SPaolo Bonzini (s->capt2 << 13) |
2903bd88451SPaolo Bonzini (s->pt << 12) |
2913bd88451SPaolo Bonzini (s->trigger << 10) |
2923bd88451SPaolo Bonzini (s->capture << 8) |
2933bd88451SPaolo Bonzini (s->scpwm << 7) |
2943bd88451SPaolo Bonzini (s->ce << 6) |
2953bd88451SPaolo Bonzini (s->pre << 5) |
2963bd88451SPaolo Bonzini (s->ptv << 2) |
2973bd88451SPaolo Bonzini (s->ar << 1) |
2983bd88451SPaolo Bonzini (s->st << 0);
2993bd88451SPaolo Bonzini
3003bd88451SPaolo Bonzini case 0x28: /* TCRR */
3013bd88451SPaolo Bonzini return omap_gp_timer_read(s);
3023bd88451SPaolo Bonzini
3033bd88451SPaolo Bonzini case 0x2c: /* TLDR */
3043bd88451SPaolo Bonzini return s->load_val;
3053bd88451SPaolo Bonzini
3063bd88451SPaolo Bonzini case 0x30: /* TTGR */
3073bd88451SPaolo Bonzini return 0xffffffff;
3083bd88451SPaolo Bonzini
3093bd88451SPaolo Bonzini case 0x34: /* TWPS */
3103bd88451SPaolo Bonzini return 0x00000000; /* No posted writes pending. */
3113bd88451SPaolo Bonzini
3123bd88451SPaolo Bonzini case 0x38: /* TMAR */
3133bd88451SPaolo Bonzini return s->match_val;
3143bd88451SPaolo Bonzini
3153bd88451SPaolo Bonzini case 0x3c: /* TCAR1 */
3163bd88451SPaolo Bonzini return s->capture_val[0];
3173bd88451SPaolo Bonzini
3183bd88451SPaolo Bonzini case 0x40: /* TSICR */
3193bd88451SPaolo Bonzini return s->posted << 2;
3203bd88451SPaolo Bonzini
3213bd88451SPaolo Bonzini case 0x44: /* TCAR2 */
3223bd88451SPaolo Bonzini return s->capture_val[1];
3233bd88451SPaolo Bonzini }
3243bd88451SPaolo Bonzini
3253bd88451SPaolo Bonzini OMAP_BAD_REG(addr);
3263bd88451SPaolo Bonzini return 0;
3273bd88451SPaolo Bonzini }
3283bd88451SPaolo Bonzini
omap_gp_timer_readh(void * opaque,hwaddr addr)3293bd88451SPaolo Bonzini static uint32_t omap_gp_timer_readh(void *opaque, hwaddr addr)
3303bd88451SPaolo Bonzini {
331*a75ed3c4SPhilippe Mathieu-Daudé struct omap_gp_timer_s *s = opaque;
3323bd88451SPaolo Bonzini uint32_t ret;
3333bd88451SPaolo Bonzini
3343bd88451SPaolo Bonzini if (addr & 2)
3353bd88451SPaolo Bonzini return s->readh;
3363bd88451SPaolo Bonzini else {
3373bd88451SPaolo Bonzini ret = omap_gp_timer_readw(opaque, addr);
3383bd88451SPaolo Bonzini s->readh = ret >> 16;
3393bd88451SPaolo Bonzini return ret & 0xffff;
3403bd88451SPaolo Bonzini }
3413bd88451SPaolo Bonzini }
3423bd88451SPaolo Bonzini
omap_gp_timer_write(void * opaque,hwaddr addr,uint32_t value)343*a75ed3c4SPhilippe Mathieu-Daudé static void omap_gp_timer_write(void *opaque, hwaddr addr, uint32_t value)
3443bd88451SPaolo Bonzini {
345*a75ed3c4SPhilippe Mathieu-Daudé struct omap_gp_timer_s *s = opaque;
3463bd88451SPaolo Bonzini
3473bd88451SPaolo Bonzini switch (addr) {
3483bd88451SPaolo Bonzini case 0x00: /* TIDR */
3493bd88451SPaolo Bonzini case 0x14: /* TISTAT */
3503bd88451SPaolo Bonzini case 0x34: /* TWPS */
3513bd88451SPaolo Bonzini case 0x3c: /* TCAR1 */
3523bd88451SPaolo Bonzini case 0x44: /* TCAR2 */
3533bd88451SPaolo Bonzini OMAP_RO_REG(addr);
3543bd88451SPaolo Bonzini break;
3553bd88451SPaolo Bonzini
3563bd88451SPaolo Bonzini case 0x10: /* TIOCP_CFG */
3573bd88451SPaolo Bonzini s->config = value & 0x33d;
3583bd88451SPaolo Bonzini if (((value >> 3) & 3) == 3) /* IDLEMODE */
3593bd88451SPaolo Bonzini fprintf(stderr, "%s: illegal IDLEMODE value in TIOCP_CFG\n",
360a89f364aSAlistair Francis __func__);
3613bd88451SPaolo Bonzini if (value & 2) /* SOFTRESET */
3623bd88451SPaolo Bonzini omap_gp_timer_reset(s);
3633bd88451SPaolo Bonzini break;
3643bd88451SPaolo Bonzini
3653bd88451SPaolo Bonzini case 0x18: /* TISR */
3663bd88451SPaolo Bonzini if (value & GPT_TCAR_IT)
3673bd88451SPaolo Bonzini s->capt_num = 0;
3683bd88451SPaolo Bonzini if (s->status && !(s->status &= ~value))
3693bd88451SPaolo Bonzini qemu_irq_lower(s->irq);
3703bd88451SPaolo Bonzini break;
3713bd88451SPaolo Bonzini
3723bd88451SPaolo Bonzini case 0x1c: /* TIER */
3733bd88451SPaolo Bonzini s->it_ena = value & 7;
3743bd88451SPaolo Bonzini break;
3753bd88451SPaolo Bonzini
3763bd88451SPaolo Bonzini case 0x20: /* TWER */
3773bd88451SPaolo Bonzini s->wu_ena = value & 7;
3783bd88451SPaolo Bonzini break;
3793bd88451SPaolo Bonzini
3803bd88451SPaolo Bonzini case 0x24: /* TCLR */
3813bd88451SPaolo Bonzini omap_gp_timer_sync(s);
3823bd88451SPaolo Bonzini s->inout = (value >> 14) & 1;
3833bd88451SPaolo Bonzini s->capt2 = (value >> 13) & 1;
3843bd88451SPaolo Bonzini s->pt = (value >> 12) & 1;
3853bd88451SPaolo Bonzini s->trigger = (value >> 10) & 3;
3863bd88451SPaolo Bonzini if (s->capture == gpt_capture_none &&
3873bd88451SPaolo Bonzini ((value >> 8) & 3) != gpt_capture_none)
3883bd88451SPaolo Bonzini s->capt_num = 0;
3893bd88451SPaolo Bonzini s->capture = (value >> 8) & 3;
3903bd88451SPaolo Bonzini s->scpwm = (value >> 7) & 1;
3913bd88451SPaolo Bonzini s->ce = (value >> 6) & 1;
3923bd88451SPaolo Bonzini s->pre = (value >> 5) & 1;
3933bd88451SPaolo Bonzini s->ptv = (value >> 2) & 7;
3943bd88451SPaolo Bonzini s->ar = (value >> 1) & 1;
3953bd88451SPaolo Bonzini s->st = (value >> 0) & 1;
3963bd88451SPaolo Bonzini if (s->inout && s->trigger != gpt_trigger_none)
3973bd88451SPaolo Bonzini fprintf(stderr, "%s: GP timer pin must be an output "
398a89f364aSAlistair Francis "for this trigger mode\n", __func__);
3993bd88451SPaolo Bonzini if (!s->inout && s->capture != gpt_capture_none)
4003bd88451SPaolo Bonzini fprintf(stderr, "%s: GP timer pin must be an input "
401a89f364aSAlistair Francis "for this capture mode\n", __func__);
4023bd88451SPaolo Bonzini if (s->trigger == gpt_trigger_none)
4033bd88451SPaolo Bonzini omap_gp_timer_out(s, s->scpwm);
4043bd88451SPaolo Bonzini /* TODO: make sure this doesn't overflow 32-bits */
40573bcb24dSRutuja Shah s->ticks_per_sec = NANOSECONDS_PER_SECOND << (s->pre ? s->ptv + 1 : 0);
4063bd88451SPaolo Bonzini omap_gp_timer_update(s);
4073bd88451SPaolo Bonzini break;
4083bd88451SPaolo Bonzini
4093bd88451SPaolo Bonzini case 0x28: /* TCRR */
410bc72ad67SAlex Bligh s->time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
4113bd88451SPaolo Bonzini s->val = value;
4123bd88451SPaolo Bonzini omap_gp_timer_update(s);
4133bd88451SPaolo Bonzini break;
4143bd88451SPaolo Bonzini
4153bd88451SPaolo Bonzini case 0x2c: /* TLDR */
4163bd88451SPaolo Bonzini s->load_val = value;
4173bd88451SPaolo Bonzini break;
4183bd88451SPaolo Bonzini
4193bd88451SPaolo Bonzini case 0x30: /* TTGR */
420bc72ad67SAlex Bligh s->time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
4213bd88451SPaolo Bonzini s->val = s->load_val;
4223bd88451SPaolo Bonzini omap_gp_timer_update(s);
4233bd88451SPaolo Bonzini break;
4243bd88451SPaolo Bonzini
4253bd88451SPaolo Bonzini case 0x38: /* TMAR */
4263bd88451SPaolo Bonzini omap_gp_timer_sync(s);
4273bd88451SPaolo Bonzini s->match_val = value;
4283bd88451SPaolo Bonzini omap_gp_timer_update(s);
4293bd88451SPaolo Bonzini break;
4303bd88451SPaolo Bonzini
4313bd88451SPaolo Bonzini case 0x40: /* TSICR */
4323bd88451SPaolo Bonzini s->posted = (value >> 2) & 1;
4333bd88451SPaolo Bonzini if (value & 2) /* How much exactly are we supposed to reset? */
4343bd88451SPaolo Bonzini omap_gp_timer_reset(s);
4353bd88451SPaolo Bonzini break;
4363bd88451SPaolo Bonzini
4373bd88451SPaolo Bonzini default:
4383bd88451SPaolo Bonzini OMAP_BAD_REG(addr);
4393bd88451SPaolo Bonzini }
4403bd88451SPaolo Bonzini }
4413bd88451SPaolo Bonzini
omap_gp_timer_writeh(void * opaque,hwaddr addr,uint32_t value)442*a75ed3c4SPhilippe Mathieu-Daudé static void omap_gp_timer_writeh(void *opaque, hwaddr addr, uint32_t value)
4433bd88451SPaolo Bonzini {
444*a75ed3c4SPhilippe Mathieu-Daudé struct omap_gp_timer_s *s = opaque;
4453bd88451SPaolo Bonzini
4463bd88451SPaolo Bonzini if (addr & 2)
44777a8257eSStefan Weil omap_gp_timer_write(opaque, addr, (value << 16) | s->writeh);
4483bd88451SPaolo Bonzini else
4493bd88451SPaolo Bonzini s->writeh = (uint16_t) value;
4503bd88451SPaolo Bonzini }
4513bd88451SPaolo Bonzini
omap_gp_timer_readfn(void * opaque,hwaddr addr,unsigned size)45213dfde33SPeter Maydell static uint64_t omap_gp_timer_readfn(void *opaque, hwaddr addr,
45313dfde33SPeter Maydell unsigned size)
45413dfde33SPeter Maydell {
45513dfde33SPeter Maydell switch (size) {
45613dfde33SPeter Maydell case 1:
45713dfde33SPeter Maydell return omap_badwidth_read32(opaque, addr);
45813dfde33SPeter Maydell case 2:
45913dfde33SPeter Maydell return omap_gp_timer_readh(opaque, addr);
46013dfde33SPeter Maydell case 4:
46113dfde33SPeter Maydell return omap_gp_timer_readw(opaque, addr);
46213dfde33SPeter Maydell default:
46313dfde33SPeter Maydell g_assert_not_reached();
46413dfde33SPeter Maydell }
46513dfde33SPeter Maydell }
46613dfde33SPeter Maydell
omap_gp_timer_writefn(void * opaque,hwaddr addr,uint64_t value,unsigned size)46713dfde33SPeter Maydell static void omap_gp_timer_writefn(void *opaque, hwaddr addr,
46813dfde33SPeter Maydell uint64_t value, unsigned size)
46913dfde33SPeter Maydell {
47013dfde33SPeter Maydell switch (size) {
47113dfde33SPeter Maydell case 1:
47213dfde33SPeter Maydell omap_badwidth_write32(opaque, addr, value);
47313dfde33SPeter Maydell break;
47413dfde33SPeter Maydell case 2:
47513dfde33SPeter Maydell omap_gp_timer_writeh(opaque, addr, value);
47613dfde33SPeter Maydell break;
47713dfde33SPeter Maydell case 4:
47813dfde33SPeter Maydell omap_gp_timer_write(opaque, addr, value);
47913dfde33SPeter Maydell break;
48013dfde33SPeter Maydell default:
48113dfde33SPeter Maydell g_assert_not_reached();
48213dfde33SPeter Maydell }
48313dfde33SPeter Maydell }
48413dfde33SPeter Maydell
4853bd88451SPaolo Bonzini static const MemoryRegionOps omap_gp_timer_ops = {
48613dfde33SPeter Maydell .read = omap_gp_timer_readfn,
48713dfde33SPeter Maydell .write = omap_gp_timer_writefn,
48813dfde33SPeter Maydell .valid.min_access_size = 1,
48913dfde33SPeter Maydell .valid.max_access_size = 4,
4903bd88451SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN,
4913bd88451SPaolo Bonzini };
4923bd88451SPaolo Bonzini
omap_gp_timer_init(struct omap_target_agent_s * ta,qemu_irq irq,omap_clk fclk,omap_clk iclk)4933bd88451SPaolo Bonzini struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,
4943bd88451SPaolo Bonzini qemu_irq irq, omap_clk fclk, omap_clk iclk)
4953bd88451SPaolo Bonzini {
496b45c03f5SMarkus Armbruster struct omap_gp_timer_s *s = g_new0(struct omap_gp_timer_s, 1);
4973bd88451SPaolo Bonzini
4983bd88451SPaolo Bonzini s->ta = ta;
4993bd88451SPaolo Bonzini s->irq = irq;
5003bd88451SPaolo Bonzini s->clk = fclk;
501bc72ad67SAlex Bligh s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_gp_timer_tick, s);
502bc72ad67SAlex Bligh s->match = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_gp_timer_match, s);
503f3c7d038SAndreas Färber s->in = qemu_allocate_irq(omap_gp_timer_input, s, 0);
5043bd88451SPaolo Bonzini omap_gp_timer_reset(s);
5053bd88451SPaolo Bonzini omap_gp_timer_clk_setup(s);
5063bd88451SPaolo Bonzini
5072c9b15caSPaolo Bonzini memory_region_init_io(&s->iomem, NULL, &omap_gp_timer_ops, s, "omap.gptimer",
5083bd88451SPaolo Bonzini omap_l4_region_size(ta, 0));
5093bd88451SPaolo Bonzini omap_l4_attach(ta, 0, &s->iomem);
5103bd88451SPaolo Bonzini
5113bd88451SPaolo Bonzini return s;
5123bd88451SPaolo Bonzini }
513