1 /* 2 * Nuvoton NPCM7xx Timer Controller 3 * 4 * Copyright 2020 Google LLC 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 */ 16 17 #include "qemu/osdep.h" 18 19 #include "hw/irq.h" 20 #include "hw/qdev-clock.h" 21 #include "hw/qdev-properties.h" 22 #include "hw/timer/npcm7xx_timer.h" 23 #include "migration/vmstate.h" 24 #include "qemu/bitops.h" 25 #include "qemu/error-report.h" 26 #include "qemu/log.h" 27 #include "qemu/module.h" 28 #include "qemu/timer.h" 29 #include "qemu/units.h" 30 #include "trace.h" 31 32 /* 32-bit register indices. */ 33 enum NPCM7xxTimerRegisters { 34 NPCM7XX_TIMER_TCSR0, 35 NPCM7XX_TIMER_TCSR1, 36 NPCM7XX_TIMER_TICR0, 37 NPCM7XX_TIMER_TICR1, 38 NPCM7XX_TIMER_TDR0, 39 NPCM7XX_TIMER_TDR1, 40 NPCM7XX_TIMER_TISR, 41 NPCM7XX_TIMER_WTCR, 42 NPCM7XX_TIMER_TCSR2, 43 NPCM7XX_TIMER_TCSR3, 44 NPCM7XX_TIMER_TICR2, 45 NPCM7XX_TIMER_TICR3, 46 NPCM7XX_TIMER_TDR2, 47 NPCM7XX_TIMER_TDR3, 48 NPCM7XX_TIMER_TCSR4 = 0x0040 / sizeof(uint32_t), 49 NPCM7XX_TIMER_TICR4 = 0x0048 / sizeof(uint32_t), 50 NPCM7XX_TIMER_TDR4 = 0x0050 / sizeof(uint32_t), 51 NPCM7XX_TIMER_REGS_END, 52 }; 53 54 /* Register field definitions. */ 55 #define NPCM7XX_TCSR_CEN BIT(30) 56 #define NPCM7XX_TCSR_IE BIT(29) 57 #define NPCM7XX_TCSR_PERIODIC BIT(27) 58 #define NPCM7XX_TCSR_CRST BIT(26) 59 #define NPCM7XX_TCSR_CACT BIT(25) 60 #define NPCM7XX_TCSR_RSVD 0x01ffff00 61 #define NPCM7XX_TCSR_PRESCALE_START 0 62 #define NPCM7XX_TCSR_PRESCALE_LEN 8 63 64 #define NPCM7XX_WTCR_WTCLK(rv) extract32(rv, 10, 2) 65 #define NPCM7XX_WTCR_FREEZE_EN BIT(9) 66 #define NPCM7XX_WTCR_WTE BIT(7) 67 #define NPCM7XX_WTCR_WTIE BIT(6) 68 #define NPCM7XX_WTCR_WTIS(rv) extract32(rv, 4, 2) 69 #define NPCM7XX_WTCR_WTIF BIT(3) 70 #define NPCM7XX_WTCR_WTRF BIT(2) 71 #define NPCM7XX_WTCR_WTRE BIT(1) 72 #define NPCM7XX_WTCR_WTR BIT(0) 73 74 /* 75 * The number of clock cycles between interrupt and reset in watchdog, used 76 * by the software to handle the interrupt before system is reset. 77 */ 78 #define NPCM7XX_WATCHDOG_INTERRUPT_TO_RESET_CYCLES 1024 79 80 /* Start or resume the timer. */ 81 static void npcm7xx_timer_start(NPCM7xxBaseTimer *t) 82 { 83 int64_t now; 84 85 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 86 t->expires_ns = now + t->remaining_ns; 87 timer_mod(&t->qtimer, t->expires_ns); 88 } 89 90 /* Stop counting. Record the time remaining so we can continue later. */ 91 static void npcm7xx_timer_pause(NPCM7xxBaseTimer *t) 92 { 93 int64_t now; 94 95 timer_del(&t->qtimer); 96 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 97 t->remaining_ns = t->expires_ns - now; 98 } 99 100 /* Delete the timer and reset it to default state. */ 101 static void npcm7xx_timer_clear(NPCM7xxBaseTimer *t) 102 { 103 timer_del(&t->qtimer); 104 t->expires_ns = 0; 105 t->remaining_ns = 0; 106 } 107 108 /* 109 * Returns the index of timer in the tc->timer array. This can be used to 110 * locate the registers that belong to this timer. 111 */ 112 static int npcm7xx_timer_index(NPCM7xxTimerCtrlState *tc, NPCM7xxTimer *timer) 113 { 114 int index = timer - tc->timer; 115 116 g_assert(index >= 0 && index < NPCM7XX_TIMERS_PER_CTRL); 117 118 return index; 119 } 120 121 /* Return the value by which to divide the reference clock rate. */ 122 static uint32_t npcm7xx_tcsr_prescaler(uint32_t tcsr) 123 { 124 return extract32(tcsr, NPCM7XX_TCSR_PRESCALE_START, 125 NPCM7XX_TCSR_PRESCALE_LEN) + 1; 126 } 127 128 /* Convert a timer cycle count to a time interval in nanoseconds. */ 129 static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count) 130 { 131 int64_t ticks = count; 132 133 ticks *= npcm7xx_tcsr_prescaler(t->tcsr); 134 135 return clock_ticks_to_ns(t->ctrl->clock, ticks); 136 } 137 138 /* Convert a time interval in nanoseconds to a timer cycle count. */ 139 static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns) 140 { 141 if (ns < 0) { 142 return 0; 143 } 144 return clock_ns_to_ticks(t->ctrl->clock, ns) / 145 npcm7xx_tcsr_prescaler(t->tcsr); 146 } 147 148 static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t) 149 { 150 switch (NPCM7XX_WTCR_WTCLK(t->wtcr)) { 151 case 0: 152 return 1; 153 case 1: 154 return 256; 155 case 2: 156 return 2048; 157 case 3: 158 return 65536; 159 default: 160 g_assert_not_reached(); 161 } 162 } 163 164 static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t, 165 int64_t cycles) 166 { 167 int64_t ticks = cycles * npcm7xx_watchdog_timer_prescaler(t); 168 int64_t ns = clock_ticks_to_ns(t->ctrl->clock, ticks); 169 170 /* 171 * The reset function always clears the current timer. The caller of the 172 * this needs to decide whether to start the watchdog timer based on 173 * specific flag in WTCR. 174 */ 175 npcm7xx_timer_clear(&t->base_timer); 176 177 t->base_timer.remaining_ns = ns; 178 } 179 180 static void npcm7xx_watchdog_timer_reset(NPCM7xxWatchdogTimer *t) 181 { 182 int64_t cycles = 1; 183 uint32_t s = NPCM7XX_WTCR_WTIS(t->wtcr); 184 185 g_assert(s <= 3); 186 187 cycles <<= NPCM7XX_WATCHDOG_BASETIME_SHIFT; 188 cycles <<= 2 * s; 189 190 npcm7xx_watchdog_timer_reset_cycles(t, cycles); 191 } 192 193 /* 194 * Raise the interrupt line if there's a pending interrupt and interrupts are 195 * enabled for this timer. If not, lower it. 196 */ 197 static void npcm7xx_timer_check_interrupt(NPCM7xxTimer *t) 198 { 199 NPCM7xxTimerCtrlState *tc = t->ctrl; 200 int index = npcm7xx_timer_index(tc, t); 201 bool pending = (t->tcsr & NPCM7XX_TCSR_IE) && (tc->tisr & BIT(index)); 202 203 qemu_set_irq(t->irq, pending); 204 trace_npcm7xx_timer_irq(DEVICE(tc)->canonical_path, index, pending); 205 } 206 207 /* 208 * Called when the counter reaches zero. Sets the interrupt flag, and either 209 * restarts or disables the timer. 210 */ 211 static void npcm7xx_timer_reached_zero(NPCM7xxTimer *t) 212 { 213 NPCM7xxTimerCtrlState *tc = t->ctrl; 214 int index = npcm7xx_timer_index(tc, t); 215 216 tc->tisr |= BIT(index); 217 218 if (t->tcsr & NPCM7XX_TCSR_PERIODIC) { 219 t->base_timer.remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr); 220 if (t->tcsr & NPCM7XX_TCSR_CEN) { 221 npcm7xx_timer_start(&t->base_timer); 222 } 223 } else { 224 t->tcsr &= ~(NPCM7XX_TCSR_CEN | NPCM7XX_TCSR_CACT); 225 } 226 227 npcm7xx_timer_check_interrupt(t); 228 } 229 230 231 /* 232 * Restart the timer from its initial value. If the timer was enabled and stays 233 * enabled, adjust the QEMU timer according to the new count. If the timer is 234 * transitioning from disabled to enabled, the caller is expected to start the 235 * timer later. 236 */ 237 static void npcm7xx_timer_restart(NPCM7xxTimer *t, uint32_t old_tcsr) 238 { 239 t->base_timer.remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr); 240 241 if (old_tcsr & t->tcsr & NPCM7XX_TCSR_CEN) { 242 npcm7xx_timer_start(&t->base_timer); 243 } 244 } 245 246 /* Register read and write handlers */ 247 248 static uint32_t npcm7xx_timer_read_tdr(NPCM7xxTimer *t) 249 { 250 if (t->tcsr & NPCM7XX_TCSR_CEN) { 251 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 252 253 return npcm7xx_timer_ns_to_count(t, t->base_timer.expires_ns - now); 254 } 255 256 return npcm7xx_timer_ns_to_count(t, t->base_timer.remaining_ns); 257 } 258 259 static void npcm7xx_timer_write_tcsr(NPCM7xxTimer *t, uint32_t new_tcsr) 260 { 261 uint32_t old_tcsr = t->tcsr; 262 uint32_t tdr; 263 264 if (new_tcsr & NPCM7XX_TCSR_RSVD) { 265 qemu_log_mask(LOG_GUEST_ERROR, "%s: reserved bits in 0x%08x ignored\n", 266 __func__, new_tcsr); 267 new_tcsr &= ~NPCM7XX_TCSR_RSVD; 268 } 269 if (new_tcsr & NPCM7XX_TCSR_CACT) { 270 qemu_log_mask(LOG_GUEST_ERROR, "%s: read-only bits in 0x%08x ignored\n", 271 __func__, new_tcsr); 272 new_tcsr &= ~NPCM7XX_TCSR_CACT; 273 } 274 if ((new_tcsr & NPCM7XX_TCSR_CRST) && (new_tcsr & NPCM7XX_TCSR_CEN)) { 275 qemu_log_mask(LOG_GUEST_ERROR, 276 "%s: both CRST and CEN set; ignoring CEN.\n", 277 __func__); 278 new_tcsr &= ~NPCM7XX_TCSR_CEN; 279 } 280 281 /* Calculate the value of TDR before potentially changing the prescaler. */ 282 tdr = npcm7xx_timer_read_tdr(t); 283 284 t->tcsr = (t->tcsr & NPCM7XX_TCSR_CACT) | new_tcsr; 285 286 if (npcm7xx_tcsr_prescaler(old_tcsr) != npcm7xx_tcsr_prescaler(new_tcsr)) { 287 /* Recalculate time remaining based on the current TDR value. */ 288 t->base_timer.remaining_ns = npcm7xx_timer_count_to_ns(t, tdr); 289 if (old_tcsr & t->tcsr & NPCM7XX_TCSR_CEN) { 290 npcm7xx_timer_start(&t->base_timer); 291 } 292 } 293 294 if ((old_tcsr ^ new_tcsr) & NPCM7XX_TCSR_IE) { 295 npcm7xx_timer_check_interrupt(t); 296 } 297 if (new_tcsr & NPCM7XX_TCSR_CRST) { 298 npcm7xx_timer_restart(t, old_tcsr); 299 t->tcsr &= ~NPCM7XX_TCSR_CRST; 300 } 301 if ((old_tcsr ^ new_tcsr) & NPCM7XX_TCSR_CEN) { 302 if (new_tcsr & NPCM7XX_TCSR_CEN) { 303 t->tcsr |= NPCM7XX_TCSR_CACT; 304 npcm7xx_timer_start(&t->base_timer); 305 } else { 306 t->tcsr &= ~NPCM7XX_TCSR_CACT; 307 npcm7xx_timer_pause(&t->base_timer); 308 if (t->base_timer.remaining_ns <= 0) { 309 npcm7xx_timer_reached_zero(t); 310 } 311 } 312 } 313 } 314 315 static void npcm7xx_timer_write_ticr(NPCM7xxTimer *t, uint32_t new_ticr) 316 { 317 t->ticr = new_ticr; 318 319 npcm7xx_timer_restart(t, t->tcsr); 320 } 321 322 static void npcm7xx_timer_write_tisr(NPCM7xxTimerCtrlState *s, uint32_t value) 323 { 324 int i; 325 326 s->tisr &= ~value; 327 for (i = 0; i < ARRAY_SIZE(s->timer); i++) { 328 if (value & (1U << i)) { 329 npcm7xx_timer_check_interrupt(&s->timer[i]); 330 } 331 332 } 333 } 334 335 static void npcm7xx_timer_write_wtcr(NPCM7xxWatchdogTimer *t, uint32_t new_wtcr) 336 { 337 uint32_t old_wtcr = t->wtcr; 338 339 /* 340 * WTIF and WTRF are cleared by writing 1. Writing 0 makes these bits 341 * unchanged. 342 */ 343 if (new_wtcr & NPCM7XX_WTCR_WTIF) { 344 new_wtcr &= ~NPCM7XX_WTCR_WTIF; 345 } else if (old_wtcr & NPCM7XX_WTCR_WTIF) { 346 new_wtcr |= NPCM7XX_WTCR_WTIF; 347 } 348 if (new_wtcr & NPCM7XX_WTCR_WTRF) { 349 new_wtcr &= ~NPCM7XX_WTCR_WTRF; 350 } else if (old_wtcr & NPCM7XX_WTCR_WTRF) { 351 new_wtcr |= NPCM7XX_WTCR_WTRF; 352 } 353 354 t->wtcr = new_wtcr; 355 356 if (new_wtcr & NPCM7XX_WTCR_WTR) { 357 t->wtcr &= ~NPCM7XX_WTCR_WTR; 358 npcm7xx_watchdog_timer_reset(t); 359 if (new_wtcr & NPCM7XX_WTCR_WTE) { 360 npcm7xx_timer_start(&t->base_timer); 361 } 362 } else if ((old_wtcr ^ new_wtcr) & NPCM7XX_WTCR_WTE) { 363 if (new_wtcr & NPCM7XX_WTCR_WTE) { 364 npcm7xx_timer_start(&t->base_timer); 365 } else { 366 npcm7xx_timer_pause(&t->base_timer); 367 } 368 } 369 370 } 371 372 static hwaddr npcm7xx_tcsr_index(hwaddr reg) 373 { 374 switch (reg) { 375 case NPCM7XX_TIMER_TCSR0: 376 return 0; 377 case NPCM7XX_TIMER_TCSR1: 378 return 1; 379 case NPCM7XX_TIMER_TCSR2: 380 return 2; 381 case NPCM7XX_TIMER_TCSR3: 382 return 3; 383 case NPCM7XX_TIMER_TCSR4: 384 return 4; 385 default: 386 g_assert_not_reached(); 387 } 388 } 389 390 static hwaddr npcm7xx_ticr_index(hwaddr reg) 391 { 392 switch (reg) { 393 case NPCM7XX_TIMER_TICR0: 394 return 0; 395 case NPCM7XX_TIMER_TICR1: 396 return 1; 397 case NPCM7XX_TIMER_TICR2: 398 return 2; 399 case NPCM7XX_TIMER_TICR3: 400 return 3; 401 case NPCM7XX_TIMER_TICR4: 402 return 4; 403 default: 404 g_assert_not_reached(); 405 } 406 } 407 408 static hwaddr npcm7xx_tdr_index(hwaddr reg) 409 { 410 switch (reg) { 411 case NPCM7XX_TIMER_TDR0: 412 return 0; 413 case NPCM7XX_TIMER_TDR1: 414 return 1; 415 case NPCM7XX_TIMER_TDR2: 416 return 2; 417 case NPCM7XX_TIMER_TDR3: 418 return 3; 419 case NPCM7XX_TIMER_TDR4: 420 return 4; 421 default: 422 g_assert_not_reached(); 423 } 424 } 425 426 static uint64_t npcm7xx_timer_read(void *opaque, hwaddr offset, unsigned size) 427 { 428 NPCM7xxTimerCtrlState *s = opaque; 429 uint64_t value = 0; 430 hwaddr reg; 431 432 reg = offset / sizeof(uint32_t); 433 switch (reg) { 434 case NPCM7XX_TIMER_TCSR0: 435 case NPCM7XX_TIMER_TCSR1: 436 case NPCM7XX_TIMER_TCSR2: 437 case NPCM7XX_TIMER_TCSR3: 438 case NPCM7XX_TIMER_TCSR4: 439 value = s->timer[npcm7xx_tcsr_index(reg)].tcsr; 440 break; 441 442 case NPCM7XX_TIMER_TICR0: 443 case NPCM7XX_TIMER_TICR1: 444 case NPCM7XX_TIMER_TICR2: 445 case NPCM7XX_TIMER_TICR3: 446 case NPCM7XX_TIMER_TICR4: 447 value = s->timer[npcm7xx_ticr_index(reg)].ticr; 448 break; 449 450 case NPCM7XX_TIMER_TDR0: 451 case NPCM7XX_TIMER_TDR1: 452 case NPCM7XX_TIMER_TDR2: 453 case NPCM7XX_TIMER_TDR3: 454 case NPCM7XX_TIMER_TDR4: 455 value = npcm7xx_timer_read_tdr(&s->timer[npcm7xx_tdr_index(reg)]); 456 break; 457 458 case NPCM7XX_TIMER_TISR: 459 value = s->tisr; 460 break; 461 462 case NPCM7XX_TIMER_WTCR: 463 value = s->watchdog_timer.wtcr; 464 break; 465 466 default: 467 qemu_log_mask(LOG_GUEST_ERROR, 468 "%s: invalid offset 0x%04" HWADDR_PRIx "\n", 469 __func__, offset); 470 break; 471 } 472 473 trace_npcm7xx_timer_read(DEVICE(s)->canonical_path, offset, value); 474 475 return value; 476 } 477 478 static void npcm7xx_timer_write(void *opaque, hwaddr offset, 479 uint64_t v, unsigned size) 480 { 481 uint32_t reg = offset / sizeof(uint32_t); 482 NPCM7xxTimerCtrlState *s = opaque; 483 uint32_t value = v; 484 485 trace_npcm7xx_timer_write(DEVICE(s)->canonical_path, offset, value); 486 487 switch (reg) { 488 case NPCM7XX_TIMER_TCSR0: 489 case NPCM7XX_TIMER_TCSR1: 490 case NPCM7XX_TIMER_TCSR2: 491 case NPCM7XX_TIMER_TCSR3: 492 case NPCM7XX_TIMER_TCSR4: 493 npcm7xx_timer_write_tcsr(&s->timer[npcm7xx_tcsr_index(reg)], value); 494 return; 495 496 case NPCM7XX_TIMER_TICR0: 497 case NPCM7XX_TIMER_TICR1: 498 case NPCM7XX_TIMER_TICR2: 499 case NPCM7XX_TIMER_TICR3: 500 case NPCM7XX_TIMER_TICR4: 501 npcm7xx_timer_write_ticr(&s->timer[npcm7xx_ticr_index(reg)], value); 502 return; 503 504 case NPCM7XX_TIMER_TDR0: 505 case NPCM7XX_TIMER_TDR1: 506 case NPCM7XX_TIMER_TDR2: 507 case NPCM7XX_TIMER_TDR3: 508 case NPCM7XX_TIMER_TDR4: 509 qemu_log_mask(LOG_GUEST_ERROR, 510 "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n", 511 __func__, offset); 512 return; 513 514 case NPCM7XX_TIMER_TISR: 515 npcm7xx_timer_write_tisr(s, value); 516 return; 517 518 case NPCM7XX_TIMER_WTCR: 519 npcm7xx_timer_write_wtcr(&s->watchdog_timer, value); 520 return; 521 } 522 523 qemu_log_mask(LOG_GUEST_ERROR, 524 "%s: invalid offset 0x%04" HWADDR_PRIx "\n", 525 __func__, offset); 526 } 527 528 static const struct MemoryRegionOps npcm7xx_timer_ops = { 529 .read = npcm7xx_timer_read, 530 .write = npcm7xx_timer_write, 531 .endianness = DEVICE_LITTLE_ENDIAN, 532 .valid = { 533 .min_access_size = 4, 534 .max_access_size = 4, 535 .unaligned = false, 536 }, 537 }; 538 539 /* Called when the QEMU timer expires. */ 540 static void npcm7xx_timer_expired(void *opaque) 541 { 542 NPCM7xxTimer *t = opaque; 543 544 if (t->tcsr & NPCM7XX_TCSR_CEN) { 545 npcm7xx_timer_reached_zero(t); 546 } 547 } 548 549 static void npcm7xx_timer_enter_reset(Object *obj, ResetType type) 550 { 551 NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj); 552 int i; 553 554 for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) { 555 NPCM7xxTimer *t = &s->timer[i]; 556 557 npcm7xx_timer_clear(&t->base_timer); 558 t->tcsr = 0x00000005; 559 t->ticr = 0x00000000; 560 } 561 562 s->tisr = 0x00000000; 563 /* 564 * Set WTCLK to 1(default) and reset all flags except WTRF. 565 * WTRF is not reset during a core domain reset. 566 */ 567 s->watchdog_timer.wtcr = 0x00000400 | (s->watchdog_timer.wtcr & 568 NPCM7XX_WTCR_WTRF); 569 } 570 571 static void npcm7xx_watchdog_timer_expired(void *opaque) 572 { 573 NPCM7xxWatchdogTimer *t = opaque; 574 575 if (t->wtcr & NPCM7XX_WTCR_WTE) { 576 if (t->wtcr & NPCM7XX_WTCR_WTIF) { 577 if (t->wtcr & NPCM7XX_WTCR_WTRE) { 578 t->wtcr |= NPCM7XX_WTCR_WTRF; 579 /* send reset signal to CLK module*/ 580 qemu_irq_raise(t->reset_signal); 581 } 582 } else { 583 t->wtcr |= NPCM7XX_WTCR_WTIF; 584 if (t->wtcr & NPCM7XX_WTCR_WTIE) { 585 /* send interrupt */ 586 qemu_irq_raise(t->irq); 587 } 588 npcm7xx_watchdog_timer_reset_cycles(t, 589 NPCM7XX_WATCHDOG_INTERRUPT_TO_RESET_CYCLES); 590 npcm7xx_timer_start(&t->base_timer); 591 } 592 } 593 } 594 595 static void npcm7xx_timer_hold_reset(Object *obj, ResetType type) 596 { 597 NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj); 598 int i; 599 600 for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) { 601 qemu_irq_lower(s->timer[i].irq); 602 } 603 qemu_irq_lower(s->watchdog_timer.irq); 604 } 605 606 static void npcm7xx_timer_init(Object *obj) 607 { 608 NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj); 609 DeviceState *dev = DEVICE(obj); 610 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 611 int i; 612 NPCM7xxWatchdogTimer *w; 613 614 for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) { 615 NPCM7xxTimer *t = &s->timer[i]; 616 t->ctrl = s; 617 timer_init_ns(&t->base_timer.qtimer, QEMU_CLOCK_VIRTUAL, 618 npcm7xx_timer_expired, t); 619 sysbus_init_irq(sbd, &t->irq); 620 } 621 622 w = &s->watchdog_timer; 623 w->ctrl = s; 624 timer_init_ns(&w->base_timer.qtimer, QEMU_CLOCK_VIRTUAL, 625 npcm7xx_watchdog_timer_expired, w); 626 sysbus_init_irq(sbd, &w->irq); 627 628 memory_region_init_io(&s->iomem, obj, &npcm7xx_timer_ops, s, 629 TYPE_NPCM7XX_TIMER, 4 * KiB); 630 sysbus_init_mmio(sbd, &s->iomem); 631 qdev_init_gpio_out_named(dev, &w->reset_signal, 632 NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 1); 633 s->clock = qdev_init_clock_in(dev, "clock", NULL, NULL, 0); 634 } 635 636 static const VMStateDescription vmstate_npcm7xx_base_timer = { 637 .name = "npcm7xx-base-timer", 638 .version_id = 0, 639 .minimum_version_id = 0, 640 .fields = (const VMStateField[]) { 641 VMSTATE_TIMER(qtimer, NPCM7xxBaseTimer), 642 VMSTATE_INT64(expires_ns, NPCM7xxBaseTimer), 643 VMSTATE_INT64(remaining_ns, NPCM7xxBaseTimer), 644 VMSTATE_END_OF_LIST(), 645 }, 646 }; 647 648 static const VMStateDescription vmstate_npcm7xx_timer = { 649 .name = "npcm7xx-timer", 650 .version_id = 1, 651 .minimum_version_id = 1, 652 .fields = (const VMStateField[]) { 653 VMSTATE_STRUCT(base_timer, NPCM7xxTimer, 654 0, vmstate_npcm7xx_base_timer, 655 NPCM7xxBaseTimer), 656 VMSTATE_UINT32(tcsr, NPCM7xxTimer), 657 VMSTATE_UINT32(ticr, NPCM7xxTimer), 658 VMSTATE_END_OF_LIST(), 659 }, 660 }; 661 662 static const VMStateDescription vmstate_npcm7xx_watchdog_timer = { 663 .name = "npcm7xx-watchdog-timer", 664 .version_id = 0, 665 .minimum_version_id = 0, 666 .fields = (const VMStateField[]) { 667 VMSTATE_STRUCT(base_timer, NPCM7xxWatchdogTimer, 668 0, vmstate_npcm7xx_base_timer, 669 NPCM7xxBaseTimer), 670 VMSTATE_UINT32(wtcr, NPCM7xxWatchdogTimer), 671 VMSTATE_END_OF_LIST(), 672 }, 673 }; 674 675 static const VMStateDescription vmstate_npcm7xx_timer_ctrl = { 676 .name = "npcm7xx-timer-ctrl", 677 .version_id = 2, 678 .minimum_version_id = 2, 679 .fields = (const VMStateField[]) { 680 VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState), 681 VMSTATE_CLOCK(clock, NPCM7xxTimerCtrlState), 682 VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState, 683 NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx_timer, 684 NPCM7xxTimer), 685 VMSTATE_STRUCT(watchdog_timer, NPCM7xxTimerCtrlState, 686 0, vmstate_npcm7xx_watchdog_timer, 687 NPCM7xxWatchdogTimer), 688 VMSTATE_END_OF_LIST(), 689 }, 690 }; 691 692 static void npcm7xx_timer_class_init(ObjectClass *klass, void *data) 693 { 694 ResettableClass *rc = RESETTABLE_CLASS(klass); 695 DeviceClass *dc = DEVICE_CLASS(klass); 696 697 QEMU_BUILD_BUG_ON(NPCM7XX_TIMER_REGS_END > NPCM7XX_TIMER_NR_REGS); 698 699 dc->desc = "NPCM7xx Timer Controller"; 700 dc->vmsd = &vmstate_npcm7xx_timer_ctrl; 701 rc->phases.enter = npcm7xx_timer_enter_reset; 702 rc->phases.hold = npcm7xx_timer_hold_reset; 703 } 704 705 static const TypeInfo npcm7xx_timer_info = { 706 .name = TYPE_NPCM7XX_TIMER, 707 .parent = TYPE_SYS_BUS_DEVICE, 708 .instance_size = sizeof(NPCM7xxTimerCtrlState), 709 .class_init = npcm7xx_timer_class_init, 710 .instance_init = npcm7xx_timer_init, 711 }; 712 713 static void npcm7xx_timer_register_type(void) 714 { 715 type_register_static(&npcm7xx_timer_info); 716 } 717 type_init(npcm7xx_timer_register_type); 718