1 /* 2 * Block model of System timer present in 3 * Microsemi's SmartFusion2 and SmartFusion SoCs. 4 * 5 * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qemu/main-loop.h" 28 #include "qemu/module.h" 29 #include "qemu/log.h" 30 #include "hw/irq.h" 31 #include "hw/timer/mss-timer.h" 32 #include "migration/vmstate.h" 33 34 #ifndef MSS_TIMER_ERR_DEBUG 35 #define MSS_TIMER_ERR_DEBUG 0 36 #endif 37 38 #define DB_PRINT_L(lvl, fmt, args...) do { \ 39 if (MSS_TIMER_ERR_DEBUG >= lvl) { \ 40 qemu_log("%s: " fmt "\n", __func__, ## args); \ 41 } \ 42 } while (0) 43 44 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) 45 46 #define R_TIM_VAL 0 47 #define R_TIM_LOADVAL 1 48 #define R_TIM_BGLOADVAL 2 49 #define R_TIM_CTRL 3 50 #define R_TIM_RIS 4 51 #define R_TIM_MIS 5 52 53 #define TIMER_CTRL_ENBL (1 << 0) 54 #define TIMER_CTRL_ONESHOT (1 << 1) 55 #define TIMER_CTRL_INTR (1 << 2) 56 #define TIMER_RIS_ACK (1 << 0) 57 #define TIMER_RST_CLR (1 << 6) 58 #define TIMER_MODE (1 << 0) 59 60 static void timer_update_irq(struct Msf2Timer *st) 61 { 62 bool isr, ier; 63 64 isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK); 65 ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR); 66 qemu_set_irq(st->irq, (ier && isr)); 67 } 68 69 static void timer_update(struct Msf2Timer *st) 70 { 71 uint64_t count; 72 73 if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL)) { 74 ptimer_stop(st->ptimer); 75 return; 76 } 77 78 count = st->regs[R_TIM_LOADVAL]; 79 ptimer_set_limit(st->ptimer, count, 1); 80 ptimer_run(st->ptimer, 1); 81 } 82 83 static uint64_t 84 timer_read(void *opaque, hwaddr offset, unsigned int size) 85 { 86 MSSTimerState *t = opaque; 87 hwaddr addr; 88 struct Msf2Timer *st; 89 uint32_t ret = 0; 90 int timer = 0; 91 int isr; 92 int ier; 93 94 addr = offset >> 2; 95 /* 96 * Two independent timers has same base address. 97 * Based on address passed figure out which timer is being used. 98 */ 99 if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) { 100 timer = 1; 101 addr -= R_TIM1_MAX; 102 } 103 104 st = &t->timers[timer]; 105 106 switch (addr) { 107 case R_TIM_VAL: 108 ret = ptimer_get_count(st->ptimer); 109 break; 110 111 case R_TIM_MIS: 112 isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK); 113 ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR); 114 ret = ier & isr; 115 break; 116 117 default: 118 if (addr < R_TIM1_MAX) { 119 ret = st->regs[addr]; 120 } else { 121 qemu_log_mask(LOG_GUEST_ERROR, 122 TYPE_MSS_TIMER": 64-bit mode not supported\n"); 123 return ret; 124 } 125 break; 126 } 127 128 DB_PRINT("timer=%d 0x%" HWADDR_PRIx "=0x%" PRIx32, timer, offset, 129 ret); 130 return ret; 131 } 132 133 static void 134 timer_write(void *opaque, hwaddr offset, 135 uint64_t val64, unsigned int size) 136 { 137 MSSTimerState *t = opaque; 138 hwaddr addr; 139 struct Msf2Timer *st; 140 int timer = 0; 141 uint32_t value = val64; 142 143 addr = offset >> 2; 144 /* 145 * Two independent timers has same base address. 146 * Based on addr passed figure out which timer is being used. 147 */ 148 if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) { 149 timer = 1; 150 addr -= R_TIM1_MAX; 151 } 152 153 st = &t->timers[timer]; 154 155 DB_PRINT("addr=0x%" HWADDR_PRIx " val=0x%" PRIx32 " (timer=%d)", offset, 156 value, timer); 157 158 switch (addr) { 159 case R_TIM_CTRL: 160 st->regs[R_TIM_CTRL] = value; 161 timer_update(st); 162 break; 163 164 case R_TIM_RIS: 165 if (value & TIMER_RIS_ACK) { 166 st->regs[R_TIM_RIS] &= ~TIMER_RIS_ACK; 167 } 168 break; 169 170 case R_TIM_LOADVAL: 171 st->regs[R_TIM_LOADVAL] = value; 172 if (st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL) { 173 timer_update(st); 174 } 175 break; 176 177 case R_TIM_BGLOADVAL: 178 st->regs[R_TIM_BGLOADVAL] = value; 179 st->regs[R_TIM_LOADVAL] = value; 180 break; 181 182 case R_TIM_VAL: 183 case R_TIM_MIS: 184 break; 185 186 default: 187 if (addr < R_TIM1_MAX) { 188 st->regs[addr] = value; 189 } else { 190 qemu_log_mask(LOG_GUEST_ERROR, 191 TYPE_MSS_TIMER": 64-bit mode not supported\n"); 192 return; 193 } 194 break; 195 } 196 timer_update_irq(st); 197 } 198 199 static const MemoryRegionOps timer_ops = { 200 .read = timer_read, 201 .write = timer_write, 202 .endianness = DEVICE_NATIVE_ENDIAN, 203 .valid = { 204 .min_access_size = 1, 205 .max_access_size = 4 206 } 207 }; 208 209 static void timer_hit(void *opaque) 210 { 211 struct Msf2Timer *st = opaque; 212 213 st->regs[R_TIM_RIS] |= TIMER_RIS_ACK; 214 215 if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ONESHOT)) { 216 timer_update(st); 217 } 218 timer_update_irq(st); 219 } 220 221 static void mss_timer_init(Object *obj) 222 { 223 MSSTimerState *t = MSS_TIMER(obj); 224 int i; 225 226 /* Init all the ptimers. */ 227 for (i = 0; i < NUM_TIMERS; i++) { 228 struct Msf2Timer *st = &t->timers[i]; 229 230 st->bh = qemu_bh_new(timer_hit, st); 231 st->ptimer = ptimer_init(st->bh, PTIMER_POLICY_DEFAULT); 232 ptimer_set_freq(st->ptimer, t->freq_hz); 233 sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq); 234 } 235 236 memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, TYPE_MSS_TIMER, 237 NUM_TIMERS * R_TIM1_MAX * 4); 238 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio); 239 } 240 241 static const VMStateDescription vmstate_timers = { 242 .name = "mss-timer-block", 243 .version_id = 1, 244 .minimum_version_id = 1, 245 .fields = (VMStateField[]) { 246 VMSTATE_PTIMER(ptimer, struct Msf2Timer), 247 VMSTATE_UINT32_ARRAY(regs, struct Msf2Timer, R_TIM1_MAX), 248 VMSTATE_END_OF_LIST() 249 } 250 }; 251 252 static const VMStateDescription vmstate_mss_timer = { 253 .name = TYPE_MSS_TIMER, 254 .version_id = 1, 255 .minimum_version_id = 1, 256 .fields = (VMStateField[]) { 257 VMSTATE_UINT32(freq_hz, MSSTimerState), 258 VMSTATE_STRUCT_ARRAY(timers, MSSTimerState, NUM_TIMERS, 0, 259 vmstate_timers, struct Msf2Timer), 260 VMSTATE_END_OF_LIST() 261 } 262 }; 263 264 static Property mss_timer_properties[] = { 265 /* Libero GUI shows 100Mhz as default for clocks */ 266 DEFINE_PROP_UINT32("clock-frequency", MSSTimerState, freq_hz, 267 100 * 1000000), 268 DEFINE_PROP_END_OF_LIST(), 269 }; 270 271 static void mss_timer_class_init(ObjectClass *klass, void *data) 272 { 273 DeviceClass *dc = DEVICE_CLASS(klass); 274 275 dc->props = mss_timer_properties; 276 dc->vmsd = &vmstate_mss_timer; 277 } 278 279 static const TypeInfo mss_timer_info = { 280 .name = TYPE_MSS_TIMER, 281 .parent = TYPE_SYS_BUS_DEVICE, 282 .instance_size = sizeof(MSSTimerState), 283 .instance_init = mss_timer_init, 284 .class_init = mss_timer_class_init, 285 }; 286 287 static void mss_timer_register_types(void) 288 { 289 type_register_static(&mss_timer_info); 290 } 291 292 type_init(mss_timer_register_types) 293