1 /* 2 * Block model of System timer present in 3 * Microsemi's SmartFusion2 and SmartFusion SoCs. 4 * 5 * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qemu/main-loop.h" 28 #include "qemu/log.h" 29 #include "hw/timer/mss-timer.h" 30 31 #ifndef MSS_TIMER_ERR_DEBUG 32 #define MSS_TIMER_ERR_DEBUG 0 33 #endif 34 35 #define DB_PRINT_L(lvl, fmt, args...) do { \ 36 if (MSS_TIMER_ERR_DEBUG >= lvl) { \ 37 qemu_log("%s: " fmt "\n", __func__, ## args); \ 38 } \ 39 } while (0) 40 41 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) 42 43 #define R_TIM_VAL 0 44 #define R_TIM_LOADVAL 1 45 #define R_TIM_BGLOADVAL 2 46 #define R_TIM_CTRL 3 47 #define R_TIM_RIS 4 48 #define R_TIM_MIS 5 49 50 #define TIMER_CTRL_ENBL (1 << 0) 51 #define TIMER_CTRL_ONESHOT (1 << 1) 52 #define TIMER_CTRL_INTR (1 << 2) 53 #define TIMER_RIS_ACK (1 << 0) 54 #define TIMER_RST_CLR (1 << 6) 55 #define TIMER_MODE (1 << 0) 56 57 static void timer_update_irq(struct Msf2Timer *st) 58 { 59 bool isr, ier; 60 61 isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK); 62 ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR); 63 qemu_set_irq(st->irq, (ier && isr)); 64 } 65 66 static void timer_update(struct Msf2Timer *st) 67 { 68 uint64_t count; 69 70 if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL)) { 71 ptimer_stop(st->ptimer); 72 return; 73 } 74 75 count = st->regs[R_TIM_LOADVAL]; 76 ptimer_set_limit(st->ptimer, count, 1); 77 ptimer_run(st->ptimer, 1); 78 } 79 80 static uint64_t 81 timer_read(void *opaque, hwaddr offset, unsigned int size) 82 { 83 MSSTimerState *t = opaque; 84 hwaddr addr; 85 struct Msf2Timer *st; 86 uint32_t ret = 0; 87 int timer = 0; 88 int isr; 89 int ier; 90 91 addr = offset >> 2; 92 /* 93 * Two independent timers has same base address. 94 * Based on address passed figure out which timer is being used. 95 */ 96 if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) { 97 timer = 1; 98 addr -= R_TIM1_MAX; 99 } 100 101 st = &t->timers[timer]; 102 103 switch (addr) { 104 case R_TIM_VAL: 105 ret = ptimer_get_count(st->ptimer); 106 break; 107 108 case R_TIM_MIS: 109 isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK); 110 ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR); 111 ret = ier & isr; 112 break; 113 114 default: 115 if (addr < R_TIM1_MAX) { 116 ret = st->regs[addr]; 117 } else { 118 qemu_log_mask(LOG_GUEST_ERROR, 119 TYPE_MSS_TIMER": 64-bit mode not supported\n"); 120 return ret; 121 } 122 break; 123 } 124 125 DB_PRINT("timer=%d 0x%" HWADDR_PRIx "=0x%" PRIx32, timer, offset, 126 ret); 127 return ret; 128 } 129 130 static void 131 timer_write(void *opaque, hwaddr offset, 132 uint64_t val64, unsigned int size) 133 { 134 MSSTimerState *t = opaque; 135 hwaddr addr; 136 struct Msf2Timer *st; 137 int timer = 0; 138 uint32_t value = val64; 139 140 addr = offset >> 2; 141 /* 142 * Two independent timers has same base address. 143 * Based on addr passed figure out which timer is being used. 144 */ 145 if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) { 146 timer = 1; 147 addr -= R_TIM1_MAX; 148 } 149 150 st = &t->timers[timer]; 151 152 DB_PRINT("addr=0x%" HWADDR_PRIx " val=0x%" PRIx32 " (timer=%d)", offset, 153 value, timer); 154 155 switch (addr) { 156 case R_TIM_CTRL: 157 st->regs[R_TIM_CTRL] = value; 158 timer_update(st); 159 break; 160 161 case R_TIM_RIS: 162 if (value & TIMER_RIS_ACK) { 163 st->regs[R_TIM_RIS] &= ~TIMER_RIS_ACK; 164 } 165 break; 166 167 case R_TIM_LOADVAL: 168 st->regs[R_TIM_LOADVAL] = value; 169 if (st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL) { 170 timer_update(st); 171 } 172 break; 173 174 case R_TIM_BGLOADVAL: 175 st->regs[R_TIM_BGLOADVAL] = value; 176 st->regs[R_TIM_LOADVAL] = value; 177 break; 178 179 case R_TIM_VAL: 180 case R_TIM_MIS: 181 break; 182 183 default: 184 if (addr < R_TIM1_MAX) { 185 st->regs[addr] = value; 186 } else { 187 qemu_log_mask(LOG_GUEST_ERROR, 188 TYPE_MSS_TIMER": 64-bit mode not supported\n"); 189 return; 190 } 191 break; 192 } 193 timer_update_irq(st); 194 } 195 196 static const MemoryRegionOps timer_ops = { 197 .read = timer_read, 198 .write = timer_write, 199 .endianness = DEVICE_NATIVE_ENDIAN, 200 .valid = { 201 .min_access_size = 1, 202 .max_access_size = 4 203 } 204 }; 205 206 static void timer_hit(void *opaque) 207 { 208 struct Msf2Timer *st = opaque; 209 210 st->regs[R_TIM_RIS] |= TIMER_RIS_ACK; 211 212 if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ONESHOT)) { 213 timer_update(st); 214 } 215 timer_update_irq(st); 216 } 217 218 static void mss_timer_init(Object *obj) 219 { 220 MSSTimerState *t = MSS_TIMER(obj); 221 int i; 222 223 /* Init all the ptimers. */ 224 for (i = 0; i < NUM_TIMERS; i++) { 225 struct Msf2Timer *st = &t->timers[i]; 226 227 st->bh = qemu_bh_new(timer_hit, st); 228 st->ptimer = ptimer_init(st->bh, PTIMER_POLICY_DEFAULT); 229 ptimer_set_freq(st->ptimer, t->freq_hz); 230 sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq); 231 } 232 233 memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, TYPE_MSS_TIMER, 234 NUM_TIMERS * R_TIM1_MAX * 4); 235 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio); 236 } 237 238 static const VMStateDescription vmstate_timers = { 239 .name = "mss-timer-block", 240 .version_id = 1, 241 .minimum_version_id = 1, 242 .fields = (VMStateField[]) { 243 VMSTATE_PTIMER(ptimer, struct Msf2Timer), 244 VMSTATE_UINT32_ARRAY(regs, struct Msf2Timer, R_TIM1_MAX), 245 VMSTATE_END_OF_LIST() 246 } 247 }; 248 249 static const VMStateDescription vmstate_mss_timer = { 250 .name = TYPE_MSS_TIMER, 251 .version_id = 1, 252 .minimum_version_id = 1, 253 .fields = (VMStateField[]) { 254 VMSTATE_UINT32(freq_hz, MSSTimerState), 255 VMSTATE_STRUCT_ARRAY(timers, MSSTimerState, NUM_TIMERS, 0, 256 vmstate_timers, struct Msf2Timer), 257 VMSTATE_END_OF_LIST() 258 } 259 }; 260 261 static Property mss_timer_properties[] = { 262 /* Libero GUI shows 100Mhz as default for clocks */ 263 DEFINE_PROP_UINT32("clock-frequency", MSSTimerState, freq_hz, 264 100 * 1000000), 265 DEFINE_PROP_END_OF_LIST(), 266 }; 267 268 static void mss_timer_class_init(ObjectClass *klass, void *data) 269 { 270 DeviceClass *dc = DEVICE_CLASS(klass); 271 272 dc->props = mss_timer_properties; 273 dc->vmsd = &vmstate_mss_timer; 274 } 275 276 static const TypeInfo mss_timer_info = { 277 .name = TYPE_MSS_TIMER, 278 .parent = TYPE_SYS_BUS_DEVICE, 279 .instance_size = sizeof(MSSTimerState), 280 .instance_init = mss_timer_init, 281 .class_init = mss_timer_class_init, 282 }; 283 284 static void mss_timer_register_types(void) 285 { 286 type_register_static(&mss_timer_info); 287 } 288 289 type_init(mss_timer_register_types) 290