1 /* 2 * IMX GPT Timer 3 * 4 * Copyright (c) 2008 OK Labs 5 * Copyright (c) 2011 NICTA Pty Ltd 6 * Originally written by Hans Jiang 7 * Updated by Peter Chubb 8 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> 9 * 10 * This code is licensed under GPL version 2 or later. See 11 * the COPYING file in the top-level directory. 12 * 13 */ 14 15 #include "qemu/osdep.h" 16 #include "hw/timer/imx_gpt.h" 17 #include "hw/misc/imx_ccm.h" 18 #include "qemu/main-loop.h" 19 20 #ifndef DEBUG_IMX_GPT 21 #define DEBUG_IMX_GPT 0 22 #endif 23 24 #define DPRINTF(fmt, args...) \ 25 do { \ 26 if (DEBUG_IMX_GPT) { \ 27 fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_GPT, \ 28 __func__, ##args); \ 29 } \ 30 } while (0) 31 32 static char const *imx_gpt_reg_name(uint32_t reg) 33 { 34 switch (reg) { 35 case 0: 36 return "CR"; 37 case 1: 38 return "PR"; 39 case 2: 40 return "SR"; 41 case 3: 42 return "IR"; 43 case 4: 44 return "OCR1"; 45 case 5: 46 return "OCR2"; 47 case 6: 48 return "OCR3"; 49 case 7: 50 return "ICR1"; 51 case 8: 52 return "ICR2"; 53 case 9: 54 return "CNT"; 55 default: 56 return "[?]"; 57 } 58 } 59 60 static const VMStateDescription vmstate_imx_timer_gpt = { 61 .name = TYPE_IMX_GPT, 62 .version_id = 3, 63 .minimum_version_id = 3, 64 .fields = (VMStateField[]) { 65 VMSTATE_UINT32(cr, IMXGPTState), 66 VMSTATE_UINT32(pr, IMXGPTState), 67 VMSTATE_UINT32(sr, IMXGPTState), 68 VMSTATE_UINT32(ir, IMXGPTState), 69 VMSTATE_UINT32(ocr1, IMXGPTState), 70 VMSTATE_UINT32(ocr2, IMXGPTState), 71 VMSTATE_UINT32(ocr3, IMXGPTState), 72 VMSTATE_UINT32(icr1, IMXGPTState), 73 VMSTATE_UINT32(icr2, IMXGPTState), 74 VMSTATE_UINT32(cnt, IMXGPTState), 75 VMSTATE_UINT32(next_timeout, IMXGPTState), 76 VMSTATE_UINT32(next_int, IMXGPTState), 77 VMSTATE_UINT32(freq, IMXGPTState), 78 VMSTATE_PTIMER(timer, IMXGPTState), 79 VMSTATE_END_OF_LIST() 80 } 81 }; 82 83 static const IMXClk imx_gpt_clocks[] = { 84 CLK_NONE, /* 000 No clock source */ 85 CLK_IPG, /* 001 ipg_clk, 532MHz*/ 86 CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */ 87 CLK_NONE, /* 011 not defined */ 88 CLK_32k, /* 100 ipg_clk_32k */ 89 CLK_NONE, /* 101 not defined */ 90 CLK_NONE, /* 110 not defined */ 91 CLK_NONE, /* 111 not defined */ 92 }; 93 94 static void imx_gpt_set_freq(IMXGPTState *s) 95 { 96 uint32_t clksrc = extract32(s->cr, GPT_CR_CLKSRC_SHIFT, 3); 97 98 s->freq = imx_ccm_get_clock_frequency(s->ccm, 99 imx_gpt_clocks[clksrc]) / (1 + s->pr); 100 101 DPRINTF("Setting clksrc %d to frequency %d\n", clksrc, s->freq); 102 103 if (s->freq) { 104 ptimer_set_freq(s->timer, s->freq); 105 } 106 } 107 108 static void imx_gpt_update_int(IMXGPTState *s) 109 { 110 if ((s->sr & s->ir) && (s->cr & GPT_CR_EN)) { 111 qemu_irq_raise(s->irq); 112 } else { 113 qemu_irq_lower(s->irq); 114 } 115 } 116 117 static uint32_t imx_gpt_update_count(IMXGPTState *s) 118 { 119 s->cnt = s->next_timeout - (uint32_t)ptimer_get_count(s->timer); 120 121 return s->cnt; 122 } 123 124 static inline uint32_t imx_gpt_find_limit(uint32_t count, uint32_t reg, 125 uint32_t timeout) 126 { 127 if ((count < reg) && (timeout > reg)) { 128 timeout = reg; 129 } 130 131 return timeout; 132 } 133 134 static void imx_gpt_compute_next_timeout(IMXGPTState *s, bool event) 135 { 136 uint32_t timeout = GPT_TIMER_MAX; 137 uint32_t count; 138 long long limit; 139 140 if (!(s->cr & GPT_CR_EN)) { 141 /* if not enabled just return */ 142 return; 143 } 144 145 /* update the count */ 146 count = imx_gpt_update_count(s); 147 148 if (event) { 149 /* 150 * This is an event (the ptimer reached 0 and stopped), and the 151 * timer counter is now equal to s->next_timeout. 152 */ 153 if (!(s->cr & GPT_CR_FRR) && (count == s->ocr1)) { 154 /* We are in restart mode and we crossed the compare channel 1 155 * value. We need to reset the counter to 0. 156 */ 157 count = s->cnt = s->next_timeout = 0; 158 } else if (count == GPT_TIMER_MAX) { 159 /* We reached GPT_TIMER_MAX so we need to rollover */ 160 count = s->cnt = s->next_timeout = 0; 161 } 162 } 163 164 /* now, find the next timeout related to count */ 165 166 if (s->ir & GPT_IR_OF1IE) { 167 timeout = imx_gpt_find_limit(count, s->ocr1, timeout); 168 } 169 if (s->ir & GPT_IR_OF2IE) { 170 timeout = imx_gpt_find_limit(count, s->ocr2, timeout); 171 } 172 if (s->ir & GPT_IR_OF3IE) { 173 timeout = imx_gpt_find_limit(count, s->ocr3, timeout); 174 } 175 176 /* find the next set of interrupts to raise for next timer event */ 177 178 s->next_int = 0; 179 if ((s->ir & GPT_IR_OF1IE) && (timeout == s->ocr1)) { 180 s->next_int |= GPT_SR_OF1; 181 } 182 if ((s->ir & GPT_IR_OF2IE) && (timeout == s->ocr2)) { 183 s->next_int |= GPT_SR_OF2; 184 } 185 if ((s->ir & GPT_IR_OF3IE) && (timeout == s->ocr3)) { 186 s->next_int |= GPT_SR_OF3; 187 } 188 if ((s->ir & GPT_IR_ROVIE) && (timeout == GPT_TIMER_MAX)) { 189 s->next_int |= GPT_SR_ROV; 190 } 191 192 /* the new range to count down from */ 193 limit = timeout - imx_gpt_update_count(s); 194 195 if (limit < 0) { 196 /* 197 * if we reach here, then QEMU is running too slow and we pass the 198 * timeout limit while computing it. Let's deliver the interrupt 199 * and compute a new limit. 200 */ 201 s->sr |= s->next_int; 202 203 imx_gpt_compute_next_timeout(s, event); 204 205 imx_gpt_update_int(s); 206 } else { 207 /* New timeout value */ 208 s->next_timeout = timeout; 209 210 /* reset the limit to the computed range */ 211 ptimer_set_limit(s->timer, limit, 1); 212 } 213 } 214 215 static uint64_t imx_gpt_read(void *opaque, hwaddr offset, unsigned size) 216 { 217 IMXGPTState *s = IMX_GPT(opaque); 218 uint32_t reg_value = 0; 219 220 switch (offset >> 2) { 221 case 0: /* Control Register */ 222 reg_value = s->cr; 223 break; 224 225 case 1: /* prescaler */ 226 reg_value = s->pr; 227 break; 228 229 case 2: /* Status Register */ 230 reg_value = s->sr; 231 break; 232 233 case 3: /* Interrupt Register */ 234 reg_value = s->ir; 235 break; 236 237 case 4: /* Output Compare Register 1 */ 238 reg_value = s->ocr1; 239 break; 240 241 case 5: /* Output Compare Register 2 */ 242 reg_value = s->ocr2; 243 break; 244 245 case 6: /* Output Compare Register 3 */ 246 reg_value = s->ocr3; 247 break; 248 249 case 7: /* input Capture Register 1 */ 250 qemu_log_mask(LOG_UNIMP, "[%s]%s: icr1 feature is not implemented\n", 251 TYPE_IMX_GPT, __func__); 252 reg_value = s->icr1; 253 break; 254 255 case 8: /* input Capture Register 2 */ 256 qemu_log_mask(LOG_UNIMP, "[%s]%s: icr2 feature is not implemented\n", 257 TYPE_IMX_GPT, __func__); 258 reg_value = s->icr2; 259 break; 260 261 case 9: /* cnt */ 262 imx_gpt_update_count(s); 263 reg_value = s->cnt; 264 break; 265 266 default: 267 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 268 HWADDR_PRIx "\n", TYPE_IMX_GPT, __func__, offset); 269 break; 270 } 271 272 DPRINTF("(%s) = 0x%08x\n", imx_gpt_reg_name(offset >> 2), reg_value); 273 274 return reg_value; 275 } 276 277 static void imx_gpt_reset(DeviceState *dev) 278 { 279 IMXGPTState *s = IMX_GPT(dev); 280 281 /* stop timer */ 282 ptimer_stop(s->timer); 283 284 /* 285 * Soft reset doesn't touch some bits; hard reset clears them 286 */ 287 s->cr &= ~(GPT_CR_EN|GPT_CR_ENMOD|GPT_CR_STOPEN|GPT_CR_DOZEN| 288 GPT_CR_WAITEN|GPT_CR_DBGEN); 289 s->sr = 0; 290 s->pr = 0; 291 s->ir = 0; 292 s->cnt = 0; 293 s->ocr1 = GPT_TIMER_MAX; 294 s->ocr2 = GPT_TIMER_MAX; 295 s->ocr3 = GPT_TIMER_MAX; 296 s->icr1 = 0; 297 s->icr2 = 0; 298 299 s->next_timeout = GPT_TIMER_MAX; 300 s->next_int = 0; 301 302 /* compute new freq */ 303 imx_gpt_set_freq(s); 304 305 /* reset the limit to GPT_TIMER_MAX */ 306 ptimer_set_limit(s->timer, GPT_TIMER_MAX, 1); 307 308 /* if the timer is still enabled, restart it */ 309 if (s->freq && (s->cr & GPT_CR_EN)) { 310 ptimer_run(s->timer, 1); 311 } 312 } 313 314 static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value, 315 unsigned size) 316 { 317 IMXGPTState *s = IMX_GPT(opaque); 318 uint32_t oldreg; 319 320 DPRINTF("(%s, value = 0x%08x)\n", imx_gpt_reg_name(offset >> 2), 321 (uint32_t)value); 322 323 switch (offset >> 2) { 324 case 0: 325 oldreg = s->cr; 326 s->cr = value & ~0x7c14; 327 if (s->cr & GPT_CR_SWR) { /* force reset */ 328 /* handle the reset */ 329 imx_gpt_reset(DEVICE(s)); 330 } else { 331 /* set our freq, as the source might have changed */ 332 imx_gpt_set_freq(s); 333 334 if ((oldreg ^ s->cr) & GPT_CR_EN) { 335 if (s->cr & GPT_CR_EN) { 336 if (s->cr & GPT_CR_ENMOD) { 337 s->next_timeout = GPT_TIMER_MAX; 338 ptimer_set_count(s->timer, GPT_TIMER_MAX); 339 imx_gpt_compute_next_timeout(s, false); 340 } 341 ptimer_run(s->timer, 1); 342 } else { 343 /* stop timer */ 344 ptimer_stop(s->timer); 345 } 346 } 347 } 348 break; 349 350 case 1: /* Prescaler */ 351 s->pr = value & 0xfff; 352 imx_gpt_set_freq(s); 353 break; 354 355 case 2: /* SR */ 356 s->sr &= ~(value & 0x3f); 357 imx_gpt_update_int(s); 358 break; 359 360 case 3: /* IR -- interrupt register */ 361 s->ir = value & 0x3f; 362 imx_gpt_update_int(s); 363 364 imx_gpt_compute_next_timeout(s, false); 365 366 break; 367 368 case 4: /* OCR1 -- output compare register */ 369 s->ocr1 = value; 370 371 /* In non-freerun mode, reset count when this register is written */ 372 if (!(s->cr & GPT_CR_FRR)) { 373 s->next_timeout = GPT_TIMER_MAX; 374 ptimer_set_limit(s->timer, GPT_TIMER_MAX, 1); 375 } 376 377 /* compute the new timeout */ 378 imx_gpt_compute_next_timeout(s, false); 379 380 break; 381 382 case 5: /* OCR2 -- output compare register */ 383 s->ocr2 = value; 384 385 /* compute the new timeout */ 386 imx_gpt_compute_next_timeout(s, false); 387 388 break; 389 390 case 6: /* OCR3 -- output compare register */ 391 s->ocr3 = value; 392 393 /* compute the new timeout */ 394 imx_gpt_compute_next_timeout(s, false); 395 396 break; 397 398 default: 399 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 400 HWADDR_PRIx "\n", TYPE_IMX_GPT, __func__, offset); 401 break; 402 } 403 } 404 405 static void imx_gpt_timeout(void *opaque) 406 { 407 IMXGPTState *s = IMX_GPT(opaque); 408 409 DPRINTF("\n"); 410 411 s->sr |= s->next_int; 412 s->next_int = 0; 413 414 imx_gpt_compute_next_timeout(s, true); 415 416 imx_gpt_update_int(s); 417 418 if (s->freq && (s->cr & GPT_CR_EN)) { 419 ptimer_run(s->timer, 1); 420 } 421 } 422 423 static const MemoryRegionOps imx_gpt_ops = { 424 .read = imx_gpt_read, 425 .write = imx_gpt_write, 426 .endianness = DEVICE_NATIVE_ENDIAN, 427 }; 428 429 430 static void imx_gpt_realize(DeviceState *dev, Error **errp) 431 { 432 IMXGPTState *s = IMX_GPT(dev); 433 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 434 QEMUBH *bh; 435 436 sysbus_init_irq(sbd, &s->irq); 437 memory_region_init_io(&s->iomem, OBJECT(s), &imx_gpt_ops, s, TYPE_IMX_GPT, 438 0x00001000); 439 sysbus_init_mmio(sbd, &s->iomem); 440 441 bh = qemu_bh_new(imx_gpt_timeout, s); 442 s->timer = ptimer_init(bh); 443 } 444 445 static void imx_gpt_class_init(ObjectClass *klass, void *data) 446 { 447 DeviceClass *dc = DEVICE_CLASS(klass); 448 449 dc->realize = imx_gpt_realize; 450 dc->reset = imx_gpt_reset; 451 dc->vmsd = &vmstate_imx_timer_gpt; 452 dc->desc = "i.MX general timer"; 453 } 454 455 static const TypeInfo imx_gpt_info = { 456 .name = TYPE_IMX_GPT, 457 .parent = TYPE_SYS_BUS_DEVICE, 458 .instance_size = sizeof(IMXGPTState), 459 .class_init = imx_gpt_class_init, 460 }; 461 462 static void imx_gpt_register_types(void) 463 { 464 type_register_static(&imx_gpt_info); 465 } 466 467 type_init(imx_gpt_register_types) 468