1 /* 2 * IMX GPT Timer 3 * 4 * Copyright (c) 2008 OK Labs 5 * Copyright (c) 2011 NICTA Pty Ltd 6 * Originally written by Hans Jiang 7 * Updated by Peter Chubb 8 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> 9 * 10 * This code is licensed under GPL version 2 or later. See 11 * the COPYING file in the top-level directory. 12 * 13 */ 14 15 #include "qemu/osdep.h" 16 #include "hw/irq.h" 17 #include "hw/timer/imx_gpt.h" 18 #include "migration/vmstate.h" 19 #include "qemu/module.h" 20 #include "qemu/log.h" 21 #include "trace.h" 22 23 #ifndef DEBUG_IMX_GPT 24 #define DEBUG_IMX_GPT 0 25 #endif 26 27 static const char *imx_gpt_reg_name(uint32_t reg) 28 { 29 switch (reg) { 30 case 0: 31 return "CR"; 32 case 1: 33 return "PR"; 34 case 2: 35 return "SR"; 36 case 3: 37 return "IR"; 38 case 4: 39 return "OCR1"; 40 case 5: 41 return "OCR2"; 42 case 6: 43 return "OCR3"; 44 case 7: 45 return "ICR1"; 46 case 8: 47 return "ICR2"; 48 case 9: 49 return "CNT"; 50 default: 51 return "[?]"; 52 } 53 } 54 55 static const VMStateDescription vmstate_imx_timer_gpt = { 56 .name = TYPE_IMX_GPT, 57 .version_id = 3, 58 .minimum_version_id = 3, 59 .fields = (const VMStateField[]) { 60 VMSTATE_UINT32(cr, IMXGPTState), 61 VMSTATE_UINT32(pr, IMXGPTState), 62 VMSTATE_UINT32(sr, IMXGPTState), 63 VMSTATE_UINT32(ir, IMXGPTState), 64 VMSTATE_UINT32(ocr1, IMXGPTState), 65 VMSTATE_UINT32(ocr2, IMXGPTState), 66 VMSTATE_UINT32(ocr3, IMXGPTState), 67 VMSTATE_UINT32(icr1, IMXGPTState), 68 VMSTATE_UINT32(icr2, IMXGPTState), 69 VMSTATE_UINT32(cnt, IMXGPTState), 70 VMSTATE_UINT32(next_timeout, IMXGPTState), 71 VMSTATE_UINT32(next_int, IMXGPTState), 72 VMSTATE_UINT32(freq, IMXGPTState), 73 VMSTATE_PTIMER(timer, IMXGPTState), 74 VMSTATE_END_OF_LIST() 75 } 76 }; 77 78 static const IMXClk imx25_gpt_clocks[] = { 79 CLK_NONE, /* 000 No clock source */ 80 CLK_IPG, /* 001 ipg_clk, 532MHz*/ 81 CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */ 82 CLK_NONE, /* 011 not defined */ 83 CLK_32k, /* 100 ipg_clk_32k */ 84 CLK_32k, /* 101 ipg_clk_32k */ 85 CLK_32k, /* 110 ipg_clk_32k */ 86 CLK_32k, /* 111 ipg_clk_32k */ 87 }; 88 89 static const IMXClk imx31_gpt_clocks[] = { 90 CLK_NONE, /* 000 No clock source */ 91 CLK_IPG, /* 001 ipg_clk, 532MHz*/ 92 CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */ 93 CLK_NONE, /* 011 not defined */ 94 CLK_32k, /* 100 ipg_clk_32k */ 95 CLK_NONE, /* 101 not defined */ 96 CLK_NONE, /* 110 not defined */ 97 CLK_NONE, /* 111 not defined */ 98 }; 99 100 static const IMXClk imx6_gpt_clocks[] = { 101 CLK_NONE, /* 000 No clock source */ 102 CLK_IPG, /* 001 ipg_clk, 532MHz*/ 103 CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */ 104 CLK_EXT, /* 011 External clock */ 105 CLK_32k, /* 100 ipg_clk_32k */ 106 CLK_HIGH_DIV, /* 101 reference clock / 8 */ 107 CLK_NONE, /* 110 not defined */ 108 CLK_HIGH, /* 111 reference clock */ 109 }; 110 111 static const IMXClk imx6ul_gpt_clocks[] = { 112 CLK_NONE, /* 000 No clock source */ 113 CLK_IPG, /* 001 ipg_clk, 532MHz*/ 114 CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */ 115 CLK_EXT, /* 011 External clock */ 116 CLK_32k, /* 100 ipg_clk_32k */ 117 CLK_NONE, /* 101 not defined */ 118 CLK_NONE, /* 110 not defined */ 119 CLK_NONE, /* 111 not defined */ 120 }; 121 122 static const IMXClk imx7_gpt_clocks[] = { 123 CLK_NONE, /* 000 No clock source */ 124 CLK_IPG, /* 001 ipg_clk, 532MHz*/ 125 CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */ 126 CLK_EXT, /* 011 External clock */ 127 CLK_32k, /* 100 ipg_clk_32k */ 128 CLK_HIGH, /* 101 reference clock */ 129 CLK_NONE, /* 110 not defined */ 130 CLK_NONE, /* 111 not defined */ 131 }; 132 133 /* Must be called from within ptimer_transaction_begin/commit block */ 134 static void imx_gpt_set_freq(IMXGPTState *s) 135 { 136 uint32_t clksrc = extract32(s->cr, GPT_CR_CLKSRC_SHIFT, 3); 137 138 s->freq = imx_ccm_get_clock_frequency(s->ccm, 139 s->clocks[clksrc]) / (1 + s->pr); 140 141 trace_imx_gpt_set_freq(clksrc, s->freq); 142 143 if (s->freq) { 144 ptimer_set_freq(s->timer, s->freq); 145 } 146 } 147 148 static void imx_gpt_update_int(IMXGPTState *s) 149 { 150 if ((s->sr & s->ir) && (s->cr & GPT_CR_EN)) { 151 qemu_irq_raise(s->irq); 152 } else { 153 qemu_irq_lower(s->irq); 154 } 155 } 156 157 static uint32_t imx_gpt_update_count(IMXGPTState *s) 158 { 159 s->cnt = s->next_timeout - (uint32_t)ptimer_get_count(s->timer); 160 161 return s->cnt; 162 } 163 164 static inline uint32_t imx_gpt_find_limit(uint32_t count, uint32_t reg, 165 uint32_t timeout) 166 { 167 if ((count < reg) && (timeout > reg)) { 168 timeout = reg; 169 } 170 171 return timeout; 172 } 173 174 /* Must be called from within ptimer_transaction_begin/commit block */ 175 static void imx_gpt_compute_next_timeout(IMXGPTState *s, bool event) 176 { 177 uint32_t timeout = GPT_TIMER_MAX; 178 uint32_t count; 179 long long limit; 180 181 if (!(s->cr & GPT_CR_EN)) { 182 /* if not enabled just return */ 183 return; 184 } 185 186 /* update the count */ 187 count = imx_gpt_update_count(s); 188 189 if (event) { 190 /* 191 * This is an event (the ptimer reached 0 and stopped), and the 192 * timer counter is now equal to s->next_timeout. 193 */ 194 if (!(s->cr & GPT_CR_FRR) && (count == s->ocr1)) { 195 /* We are in restart mode and we crossed the compare channel 1 196 * value. We need to reset the counter to 0. 197 */ 198 count = s->cnt = s->next_timeout = 0; 199 } else if (count == GPT_TIMER_MAX) { 200 /* We reached GPT_TIMER_MAX so we need to rollover */ 201 count = s->cnt = s->next_timeout = 0; 202 } 203 } 204 205 /* now, find the next timeout related to count */ 206 207 if (s->ir & GPT_IR_OF1IE) { 208 timeout = imx_gpt_find_limit(count, s->ocr1, timeout); 209 } 210 if (s->ir & GPT_IR_OF2IE) { 211 timeout = imx_gpt_find_limit(count, s->ocr2, timeout); 212 } 213 if (s->ir & GPT_IR_OF3IE) { 214 timeout = imx_gpt_find_limit(count, s->ocr3, timeout); 215 } 216 217 /* find the next set of interrupts to raise for next timer event */ 218 219 s->next_int = 0; 220 if ((s->ir & GPT_IR_OF1IE) && (timeout == s->ocr1)) { 221 s->next_int |= GPT_SR_OF1; 222 } 223 if ((s->ir & GPT_IR_OF2IE) && (timeout == s->ocr2)) { 224 s->next_int |= GPT_SR_OF2; 225 } 226 if ((s->ir & GPT_IR_OF3IE) && (timeout == s->ocr3)) { 227 s->next_int |= GPT_SR_OF3; 228 } 229 if ((s->ir & GPT_IR_ROVIE) && (timeout == GPT_TIMER_MAX)) { 230 s->next_int |= GPT_SR_ROV; 231 } 232 233 /* the new range to count down from */ 234 limit = timeout - imx_gpt_update_count(s); 235 236 if (limit < 0) { 237 /* 238 * if we reach here, then QEMU is running too slow and we pass the 239 * timeout limit while computing it. Let's deliver the interrupt 240 * and compute a new limit. 241 */ 242 s->sr |= s->next_int; 243 244 imx_gpt_compute_next_timeout(s, event); 245 246 imx_gpt_update_int(s); 247 } else { 248 /* New timeout value */ 249 s->next_timeout = timeout; 250 251 /* reset the limit to the computed range */ 252 ptimer_set_limit(s->timer, limit, 1); 253 } 254 } 255 256 static uint64_t imx_gpt_read(void *opaque, hwaddr offset, unsigned size) 257 { 258 IMXGPTState *s = IMX_GPT(opaque); 259 uint32_t reg_value = 0; 260 261 switch (offset >> 2) { 262 case 0: /* Control Register */ 263 reg_value = s->cr; 264 break; 265 266 case 1: /* prescaler */ 267 reg_value = s->pr; 268 break; 269 270 case 2: /* Status Register */ 271 reg_value = s->sr; 272 break; 273 274 case 3: /* Interrupt Register */ 275 reg_value = s->ir; 276 break; 277 278 case 4: /* Output Compare Register 1 */ 279 reg_value = s->ocr1; 280 break; 281 282 case 5: /* Output Compare Register 2 */ 283 reg_value = s->ocr2; 284 break; 285 286 case 6: /* Output Compare Register 3 */ 287 reg_value = s->ocr3; 288 break; 289 290 case 7: /* input Capture Register 1 */ 291 qemu_log_mask(LOG_UNIMP, "[%s]%s: icr1 feature is not implemented\n", 292 TYPE_IMX_GPT, __func__); 293 reg_value = s->icr1; 294 break; 295 296 case 8: /* input Capture Register 2 */ 297 qemu_log_mask(LOG_UNIMP, "[%s]%s: icr2 feature is not implemented\n", 298 TYPE_IMX_GPT, __func__); 299 reg_value = s->icr2; 300 break; 301 302 case 9: /* cnt */ 303 imx_gpt_update_count(s); 304 reg_value = s->cnt; 305 break; 306 307 default: 308 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 309 HWADDR_PRIx "\n", TYPE_IMX_GPT, __func__, offset); 310 break; 311 } 312 313 trace_imx_gpt_read(imx_gpt_reg_name(offset >> 2), reg_value); 314 315 return reg_value; 316 } 317 318 319 static void imx_gpt_reset_common(IMXGPTState *s, bool is_soft_reset) 320 { 321 ptimer_transaction_begin(s->timer); 322 /* stop timer */ 323 ptimer_stop(s->timer); 324 325 /* Soft reset and hard reset differ only in their handling of the CR 326 * register -- soft reset preserves the values of some bits there. 327 */ 328 if (is_soft_reset) { 329 /* Clear all CR bits except those that are preserved by soft reset. */ 330 s->cr &= GPT_CR_EN | GPT_CR_ENMOD | GPT_CR_STOPEN | GPT_CR_DOZEN | 331 GPT_CR_WAITEN | GPT_CR_DBGEN | 332 (GPT_CR_CLKSRC_MASK << GPT_CR_CLKSRC_SHIFT); 333 } else { 334 s->cr = 0; 335 } 336 s->sr = 0; 337 s->pr = 0; 338 s->ir = 0; 339 s->cnt = 0; 340 s->ocr1 = GPT_TIMER_MAX; 341 s->ocr2 = GPT_TIMER_MAX; 342 s->ocr3 = GPT_TIMER_MAX; 343 s->icr1 = 0; 344 s->icr2 = 0; 345 346 s->next_timeout = GPT_TIMER_MAX; 347 s->next_int = 0; 348 349 /* compute new freq */ 350 imx_gpt_set_freq(s); 351 352 /* reset the limit to GPT_TIMER_MAX */ 353 ptimer_set_limit(s->timer, GPT_TIMER_MAX, 1); 354 355 /* if the timer is still enabled, restart it */ 356 if (s->freq && (s->cr & GPT_CR_EN)) { 357 ptimer_run(s->timer, 1); 358 } 359 ptimer_transaction_commit(s->timer); 360 } 361 362 static void imx_gpt_soft_reset(DeviceState *dev) 363 { 364 IMXGPTState *s = IMX_GPT(dev); 365 imx_gpt_reset_common(s, true); 366 } 367 368 static void imx_gpt_reset(DeviceState *dev) 369 { 370 IMXGPTState *s = IMX_GPT(dev); 371 imx_gpt_reset_common(s, false); 372 } 373 374 static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value, 375 unsigned size) 376 { 377 IMXGPTState *s = IMX_GPT(opaque); 378 uint32_t oldreg; 379 380 trace_imx_gpt_write(imx_gpt_reg_name(offset >> 2), (uint32_t)value); 381 382 switch (offset >> 2) { 383 case 0: 384 oldreg = s->cr; 385 s->cr = value & ~0x7c14; 386 if (s->cr & GPT_CR_SWR) { /* force reset */ 387 /* handle the reset */ 388 imx_gpt_soft_reset(DEVICE(s)); 389 } else { 390 /* set our freq, as the source might have changed */ 391 ptimer_transaction_begin(s->timer); 392 imx_gpt_set_freq(s); 393 394 if ((oldreg ^ s->cr) & GPT_CR_EN) { 395 if (s->cr & GPT_CR_EN) { 396 if (s->cr & GPT_CR_ENMOD) { 397 s->next_timeout = GPT_TIMER_MAX; 398 ptimer_set_count(s->timer, GPT_TIMER_MAX); 399 imx_gpt_compute_next_timeout(s, false); 400 } 401 ptimer_run(s->timer, 1); 402 } else { 403 /* stop timer */ 404 ptimer_stop(s->timer); 405 } 406 } 407 ptimer_transaction_commit(s->timer); 408 } 409 break; 410 411 case 1: /* Prescaler */ 412 s->pr = value & 0xfff; 413 ptimer_transaction_begin(s->timer); 414 imx_gpt_set_freq(s); 415 ptimer_transaction_commit(s->timer); 416 break; 417 418 case 2: /* SR */ 419 s->sr &= ~(value & 0x3f); 420 imx_gpt_update_int(s); 421 break; 422 423 case 3: /* IR -- interrupt register */ 424 s->ir = value & 0x3f; 425 imx_gpt_update_int(s); 426 427 ptimer_transaction_begin(s->timer); 428 imx_gpt_compute_next_timeout(s, false); 429 ptimer_transaction_commit(s->timer); 430 431 break; 432 433 case 4: /* OCR1 -- output compare register */ 434 s->ocr1 = value; 435 436 ptimer_transaction_begin(s->timer); 437 /* In non-freerun mode, reset count when this register is written */ 438 if (!(s->cr & GPT_CR_FRR)) { 439 s->next_timeout = GPT_TIMER_MAX; 440 ptimer_set_limit(s->timer, GPT_TIMER_MAX, 1); 441 } 442 443 /* compute the new timeout */ 444 imx_gpt_compute_next_timeout(s, false); 445 ptimer_transaction_commit(s->timer); 446 447 break; 448 449 case 5: /* OCR2 -- output compare register */ 450 s->ocr2 = value; 451 452 /* compute the new timeout */ 453 ptimer_transaction_begin(s->timer); 454 imx_gpt_compute_next_timeout(s, false); 455 ptimer_transaction_commit(s->timer); 456 457 break; 458 459 case 6: /* OCR3 -- output compare register */ 460 s->ocr3 = value; 461 462 /* compute the new timeout */ 463 ptimer_transaction_begin(s->timer); 464 imx_gpt_compute_next_timeout(s, false); 465 ptimer_transaction_commit(s->timer); 466 467 break; 468 469 default: 470 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 471 HWADDR_PRIx "\n", TYPE_IMX_GPT, __func__, offset); 472 break; 473 } 474 } 475 476 static void imx_gpt_timeout(void *opaque) 477 { 478 IMXGPTState *s = IMX_GPT(opaque); 479 480 trace_imx_gpt_timeout(); 481 482 s->sr |= s->next_int; 483 s->next_int = 0; 484 485 imx_gpt_compute_next_timeout(s, true); 486 487 imx_gpt_update_int(s); 488 489 if (s->freq && (s->cr & GPT_CR_EN)) { 490 ptimer_run(s->timer, 1); 491 } 492 } 493 494 static const MemoryRegionOps imx_gpt_ops = { 495 .read = imx_gpt_read, 496 .write = imx_gpt_write, 497 .endianness = DEVICE_NATIVE_ENDIAN, 498 }; 499 500 501 static void imx_gpt_realize(DeviceState *dev, Error **errp) 502 { 503 IMXGPTState *s = IMX_GPT(dev); 504 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 505 506 sysbus_init_irq(sbd, &s->irq); 507 memory_region_init_io(&s->iomem, OBJECT(s), &imx_gpt_ops, s, TYPE_IMX_GPT, 508 0x00001000); 509 sysbus_init_mmio(sbd, &s->iomem); 510 511 s->timer = ptimer_init(imx_gpt_timeout, s, PTIMER_POLICY_LEGACY); 512 } 513 514 static void imx_gpt_class_init(ObjectClass *klass, void *data) 515 { 516 DeviceClass *dc = DEVICE_CLASS(klass); 517 518 dc->realize = imx_gpt_realize; 519 device_class_set_legacy_reset(dc, imx_gpt_reset); 520 dc->vmsd = &vmstate_imx_timer_gpt; 521 dc->desc = "i.MX general timer"; 522 } 523 524 static void imx25_gpt_init(Object *obj) 525 { 526 IMXGPTState *s = IMX_GPT(obj); 527 528 s->clocks = imx25_gpt_clocks; 529 } 530 531 static void imx31_gpt_init(Object *obj) 532 { 533 IMXGPTState *s = IMX_GPT(obj); 534 535 s->clocks = imx31_gpt_clocks; 536 } 537 538 static void imx6_gpt_init(Object *obj) 539 { 540 IMXGPTState *s = IMX_GPT(obj); 541 542 s->clocks = imx6_gpt_clocks; 543 } 544 545 static void imx6ul_gpt_init(Object *obj) 546 { 547 IMXGPTState *s = IMX_GPT(obj); 548 549 s->clocks = imx6ul_gpt_clocks; 550 } 551 552 static void imx7_gpt_init(Object *obj) 553 { 554 IMXGPTState *s = IMX_GPT(obj); 555 556 s->clocks = imx7_gpt_clocks; 557 } 558 559 static const TypeInfo imx25_gpt_info = { 560 .name = TYPE_IMX25_GPT, 561 .parent = TYPE_SYS_BUS_DEVICE, 562 .instance_size = sizeof(IMXGPTState), 563 .instance_init = imx25_gpt_init, 564 .class_init = imx_gpt_class_init, 565 }; 566 567 static const TypeInfo imx31_gpt_info = { 568 .name = TYPE_IMX31_GPT, 569 .parent = TYPE_IMX25_GPT, 570 .instance_init = imx31_gpt_init, 571 }; 572 573 static const TypeInfo imx6_gpt_info = { 574 .name = TYPE_IMX6_GPT, 575 .parent = TYPE_IMX25_GPT, 576 .instance_init = imx6_gpt_init, 577 }; 578 579 static const TypeInfo imx6ul_gpt_info = { 580 .name = TYPE_IMX6UL_GPT, 581 .parent = TYPE_IMX25_GPT, 582 .instance_init = imx6ul_gpt_init, 583 }; 584 585 static const TypeInfo imx7_gpt_info = { 586 .name = TYPE_IMX7_GPT, 587 .parent = TYPE_IMX25_GPT, 588 .instance_init = imx7_gpt_init, 589 }; 590 591 static void imx_gpt_register_types(void) 592 { 593 type_register_static(&imx25_gpt_info); 594 type_register_static(&imx31_gpt_info); 595 type_register_static(&imx6_gpt_info); 596 type_register_static(&imx6ul_gpt_info); 597 type_register_static(&imx7_gpt_info); 598 } 599 600 type_init(imx_gpt_register_types) 601