1 /* 2 * IMX GPT Timer 3 * 4 * Copyright (c) 2008 OK Labs 5 * Copyright (c) 2011 NICTA Pty Ltd 6 * Originally written by Hans Jiang 7 * Updated by Peter Chubb 8 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> 9 * 10 * This code is licensed under GPL version 2 or later. See 11 * the COPYING file in the top-level directory. 12 * 13 */ 14 15 #include "qemu/osdep.h" 16 #include "hw/timer/imx_gpt.h" 17 #include "qemu/main-loop.h" 18 #include "qemu/log.h" 19 20 #ifndef DEBUG_IMX_GPT 21 #define DEBUG_IMX_GPT 0 22 #endif 23 24 #define DPRINTF(fmt, args...) \ 25 do { \ 26 if (DEBUG_IMX_GPT) { \ 27 fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_GPT, \ 28 __func__, ##args); \ 29 } \ 30 } while (0) 31 32 static const char *imx_gpt_reg_name(uint32_t reg) 33 { 34 switch (reg) { 35 case 0: 36 return "CR"; 37 case 1: 38 return "PR"; 39 case 2: 40 return "SR"; 41 case 3: 42 return "IR"; 43 case 4: 44 return "OCR1"; 45 case 5: 46 return "OCR2"; 47 case 6: 48 return "OCR3"; 49 case 7: 50 return "ICR1"; 51 case 8: 52 return "ICR2"; 53 case 9: 54 return "CNT"; 55 default: 56 return "[?]"; 57 } 58 } 59 60 static const VMStateDescription vmstate_imx_timer_gpt = { 61 .name = TYPE_IMX_GPT, 62 .version_id = 3, 63 .minimum_version_id = 3, 64 .fields = (VMStateField[]) { 65 VMSTATE_UINT32(cr, IMXGPTState), 66 VMSTATE_UINT32(pr, IMXGPTState), 67 VMSTATE_UINT32(sr, IMXGPTState), 68 VMSTATE_UINT32(ir, IMXGPTState), 69 VMSTATE_UINT32(ocr1, IMXGPTState), 70 VMSTATE_UINT32(ocr2, IMXGPTState), 71 VMSTATE_UINT32(ocr3, IMXGPTState), 72 VMSTATE_UINT32(icr1, IMXGPTState), 73 VMSTATE_UINT32(icr2, IMXGPTState), 74 VMSTATE_UINT32(cnt, IMXGPTState), 75 VMSTATE_UINT32(next_timeout, IMXGPTState), 76 VMSTATE_UINT32(next_int, IMXGPTState), 77 VMSTATE_UINT32(freq, IMXGPTState), 78 VMSTATE_PTIMER(timer, IMXGPTState), 79 VMSTATE_END_OF_LIST() 80 } 81 }; 82 83 static const IMXClk imx25_gpt_clocks[] = { 84 CLK_NONE, /* 000 No clock source */ 85 CLK_IPG, /* 001 ipg_clk, 532MHz*/ 86 CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */ 87 CLK_NONE, /* 011 not defined */ 88 CLK_32k, /* 100 ipg_clk_32k */ 89 CLK_32k, /* 101 ipg_clk_32k */ 90 CLK_32k, /* 110 ipg_clk_32k */ 91 CLK_32k, /* 111 ipg_clk_32k */ 92 }; 93 94 static const IMXClk imx31_gpt_clocks[] = { 95 CLK_NONE, /* 000 No clock source */ 96 CLK_IPG, /* 001 ipg_clk, 532MHz*/ 97 CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */ 98 CLK_NONE, /* 011 not defined */ 99 CLK_32k, /* 100 ipg_clk_32k */ 100 CLK_NONE, /* 101 not defined */ 101 CLK_NONE, /* 110 not defined */ 102 CLK_NONE, /* 111 not defined */ 103 }; 104 105 static const IMXClk imx6_gpt_clocks[] = { 106 CLK_NONE, /* 000 No clock source */ 107 CLK_IPG, /* 001 ipg_clk, 532MHz*/ 108 CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */ 109 CLK_EXT, /* 011 External clock */ 110 CLK_32k, /* 100 ipg_clk_32k */ 111 CLK_HIGH_DIV, /* 101 reference clock / 8 */ 112 CLK_NONE, /* 110 not defined */ 113 CLK_HIGH, /* 111 reference clock */ 114 }; 115 116 static void imx_gpt_set_freq(IMXGPTState *s) 117 { 118 uint32_t clksrc = extract32(s->cr, GPT_CR_CLKSRC_SHIFT, 3); 119 120 s->freq = imx_ccm_get_clock_frequency(s->ccm, 121 s->clocks[clksrc]) / (1 + s->pr); 122 123 DPRINTF("Setting clksrc %d to frequency %d\n", clksrc, s->freq); 124 125 if (s->freq) { 126 ptimer_set_freq(s->timer, s->freq); 127 } 128 } 129 130 static void imx_gpt_update_int(IMXGPTState *s) 131 { 132 if ((s->sr & s->ir) && (s->cr & GPT_CR_EN)) { 133 qemu_irq_raise(s->irq); 134 } else { 135 qemu_irq_lower(s->irq); 136 } 137 } 138 139 static uint32_t imx_gpt_update_count(IMXGPTState *s) 140 { 141 s->cnt = s->next_timeout - (uint32_t)ptimer_get_count(s->timer); 142 143 return s->cnt; 144 } 145 146 static inline uint32_t imx_gpt_find_limit(uint32_t count, uint32_t reg, 147 uint32_t timeout) 148 { 149 if ((count < reg) && (timeout > reg)) { 150 timeout = reg; 151 } 152 153 return timeout; 154 } 155 156 static void imx_gpt_compute_next_timeout(IMXGPTState *s, bool event) 157 { 158 uint32_t timeout = GPT_TIMER_MAX; 159 uint32_t count; 160 long long limit; 161 162 if (!(s->cr & GPT_CR_EN)) { 163 /* if not enabled just return */ 164 return; 165 } 166 167 /* update the count */ 168 count = imx_gpt_update_count(s); 169 170 if (event) { 171 /* 172 * This is an event (the ptimer reached 0 and stopped), and the 173 * timer counter is now equal to s->next_timeout. 174 */ 175 if (!(s->cr & GPT_CR_FRR) && (count == s->ocr1)) { 176 /* We are in restart mode and we crossed the compare channel 1 177 * value. We need to reset the counter to 0. 178 */ 179 count = s->cnt = s->next_timeout = 0; 180 } else if (count == GPT_TIMER_MAX) { 181 /* We reached GPT_TIMER_MAX so we need to rollover */ 182 count = s->cnt = s->next_timeout = 0; 183 } 184 } 185 186 /* now, find the next timeout related to count */ 187 188 if (s->ir & GPT_IR_OF1IE) { 189 timeout = imx_gpt_find_limit(count, s->ocr1, timeout); 190 } 191 if (s->ir & GPT_IR_OF2IE) { 192 timeout = imx_gpt_find_limit(count, s->ocr2, timeout); 193 } 194 if (s->ir & GPT_IR_OF3IE) { 195 timeout = imx_gpt_find_limit(count, s->ocr3, timeout); 196 } 197 198 /* find the next set of interrupts to raise for next timer event */ 199 200 s->next_int = 0; 201 if ((s->ir & GPT_IR_OF1IE) && (timeout == s->ocr1)) { 202 s->next_int |= GPT_SR_OF1; 203 } 204 if ((s->ir & GPT_IR_OF2IE) && (timeout == s->ocr2)) { 205 s->next_int |= GPT_SR_OF2; 206 } 207 if ((s->ir & GPT_IR_OF3IE) && (timeout == s->ocr3)) { 208 s->next_int |= GPT_SR_OF3; 209 } 210 if ((s->ir & GPT_IR_ROVIE) && (timeout == GPT_TIMER_MAX)) { 211 s->next_int |= GPT_SR_ROV; 212 } 213 214 /* the new range to count down from */ 215 limit = timeout - imx_gpt_update_count(s); 216 217 if (limit < 0) { 218 /* 219 * if we reach here, then QEMU is running too slow and we pass the 220 * timeout limit while computing it. Let's deliver the interrupt 221 * and compute a new limit. 222 */ 223 s->sr |= s->next_int; 224 225 imx_gpt_compute_next_timeout(s, event); 226 227 imx_gpt_update_int(s); 228 } else { 229 /* New timeout value */ 230 s->next_timeout = timeout; 231 232 /* reset the limit to the computed range */ 233 ptimer_set_limit(s->timer, limit, 1); 234 } 235 } 236 237 static uint64_t imx_gpt_read(void *opaque, hwaddr offset, unsigned size) 238 { 239 IMXGPTState *s = IMX_GPT(opaque); 240 uint32_t reg_value = 0; 241 242 switch (offset >> 2) { 243 case 0: /* Control Register */ 244 reg_value = s->cr; 245 break; 246 247 case 1: /* prescaler */ 248 reg_value = s->pr; 249 break; 250 251 case 2: /* Status Register */ 252 reg_value = s->sr; 253 break; 254 255 case 3: /* Interrupt Register */ 256 reg_value = s->ir; 257 break; 258 259 case 4: /* Output Compare Register 1 */ 260 reg_value = s->ocr1; 261 break; 262 263 case 5: /* Output Compare Register 2 */ 264 reg_value = s->ocr2; 265 break; 266 267 case 6: /* Output Compare Register 3 */ 268 reg_value = s->ocr3; 269 break; 270 271 case 7: /* input Capture Register 1 */ 272 qemu_log_mask(LOG_UNIMP, "[%s]%s: icr1 feature is not implemented\n", 273 TYPE_IMX_GPT, __func__); 274 reg_value = s->icr1; 275 break; 276 277 case 8: /* input Capture Register 2 */ 278 qemu_log_mask(LOG_UNIMP, "[%s]%s: icr2 feature is not implemented\n", 279 TYPE_IMX_GPT, __func__); 280 reg_value = s->icr2; 281 break; 282 283 case 9: /* cnt */ 284 imx_gpt_update_count(s); 285 reg_value = s->cnt; 286 break; 287 288 default: 289 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 290 HWADDR_PRIx "\n", TYPE_IMX_GPT, __func__, offset); 291 break; 292 } 293 294 DPRINTF("(%s) = 0x%08x\n", imx_gpt_reg_name(offset >> 2), reg_value); 295 296 return reg_value; 297 } 298 299 300 static void imx_gpt_reset_common(IMXGPTState *s, bool is_soft_reset) 301 { 302 /* stop timer */ 303 ptimer_stop(s->timer); 304 305 /* Soft reset and hard reset differ only in their handling of the CR 306 * register -- soft reset preserves the values of some bits there. 307 */ 308 if (is_soft_reset) { 309 /* Clear all CR bits except those that are preserved by soft reset. */ 310 s->cr &= GPT_CR_EN | GPT_CR_ENMOD | GPT_CR_STOPEN | GPT_CR_DOZEN | 311 GPT_CR_WAITEN | GPT_CR_DBGEN | 312 (GPT_CR_CLKSRC_MASK << GPT_CR_CLKSRC_SHIFT); 313 } else { 314 s->cr = 0; 315 } 316 s->sr = 0; 317 s->pr = 0; 318 s->ir = 0; 319 s->cnt = 0; 320 s->ocr1 = GPT_TIMER_MAX; 321 s->ocr2 = GPT_TIMER_MAX; 322 s->ocr3 = GPT_TIMER_MAX; 323 s->icr1 = 0; 324 s->icr2 = 0; 325 326 s->next_timeout = GPT_TIMER_MAX; 327 s->next_int = 0; 328 329 /* compute new freq */ 330 imx_gpt_set_freq(s); 331 332 /* reset the limit to GPT_TIMER_MAX */ 333 ptimer_set_limit(s->timer, GPT_TIMER_MAX, 1); 334 335 /* if the timer is still enabled, restart it */ 336 if (s->freq && (s->cr & GPT_CR_EN)) { 337 ptimer_run(s->timer, 1); 338 } 339 } 340 341 static void imx_gpt_soft_reset(DeviceState *dev) 342 { 343 IMXGPTState *s = IMX_GPT(dev); 344 imx_gpt_reset_common(s, true); 345 } 346 347 static void imx_gpt_reset(DeviceState *dev) 348 { 349 IMXGPTState *s = IMX_GPT(dev); 350 imx_gpt_reset_common(s, false); 351 } 352 353 static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value, 354 unsigned size) 355 { 356 IMXGPTState *s = IMX_GPT(opaque); 357 uint32_t oldreg; 358 359 DPRINTF("(%s, value = 0x%08x)\n", imx_gpt_reg_name(offset >> 2), 360 (uint32_t)value); 361 362 switch (offset >> 2) { 363 case 0: 364 oldreg = s->cr; 365 s->cr = value & ~0x7c14; 366 if (s->cr & GPT_CR_SWR) { /* force reset */ 367 /* handle the reset */ 368 imx_gpt_soft_reset(DEVICE(s)); 369 } else { 370 /* set our freq, as the source might have changed */ 371 imx_gpt_set_freq(s); 372 373 if ((oldreg ^ s->cr) & GPT_CR_EN) { 374 if (s->cr & GPT_CR_EN) { 375 if (s->cr & GPT_CR_ENMOD) { 376 s->next_timeout = GPT_TIMER_MAX; 377 ptimer_set_count(s->timer, GPT_TIMER_MAX); 378 imx_gpt_compute_next_timeout(s, false); 379 } 380 ptimer_run(s->timer, 1); 381 } else { 382 /* stop timer */ 383 ptimer_stop(s->timer); 384 } 385 } 386 } 387 break; 388 389 case 1: /* Prescaler */ 390 s->pr = value & 0xfff; 391 imx_gpt_set_freq(s); 392 break; 393 394 case 2: /* SR */ 395 s->sr &= ~(value & 0x3f); 396 imx_gpt_update_int(s); 397 break; 398 399 case 3: /* IR -- interrupt register */ 400 s->ir = value & 0x3f; 401 imx_gpt_update_int(s); 402 403 imx_gpt_compute_next_timeout(s, false); 404 405 break; 406 407 case 4: /* OCR1 -- output compare register */ 408 s->ocr1 = value; 409 410 /* In non-freerun mode, reset count when this register is written */ 411 if (!(s->cr & GPT_CR_FRR)) { 412 s->next_timeout = GPT_TIMER_MAX; 413 ptimer_set_limit(s->timer, GPT_TIMER_MAX, 1); 414 } 415 416 /* compute the new timeout */ 417 imx_gpt_compute_next_timeout(s, false); 418 419 break; 420 421 case 5: /* OCR2 -- output compare register */ 422 s->ocr2 = value; 423 424 /* compute the new timeout */ 425 imx_gpt_compute_next_timeout(s, false); 426 427 break; 428 429 case 6: /* OCR3 -- output compare register */ 430 s->ocr3 = value; 431 432 /* compute the new timeout */ 433 imx_gpt_compute_next_timeout(s, false); 434 435 break; 436 437 default: 438 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 439 HWADDR_PRIx "\n", TYPE_IMX_GPT, __func__, offset); 440 break; 441 } 442 } 443 444 static void imx_gpt_timeout(void *opaque) 445 { 446 IMXGPTState *s = IMX_GPT(opaque); 447 448 DPRINTF("\n"); 449 450 s->sr |= s->next_int; 451 s->next_int = 0; 452 453 imx_gpt_compute_next_timeout(s, true); 454 455 imx_gpt_update_int(s); 456 457 if (s->freq && (s->cr & GPT_CR_EN)) { 458 ptimer_run(s->timer, 1); 459 } 460 } 461 462 static const MemoryRegionOps imx_gpt_ops = { 463 .read = imx_gpt_read, 464 .write = imx_gpt_write, 465 .endianness = DEVICE_NATIVE_ENDIAN, 466 }; 467 468 469 static void imx_gpt_realize(DeviceState *dev, Error **errp) 470 { 471 IMXGPTState *s = IMX_GPT(dev); 472 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 473 QEMUBH *bh; 474 475 sysbus_init_irq(sbd, &s->irq); 476 memory_region_init_io(&s->iomem, OBJECT(s), &imx_gpt_ops, s, TYPE_IMX_GPT, 477 0x00001000); 478 sysbus_init_mmio(sbd, &s->iomem); 479 480 bh = qemu_bh_new(imx_gpt_timeout, s); 481 s->timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); 482 } 483 484 static void imx_gpt_class_init(ObjectClass *klass, void *data) 485 { 486 DeviceClass *dc = DEVICE_CLASS(klass); 487 488 dc->realize = imx_gpt_realize; 489 dc->reset = imx_gpt_reset; 490 dc->vmsd = &vmstate_imx_timer_gpt; 491 dc->desc = "i.MX general timer"; 492 } 493 494 static void imx25_gpt_init(Object *obj) 495 { 496 IMXGPTState *s = IMX_GPT(obj); 497 498 s->clocks = imx25_gpt_clocks; 499 } 500 501 static void imx31_gpt_init(Object *obj) 502 { 503 IMXGPTState *s = IMX_GPT(obj); 504 505 s->clocks = imx31_gpt_clocks; 506 } 507 508 static void imx6_gpt_init(Object *obj) 509 { 510 IMXGPTState *s = IMX_GPT(obj); 511 512 s->clocks = imx6_gpt_clocks; 513 } 514 515 static const TypeInfo imx25_gpt_info = { 516 .name = TYPE_IMX25_GPT, 517 .parent = TYPE_SYS_BUS_DEVICE, 518 .instance_size = sizeof(IMXGPTState), 519 .instance_init = imx25_gpt_init, 520 .class_init = imx_gpt_class_init, 521 }; 522 523 static const TypeInfo imx31_gpt_info = { 524 .name = TYPE_IMX31_GPT, 525 .parent = TYPE_IMX25_GPT, 526 .instance_init = imx31_gpt_init, 527 }; 528 529 static const TypeInfo imx6_gpt_info = { 530 .name = TYPE_IMX6_GPT, 531 .parent = TYPE_IMX25_GPT, 532 .instance_init = imx6_gpt_init, 533 }; 534 535 static void imx_gpt_register_types(void) 536 { 537 type_register_static(&imx25_gpt_info); 538 type_register_static(&imx31_gpt_info); 539 type_register_static(&imx6_gpt_info); 540 } 541 542 type_init(imx_gpt_register_types) 543