1 /* 2 * IMX GPT Timer 3 * 4 * Copyright (c) 2008 OK Labs 5 * Copyright (c) 2011 NICTA Pty Ltd 6 * Originally written by Hans Jiang 7 * Updated by Peter Chubb 8 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> 9 * 10 * This code is licensed under GPL version 2 or later. See 11 * the COPYING file in the top-level directory. 12 * 13 */ 14 15 #include "hw/arm/imx.h" 16 #include "hw/timer/imx_gpt.h" 17 #include "hw/misc/imx_ccm.h" 18 #include "qemu/main-loop.h" 19 20 /* 21 * Define to 1 for debug messages 22 */ 23 #define DEBUG_TIMER 0 24 #if DEBUG_TIMER 25 26 static char const *imx_gpt_reg_name(uint32_t reg) 27 { 28 switch (reg) { 29 case 0: 30 return "CR"; 31 case 1: 32 return "PR"; 33 case 2: 34 return "SR"; 35 case 3: 36 return "IR"; 37 case 4: 38 return "OCR1"; 39 case 5: 40 return "OCR2"; 41 case 6: 42 return "OCR3"; 43 case 7: 44 return "ICR1"; 45 case 8: 46 return "ICR2"; 47 case 9: 48 return "CNT"; 49 default: 50 return "[?]"; 51 } 52 } 53 54 # define DPRINTF(fmt, args...) \ 55 do { printf("%s: " fmt , __func__, ##args); } while (0) 56 #else 57 # define DPRINTF(fmt, args...) do {} while (0) 58 #endif 59 60 /* 61 * Define to 1 for messages about attempts to 62 * access unimplemented registers or similar. 63 */ 64 #define DEBUG_IMPLEMENTATION 1 65 #if DEBUG_IMPLEMENTATION 66 # define IPRINTF(fmt, args...) \ 67 do { fprintf(stderr, "%s: " fmt, __func__, ##args); } while (0) 68 #else 69 # define IPRINTF(fmt, args...) do {} while (0) 70 #endif 71 72 static const VMStateDescription vmstate_imx_timer_gpt = { 73 .name = TYPE_IMX_GPT, 74 .version_id = 3, 75 .minimum_version_id = 3, 76 .fields = (VMStateField[]) { 77 VMSTATE_UINT32(cr, IMXGPTState), 78 VMSTATE_UINT32(pr, IMXGPTState), 79 VMSTATE_UINT32(sr, IMXGPTState), 80 VMSTATE_UINT32(ir, IMXGPTState), 81 VMSTATE_UINT32(ocr1, IMXGPTState), 82 VMSTATE_UINT32(ocr2, IMXGPTState), 83 VMSTATE_UINT32(ocr3, IMXGPTState), 84 VMSTATE_UINT32(icr1, IMXGPTState), 85 VMSTATE_UINT32(icr2, IMXGPTState), 86 VMSTATE_UINT32(cnt, IMXGPTState), 87 VMSTATE_UINT32(next_timeout, IMXGPTState), 88 VMSTATE_UINT32(next_int, IMXGPTState), 89 VMSTATE_UINT32(freq, IMXGPTState), 90 VMSTATE_PTIMER(timer, IMXGPTState), 91 VMSTATE_END_OF_LIST() 92 } 93 }; 94 95 static const IMXClk imx_gpt_clocks[] = { 96 NOCLK, /* 000 No clock source */ 97 IPG, /* 001 ipg_clk, 532MHz*/ 98 IPG, /* 010 ipg_clk_highfreq */ 99 NOCLK, /* 011 not defined */ 100 CLK_32k, /* 100 ipg_clk_32k */ 101 NOCLK, /* 101 not defined */ 102 NOCLK, /* 110 not defined */ 103 NOCLK, /* 111 not defined */ 104 }; 105 106 static void imx_gpt_set_freq(IMXGPTState *s) 107 { 108 uint32_t clksrc = extract32(s->cr, GPT_CR_CLKSRC_SHIFT, 3); 109 uint32_t freq = imx_clock_frequency(s->ccm, imx_gpt_clocks[clksrc]) 110 / (1 + s->pr); 111 s->freq = freq; 112 113 DPRINTF("Setting clksrc %d to frequency %d\n", clksrc, freq); 114 115 if (freq) { 116 ptimer_set_freq(s->timer, freq); 117 } 118 } 119 120 static void imx_gpt_update_int(IMXGPTState *s) 121 { 122 if ((s->sr & s->ir) && (s->cr & GPT_CR_EN)) { 123 qemu_irq_raise(s->irq); 124 } else { 125 qemu_irq_lower(s->irq); 126 } 127 } 128 129 static uint32_t imx_gpt_update_count(IMXGPTState *s) 130 { 131 s->cnt = s->next_timeout - (uint32_t)ptimer_get_count(s->timer); 132 133 return s->cnt; 134 } 135 136 static inline uint32_t imx_gpt_find_limit(uint32_t count, uint32_t reg, 137 uint32_t timeout) 138 { 139 if ((count < reg) && (timeout > reg)) { 140 timeout = reg; 141 } 142 143 return timeout; 144 } 145 146 static void imx_gpt_compute_next_timeout(IMXGPTState *s, bool event) 147 { 148 uint32_t timeout = GPT_TIMER_MAX; 149 uint32_t count = 0; 150 long long limit; 151 152 if (!(s->cr & GPT_CR_EN)) { 153 /* if not enabled just return */ 154 return; 155 } 156 157 if (event) { 158 /* This is a timer event */ 159 160 if ((s->cr & GPT_CR_FRR) && (s->next_timeout != GPT_TIMER_MAX)) { 161 /* 162 * if we are in free running mode and we have not reached 163 * the GPT_TIMER_MAX limit, then update the count 164 */ 165 count = imx_gpt_update_count(s); 166 } 167 } else { 168 /* not a timer event, then just update the count */ 169 170 count = imx_gpt_update_count(s); 171 } 172 173 /* now, find the next timeout related to count */ 174 175 if (s->ir & GPT_IR_OF1IE) { 176 timeout = imx_gpt_find_limit(count, s->ocr1, timeout); 177 } 178 if (s->ir & GPT_IR_OF2IE) { 179 timeout = imx_gpt_find_limit(count, s->ocr2, timeout); 180 } 181 if (s->ir & GPT_IR_OF3IE) { 182 timeout = imx_gpt_find_limit(count, s->ocr3, timeout); 183 } 184 185 /* find the next set of interrupts to raise for next timer event */ 186 187 s->next_int = 0; 188 if ((s->ir & GPT_IR_OF1IE) && (timeout == s->ocr1)) { 189 s->next_int |= GPT_SR_OF1; 190 } 191 if ((s->ir & GPT_IR_OF2IE) && (timeout == s->ocr2)) { 192 s->next_int |= GPT_SR_OF2; 193 } 194 if ((s->ir & GPT_IR_OF3IE) && (timeout == s->ocr3)) { 195 s->next_int |= GPT_SR_OF3; 196 } 197 if ((s->ir & GPT_IR_ROVIE) && (timeout == GPT_TIMER_MAX)) { 198 s->next_int |= GPT_SR_ROV; 199 } 200 201 /* the new range to count down from */ 202 limit = timeout - imx_gpt_update_count(s); 203 204 if (limit < 0) { 205 /* 206 * if we reach here, then QEMU is running too slow and we pass the 207 * timeout limit while computing it. Let's deliver the interrupt 208 * and compute a new limit. 209 */ 210 s->sr |= s->next_int; 211 212 imx_gpt_compute_next_timeout(s, event); 213 214 imx_gpt_update_int(s); 215 } else { 216 /* New timeout value */ 217 s->next_timeout = timeout; 218 219 /* reset the limit to the computed range */ 220 ptimer_set_limit(s->timer, limit, 1); 221 } 222 } 223 224 static uint64_t imx_gpt_read(void *opaque, hwaddr offset, unsigned size) 225 { 226 IMXGPTState *s = IMX_GPT(opaque); 227 uint32_t reg_value = 0; 228 uint32_t reg = offset >> 2; 229 230 switch (reg) { 231 case 0: /* Control Register */ 232 reg_value = s->cr; 233 break; 234 235 case 1: /* prescaler */ 236 reg_value = s->pr; 237 break; 238 239 case 2: /* Status Register */ 240 reg_value = s->sr; 241 break; 242 243 case 3: /* Interrupt Register */ 244 reg_value = s->ir; 245 break; 246 247 case 4: /* Output Compare Register 1 */ 248 reg_value = s->ocr1; 249 break; 250 251 case 5: /* Output Compare Register 2 */ 252 reg_value = s->ocr2; 253 break; 254 255 case 6: /* Output Compare Register 3 */ 256 reg_value = s->ocr3; 257 break; 258 259 case 7: /* input Capture Register 1 */ 260 qemu_log_mask(LOG_UNIMP, "icr1 feature is not implemented\n"); 261 reg_value = s->icr1; 262 break; 263 264 case 8: /* input Capture Register 2 */ 265 qemu_log_mask(LOG_UNIMP, "icr2 feature is not implemented\n"); 266 reg_value = s->icr2; 267 break; 268 269 case 9: /* cnt */ 270 imx_gpt_update_count(s); 271 reg_value = s->cnt; 272 break; 273 274 default: 275 IPRINTF("Bad offset %x\n", reg); 276 break; 277 } 278 279 DPRINTF("(%s) = 0x%08x\n", imx_gpt_reg_name(reg), reg_value); 280 281 return reg_value; 282 } 283 284 static void imx_gpt_reset(DeviceState *dev) 285 { 286 IMXGPTState *s = IMX_GPT(dev); 287 288 /* stop timer */ 289 ptimer_stop(s->timer); 290 291 /* 292 * Soft reset doesn't touch some bits; hard reset clears them 293 */ 294 s->cr &= ~(GPT_CR_EN|GPT_CR_ENMOD|GPT_CR_STOPEN|GPT_CR_DOZEN| 295 GPT_CR_WAITEN|GPT_CR_DBGEN); 296 s->sr = 0; 297 s->pr = 0; 298 s->ir = 0; 299 s->cnt = 0; 300 s->ocr1 = GPT_TIMER_MAX; 301 s->ocr2 = GPT_TIMER_MAX; 302 s->ocr3 = GPT_TIMER_MAX; 303 s->icr1 = 0; 304 s->icr2 = 0; 305 306 s->next_timeout = GPT_TIMER_MAX; 307 s->next_int = 0; 308 309 /* compute new freq */ 310 imx_gpt_set_freq(s); 311 312 /* reset the limit to GPT_TIMER_MAX */ 313 ptimer_set_limit(s->timer, GPT_TIMER_MAX, 1); 314 315 /* if the timer is still enabled, restart it */ 316 if (s->freq && (s->cr & GPT_CR_EN)) { 317 ptimer_run(s->timer, 1); 318 } 319 } 320 321 static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value, 322 unsigned size) 323 { 324 IMXGPTState *s = IMX_GPT(opaque); 325 uint32_t oldreg; 326 uint32_t reg = offset >> 2; 327 328 DPRINTF("(%s, value = 0x%08x)\n", imx_gpt_reg_name(reg), 329 (uint32_t)value); 330 331 switch (reg) { 332 case 0: 333 oldreg = s->cr; 334 s->cr = value & ~0x7c14; 335 if (s->cr & GPT_CR_SWR) { /* force reset */ 336 /* handle the reset */ 337 imx_gpt_reset(DEVICE(s)); 338 } else { 339 /* set our freq, as the source might have changed */ 340 imx_gpt_set_freq(s); 341 342 if ((oldreg ^ s->cr) & GPT_CR_EN) { 343 if (s->cr & GPT_CR_EN) { 344 if (s->cr & GPT_CR_ENMOD) { 345 s->next_timeout = GPT_TIMER_MAX; 346 ptimer_set_count(s->timer, GPT_TIMER_MAX); 347 imx_gpt_compute_next_timeout(s, false); 348 } 349 ptimer_run(s->timer, 1); 350 } else { 351 /* stop timer */ 352 ptimer_stop(s->timer); 353 } 354 } 355 } 356 break; 357 358 case 1: /* Prescaler */ 359 s->pr = value & 0xfff; 360 imx_gpt_set_freq(s); 361 break; 362 363 case 2: /* SR */ 364 s->sr &= ~(value & 0x3f); 365 imx_gpt_update_int(s); 366 break; 367 368 case 3: /* IR -- interrupt register */ 369 s->ir = value & 0x3f; 370 imx_gpt_update_int(s); 371 372 imx_gpt_compute_next_timeout(s, false); 373 374 break; 375 376 case 4: /* OCR1 -- output compare register */ 377 s->ocr1 = value; 378 379 /* In non-freerun mode, reset count when this register is written */ 380 if (!(s->cr & GPT_CR_FRR)) { 381 s->next_timeout = GPT_TIMER_MAX; 382 ptimer_set_limit(s->timer, GPT_TIMER_MAX, 1); 383 } 384 385 /* compute the new timeout */ 386 imx_gpt_compute_next_timeout(s, false); 387 388 break; 389 390 case 5: /* OCR2 -- output compare register */ 391 s->ocr2 = value; 392 393 /* compute the new timeout */ 394 imx_gpt_compute_next_timeout(s, false); 395 396 break; 397 398 case 6: /* OCR3 -- output compare register */ 399 s->ocr3 = value; 400 401 /* compute the new timeout */ 402 imx_gpt_compute_next_timeout(s, false); 403 404 break; 405 406 default: 407 IPRINTF("Bad offset %x\n", reg); 408 break; 409 } 410 } 411 412 static void imx_gpt_timeout(void *opaque) 413 { 414 IMXGPTState *s = IMX_GPT(opaque); 415 416 DPRINTF("\n"); 417 418 s->sr |= s->next_int; 419 s->next_int = 0; 420 421 imx_gpt_compute_next_timeout(s, true); 422 423 imx_gpt_update_int(s); 424 425 if (s->freq && (s->cr & GPT_CR_EN)) { 426 ptimer_run(s->timer, 1); 427 } 428 } 429 430 static const MemoryRegionOps imx_gpt_ops = { 431 .read = imx_gpt_read, 432 .write = imx_gpt_write, 433 .endianness = DEVICE_NATIVE_ENDIAN, 434 }; 435 436 437 static void imx_gpt_realize(DeviceState *dev, Error **errp) 438 { 439 IMXGPTState *s = IMX_GPT(dev); 440 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 441 QEMUBH *bh; 442 443 sysbus_init_irq(sbd, &s->irq); 444 memory_region_init_io(&s->iomem, OBJECT(s), &imx_gpt_ops, s, TYPE_IMX_GPT, 445 0x00001000); 446 sysbus_init_mmio(sbd, &s->iomem); 447 448 bh = qemu_bh_new(imx_gpt_timeout, s); 449 s->timer = ptimer_init(bh); 450 } 451 452 void imx_timerg_create(const hwaddr addr, qemu_irq irq, DeviceState *ccm) 453 { 454 IMXGPTState *pp; 455 DeviceState *dev; 456 457 dev = sysbus_create_simple(TYPE_IMX_GPT, addr, irq); 458 pp = IMX_GPT(dev); 459 pp->ccm = ccm; 460 } 461 462 static void imx_gpt_class_init(ObjectClass *klass, void *data) 463 { 464 DeviceClass *dc = DEVICE_CLASS(klass); 465 466 dc->realize = imx_gpt_realize; 467 dc->reset = imx_gpt_reset; 468 dc->vmsd = &vmstate_imx_timer_gpt; 469 dc->desc = "i.MX general timer"; 470 } 471 472 static const TypeInfo imx_gpt_info = { 473 .name = TYPE_IMX_GPT, 474 .parent = TYPE_SYS_BUS_DEVICE, 475 .instance_size = sizeof(IMXGPTState), 476 .class_init = imx_gpt_class_init, 477 }; 478 479 static void imx_gpt_register_types(void) 480 { 481 type_register_static(&imx_gpt_info); 482 } 483 484 type_init(imx_gpt_register_types) 485