1 /* 2 * IMX GPT Timer 3 * 4 * Copyright (c) 2008 OK Labs 5 * Copyright (c) 2011 NICTA Pty Ltd 6 * Originally written by Hans Jiang 7 * Updated by Peter Chubb 8 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> 9 * 10 * This code is licensed under GPL version 2 or later. See 11 * the COPYING file in the top-level directory. 12 * 13 */ 14 15 #include "qemu/osdep.h" 16 #include "hw/irq.h" 17 #include "hw/timer/imx_gpt.h" 18 #include "qemu/main-loop.h" 19 #include "qemu/module.h" 20 #include "qemu/log.h" 21 22 #ifndef DEBUG_IMX_GPT 23 #define DEBUG_IMX_GPT 0 24 #endif 25 26 #define DPRINTF(fmt, args...) \ 27 do { \ 28 if (DEBUG_IMX_GPT) { \ 29 fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_GPT, \ 30 __func__, ##args); \ 31 } \ 32 } while (0) 33 34 static const char *imx_gpt_reg_name(uint32_t reg) 35 { 36 switch (reg) { 37 case 0: 38 return "CR"; 39 case 1: 40 return "PR"; 41 case 2: 42 return "SR"; 43 case 3: 44 return "IR"; 45 case 4: 46 return "OCR1"; 47 case 5: 48 return "OCR2"; 49 case 6: 50 return "OCR3"; 51 case 7: 52 return "ICR1"; 53 case 8: 54 return "ICR2"; 55 case 9: 56 return "CNT"; 57 default: 58 return "[?]"; 59 } 60 } 61 62 static const VMStateDescription vmstate_imx_timer_gpt = { 63 .name = TYPE_IMX_GPT, 64 .version_id = 3, 65 .minimum_version_id = 3, 66 .fields = (VMStateField[]) { 67 VMSTATE_UINT32(cr, IMXGPTState), 68 VMSTATE_UINT32(pr, IMXGPTState), 69 VMSTATE_UINT32(sr, IMXGPTState), 70 VMSTATE_UINT32(ir, IMXGPTState), 71 VMSTATE_UINT32(ocr1, IMXGPTState), 72 VMSTATE_UINT32(ocr2, IMXGPTState), 73 VMSTATE_UINT32(ocr3, IMXGPTState), 74 VMSTATE_UINT32(icr1, IMXGPTState), 75 VMSTATE_UINT32(icr2, IMXGPTState), 76 VMSTATE_UINT32(cnt, IMXGPTState), 77 VMSTATE_UINT32(next_timeout, IMXGPTState), 78 VMSTATE_UINT32(next_int, IMXGPTState), 79 VMSTATE_UINT32(freq, IMXGPTState), 80 VMSTATE_PTIMER(timer, IMXGPTState), 81 VMSTATE_END_OF_LIST() 82 } 83 }; 84 85 static const IMXClk imx25_gpt_clocks[] = { 86 CLK_NONE, /* 000 No clock source */ 87 CLK_IPG, /* 001 ipg_clk, 532MHz*/ 88 CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */ 89 CLK_NONE, /* 011 not defined */ 90 CLK_32k, /* 100 ipg_clk_32k */ 91 CLK_32k, /* 101 ipg_clk_32k */ 92 CLK_32k, /* 110 ipg_clk_32k */ 93 CLK_32k, /* 111 ipg_clk_32k */ 94 }; 95 96 static const IMXClk imx31_gpt_clocks[] = { 97 CLK_NONE, /* 000 No clock source */ 98 CLK_IPG, /* 001 ipg_clk, 532MHz*/ 99 CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */ 100 CLK_NONE, /* 011 not defined */ 101 CLK_32k, /* 100 ipg_clk_32k */ 102 CLK_NONE, /* 101 not defined */ 103 CLK_NONE, /* 110 not defined */ 104 CLK_NONE, /* 111 not defined */ 105 }; 106 107 static const IMXClk imx6_gpt_clocks[] = { 108 CLK_NONE, /* 000 No clock source */ 109 CLK_IPG, /* 001 ipg_clk, 532MHz*/ 110 CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */ 111 CLK_EXT, /* 011 External clock */ 112 CLK_32k, /* 100 ipg_clk_32k */ 113 CLK_HIGH_DIV, /* 101 reference clock / 8 */ 114 CLK_NONE, /* 110 not defined */ 115 CLK_HIGH, /* 111 reference clock */ 116 }; 117 118 static const IMXClk imx7_gpt_clocks[] = { 119 CLK_NONE, /* 000 No clock source */ 120 CLK_IPG, /* 001 ipg_clk, 532MHz*/ 121 CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */ 122 CLK_EXT, /* 011 External clock */ 123 CLK_32k, /* 100 ipg_clk_32k */ 124 CLK_HIGH, /* 101 reference clock */ 125 CLK_NONE, /* 110 not defined */ 126 CLK_NONE, /* 111 not defined */ 127 }; 128 129 static void imx_gpt_set_freq(IMXGPTState *s) 130 { 131 uint32_t clksrc = extract32(s->cr, GPT_CR_CLKSRC_SHIFT, 3); 132 133 s->freq = imx_ccm_get_clock_frequency(s->ccm, 134 s->clocks[clksrc]) / (1 + s->pr); 135 136 DPRINTF("Setting clksrc %d to frequency %d\n", clksrc, s->freq); 137 138 if (s->freq) { 139 ptimer_set_freq(s->timer, s->freq); 140 } 141 } 142 143 static void imx_gpt_update_int(IMXGPTState *s) 144 { 145 if ((s->sr & s->ir) && (s->cr & GPT_CR_EN)) { 146 qemu_irq_raise(s->irq); 147 } else { 148 qemu_irq_lower(s->irq); 149 } 150 } 151 152 static uint32_t imx_gpt_update_count(IMXGPTState *s) 153 { 154 s->cnt = s->next_timeout - (uint32_t)ptimer_get_count(s->timer); 155 156 return s->cnt; 157 } 158 159 static inline uint32_t imx_gpt_find_limit(uint32_t count, uint32_t reg, 160 uint32_t timeout) 161 { 162 if ((count < reg) && (timeout > reg)) { 163 timeout = reg; 164 } 165 166 return timeout; 167 } 168 169 static void imx_gpt_compute_next_timeout(IMXGPTState *s, bool event) 170 { 171 uint32_t timeout = GPT_TIMER_MAX; 172 uint32_t count; 173 long long limit; 174 175 if (!(s->cr & GPT_CR_EN)) { 176 /* if not enabled just return */ 177 return; 178 } 179 180 /* update the count */ 181 count = imx_gpt_update_count(s); 182 183 if (event) { 184 /* 185 * This is an event (the ptimer reached 0 and stopped), and the 186 * timer counter is now equal to s->next_timeout. 187 */ 188 if (!(s->cr & GPT_CR_FRR) && (count == s->ocr1)) { 189 /* We are in restart mode and we crossed the compare channel 1 190 * value. We need to reset the counter to 0. 191 */ 192 count = s->cnt = s->next_timeout = 0; 193 } else if (count == GPT_TIMER_MAX) { 194 /* We reached GPT_TIMER_MAX so we need to rollover */ 195 count = s->cnt = s->next_timeout = 0; 196 } 197 } 198 199 /* now, find the next timeout related to count */ 200 201 if (s->ir & GPT_IR_OF1IE) { 202 timeout = imx_gpt_find_limit(count, s->ocr1, timeout); 203 } 204 if (s->ir & GPT_IR_OF2IE) { 205 timeout = imx_gpt_find_limit(count, s->ocr2, timeout); 206 } 207 if (s->ir & GPT_IR_OF3IE) { 208 timeout = imx_gpt_find_limit(count, s->ocr3, timeout); 209 } 210 211 /* find the next set of interrupts to raise for next timer event */ 212 213 s->next_int = 0; 214 if ((s->ir & GPT_IR_OF1IE) && (timeout == s->ocr1)) { 215 s->next_int |= GPT_SR_OF1; 216 } 217 if ((s->ir & GPT_IR_OF2IE) && (timeout == s->ocr2)) { 218 s->next_int |= GPT_SR_OF2; 219 } 220 if ((s->ir & GPT_IR_OF3IE) && (timeout == s->ocr3)) { 221 s->next_int |= GPT_SR_OF3; 222 } 223 if ((s->ir & GPT_IR_ROVIE) && (timeout == GPT_TIMER_MAX)) { 224 s->next_int |= GPT_SR_ROV; 225 } 226 227 /* the new range to count down from */ 228 limit = timeout - imx_gpt_update_count(s); 229 230 if (limit < 0) { 231 /* 232 * if we reach here, then QEMU is running too slow and we pass the 233 * timeout limit while computing it. Let's deliver the interrupt 234 * and compute a new limit. 235 */ 236 s->sr |= s->next_int; 237 238 imx_gpt_compute_next_timeout(s, event); 239 240 imx_gpt_update_int(s); 241 } else { 242 /* New timeout value */ 243 s->next_timeout = timeout; 244 245 /* reset the limit to the computed range */ 246 ptimer_set_limit(s->timer, limit, 1); 247 } 248 } 249 250 static uint64_t imx_gpt_read(void *opaque, hwaddr offset, unsigned size) 251 { 252 IMXGPTState *s = IMX_GPT(opaque); 253 uint32_t reg_value = 0; 254 255 switch (offset >> 2) { 256 case 0: /* Control Register */ 257 reg_value = s->cr; 258 break; 259 260 case 1: /* prescaler */ 261 reg_value = s->pr; 262 break; 263 264 case 2: /* Status Register */ 265 reg_value = s->sr; 266 break; 267 268 case 3: /* Interrupt Register */ 269 reg_value = s->ir; 270 break; 271 272 case 4: /* Output Compare Register 1 */ 273 reg_value = s->ocr1; 274 break; 275 276 case 5: /* Output Compare Register 2 */ 277 reg_value = s->ocr2; 278 break; 279 280 case 6: /* Output Compare Register 3 */ 281 reg_value = s->ocr3; 282 break; 283 284 case 7: /* input Capture Register 1 */ 285 qemu_log_mask(LOG_UNIMP, "[%s]%s: icr1 feature is not implemented\n", 286 TYPE_IMX_GPT, __func__); 287 reg_value = s->icr1; 288 break; 289 290 case 8: /* input Capture Register 2 */ 291 qemu_log_mask(LOG_UNIMP, "[%s]%s: icr2 feature is not implemented\n", 292 TYPE_IMX_GPT, __func__); 293 reg_value = s->icr2; 294 break; 295 296 case 9: /* cnt */ 297 imx_gpt_update_count(s); 298 reg_value = s->cnt; 299 break; 300 301 default: 302 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 303 HWADDR_PRIx "\n", TYPE_IMX_GPT, __func__, offset); 304 break; 305 } 306 307 DPRINTF("(%s) = 0x%08x\n", imx_gpt_reg_name(offset >> 2), reg_value); 308 309 return reg_value; 310 } 311 312 313 static void imx_gpt_reset_common(IMXGPTState *s, bool is_soft_reset) 314 { 315 /* stop timer */ 316 ptimer_stop(s->timer); 317 318 /* Soft reset and hard reset differ only in their handling of the CR 319 * register -- soft reset preserves the values of some bits there. 320 */ 321 if (is_soft_reset) { 322 /* Clear all CR bits except those that are preserved by soft reset. */ 323 s->cr &= GPT_CR_EN | GPT_CR_ENMOD | GPT_CR_STOPEN | GPT_CR_DOZEN | 324 GPT_CR_WAITEN | GPT_CR_DBGEN | 325 (GPT_CR_CLKSRC_MASK << GPT_CR_CLKSRC_SHIFT); 326 } else { 327 s->cr = 0; 328 } 329 s->sr = 0; 330 s->pr = 0; 331 s->ir = 0; 332 s->cnt = 0; 333 s->ocr1 = GPT_TIMER_MAX; 334 s->ocr2 = GPT_TIMER_MAX; 335 s->ocr3 = GPT_TIMER_MAX; 336 s->icr1 = 0; 337 s->icr2 = 0; 338 339 s->next_timeout = GPT_TIMER_MAX; 340 s->next_int = 0; 341 342 /* compute new freq */ 343 imx_gpt_set_freq(s); 344 345 /* reset the limit to GPT_TIMER_MAX */ 346 ptimer_set_limit(s->timer, GPT_TIMER_MAX, 1); 347 348 /* if the timer is still enabled, restart it */ 349 if (s->freq && (s->cr & GPT_CR_EN)) { 350 ptimer_run(s->timer, 1); 351 } 352 } 353 354 static void imx_gpt_soft_reset(DeviceState *dev) 355 { 356 IMXGPTState *s = IMX_GPT(dev); 357 imx_gpt_reset_common(s, true); 358 } 359 360 static void imx_gpt_reset(DeviceState *dev) 361 { 362 IMXGPTState *s = IMX_GPT(dev); 363 imx_gpt_reset_common(s, false); 364 } 365 366 static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value, 367 unsigned size) 368 { 369 IMXGPTState *s = IMX_GPT(opaque); 370 uint32_t oldreg; 371 372 DPRINTF("(%s, value = 0x%08x)\n", imx_gpt_reg_name(offset >> 2), 373 (uint32_t)value); 374 375 switch (offset >> 2) { 376 case 0: 377 oldreg = s->cr; 378 s->cr = value & ~0x7c14; 379 if (s->cr & GPT_CR_SWR) { /* force reset */ 380 /* handle the reset */ 381 imx_gpt_soft_reset(DEVICE(s)); 382 } else { 383 /* set our freq, as the source might have changed */ 384 imx_gpt_set_freq(s); 385 386 if ((oldreg ^ s->cr) & GPT_CR_EN) { 387 if (s->cr & GPT_CR_EN) { 388 if (s->cr & GPT_CR_ENMOD) { 389 s->next_timeout = GPT_TIMER_MAX; 390 ptimer_set_count(s->timer, GPT_TIMER_MAX); 391 imx_gpt_compute_next_timeout(s, false); 392 } 393 ptimer_run(s->timer, 1); 394 } else { 395 /* stop timer */ 396 ptimer_stop(s->timer); 397 } 398 } 399 } 400 break; 401 402 case 1: /* Prescaler */ 403 s->pr = value & 0xfff; 404 imx_gpt_set_freq(s); 405 break; 406 407 case 2: /* SR */ 408 s->sr &= ~(value & 0x3f); 409 imx_gpt_update_int(s); 410 break; 411 412 case 3: /* IR -- interrupt register */ 413 s->ir = value & 0x3f; 414 imx_gpt_update_int(s); 415 416 imx_gpt_compute_next_timeout(s, false); 417 418 break; 419 420 case 4: /* OCR1 -- output compare register */ 421 s->ocr1 = value; 422 423 /* In non-freerun mode, reset count when this register is written */ 424 if (!(s->cr & GPT_CR_FRR)) { 425 s->next_timeout = GPT_TIMER_MAX; 426 ptimer_set_limit(s->timer, GPT_TIMER_MAX, 1); 427 } 428 429 /* compute the new timeout */ 430 imx_gpt_compute_next_timeout(s, false); 431 432 break; 433 434 case 5: /* OCR2 -- output compare register */ 435 s->ocr2 = value; 436 437 /* compute the new timeout */ 438 imx_gpt_compute_next_timeout(s, false); 439 440 break; 441 442 case 6: /* OCR3 -- output compare register */ 443 s->ocr3 = value; 444 445 /* compute the new timeout */ 446 imx_gpt_compute_next_timeout(s, false); 447 448 break; 449 450 default: 451 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 452 HWADDR_PRIx "\n", TYPE_IMX_GPT, __func__, offset); 453 break; 454 } 455 } 456 457 static void imx_gpt_timeout(void *opaque) 458 { 459 IMXGPTState *s = IMX_GPT(opaque); 460 461 DPRINTF("\n"); 462 463 s->sr |= s->next_int; 464 s->next_int = 0; 465 466 imx_gpt_compute_next_timeout(s, true); 467 468 imx_gpt_update_int(s); 469 470 if (s->freq && (s->cr & GPT_CR_EN)) { 471 ptimer_run(s->timer, 1); 472 } 473 } 474 475 static const MemoryRegionOps imx_gpt_ops = { 476 .read = imx_gpt_read, 477 .write = imx_gpt_write, 478 .endianness = DEVICE_NATIVE_ENDIAN, 479 }; 480 481 482 static void imx_gpt_realize(DeviceState *dev, Error **errp) 483 { 484 IMXGPTState *s = IMX_GPT(dev); 485 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 486 QEMUBH *bh; 487 488 sysbus_init_irq(sbd, &s->irq); 489 memory_region_init_io(&s->iomem, OBJECT(s), &imx_gpt_ops, s, TYPE_IMX_GPT, 490 0x00001000); 491 sysbus_init_mmio(sbd, &s->iomem); 492 493 bh = qemu_bh_new(imx_gpt_timeout, s); 494 s->timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); 495 } 496 497 static void imx_gpt_class_init(ObjectClass *klass, void *data) 498 { 499 DeviceClass *dc = DEVICE_CLASS(klass); 500 501 dc->realize = imx_gpt_realize; 502 dc->reset = imx_gpt_reset; 503 dc->vmsd = &vmstate_imx_timer_gpt; 504 dc->desc = "i.MX general timer"; 505 } 506 507 static void imx25_gpt_init(Object *obj) 508 { 509 IMXGPTState *s = IMX_GPT(obj); 510 511 s->clocks = imx25_gpt_clocks; 512 } 513 514 static void imx31_gpt_init(Object *obj) 515 { 516 IMXGPTState *s = IMX_GPT(obj); 517 518 s->clocks = imx31_gpt_clocks; 519 } 520 521 static void imx6_gpt_init(Object *obj) 522 { 523 IMXGPTState *s = IMX_GPT(obj); 524 525 s->clocks = imx6_gpt_clocks; 526 } 527 528 static void imx7_gpt_init(Object *obj) 529 { 530 IMXGPTState *s = IMX_GPT(obj); 531 532 s->clocks = imx7_gpt_clocks; 533 } 534 535 static const TypeInfo imx25_gpt_info = { 536 .name = TYPE_IMX25_GPT, 537 .parent = TYPE_SYS_BUS_DEVICE, 538 .instance_size = sizeof(IMXGPTState), 539 .instance_init = imx25_gpt_init, 540 .class_init = imx_gpt_class_init, 541 }; 542 543 static const TypeInfo imx31_gpt_info = { 544 .name = TYPE_IMX31_GPT, 545 .parent = TYPE_IMX25_GPT, 546 .instance_init = imx31_gpt_init, 547 }; 548 549 static const TypeInfo imx6_gpt_info = { 550 .name = TYPE_IMX6_GPT, 551 .parent = TYPE_IMX25_GPT, 552 .instance_init = imx6_gpt_init, 553 }; 554 555 static const TypeInfo imx7_gpt_info = { 556 .name = TYPE_IMX7_GPT, 557 .parent = TYPE_IMX25_GPT, 558 .instance_init = imx7_gpt_init, 559 }; 560 561 static void imx_gpt_register_types(void) 562 { 563 type_register_static(&imx25_gpt_info); 564 type_register_static(&imx31_gpt_info); 565 type_register_static(&imx6_gpt_info); 566 type_register_static(&imx7_gpt_info); 567 } 568 569 type_init(imx_gpt_register_types) 570