1 /* 2 * IMX GPT Timer 3 * 4 * Copyright (c) 2008 OK Labs 5 * Copyright (c) 2011 NICTA Pty Ltd 6 * Originally written by Hans Jiang 7 * Updated by Peter Chubb 8 * Updated by Jean-Christophe Dubois 9 * 10 * This code is licensed under GPL version 2 or later. See 11 * the COPYING file in the top-level directory. 12 * 13 */ 14 15 #include "hw/hw.h" 16 #include "qemu/bitops.h" 17 #include "qemu/timer.h" 18 #include "hw/ptimer.h" 19 #include "hw/sysbus.h" 20 #include "hw/arm/imx.h" 21 22 #define TYPE_IMX_GPT "imx.gpt" 23 24 /* 25 * Define to 1 for debug messages 26 */ 27 #define DEBUG_TIMER 0 28 #if DEBUG_TIMER 29 30 static char const *imx_timerg_reg_name(uint32_t reg) 31 { 32 switch (reg) { 33 case 0: 34 return "CR"; 35 case 1: 36 return "PR"; 37 case 2: 38 return "SR"; 39 case 3: 40 return "IR"; 41 case 4: 42 return "OCR1"; 43 case 5: 44 return "OCR2"; 45 case 6: 46 return "OCR3"; 47 case 7: 48 return "ICR1"; 49 case 8: 50 return "ICR2"; 51 case 9: 52 return "CNT"; 53 default: 54 return "[?]"; 55 } 56 } 57 58 # define DPRINTF(fmt, args...) \ 59 do { printf("%s: " fmt , __func__, ##args); } while (0) 60 #else 61 # define DPRINTF(fmt, args...) do {} while (0) 62 #endif 63 64 /* 65 * Define to 1 for messages about attempts to 66 * access unimplemented registers or similar. 67 */ 68 #define DEBUG_IMPLEMENTATION 1 69 #if DEBUG_IMPLEMENTATION 70 # define IPRINTF(fmt, args...) \ 71 do { fprintf(stderr, "%s: " fmt, __func__, ##args); } while (0) 72 #else 73 # define IPRINTF(fmt, args...) do {} while (0) 74 #endif 75 76 /* 77 * GPT : General purpose timer 78 * 79 * This timer counts up continuously while it is enabled, resetting itself 80 * to 0 when it reaches TIMER_MAX (in freerun mode) or when it 81 * reaches the value of one of the ocrX (in periodic mode). 82 */ 83 84 #define TIMER_MAX 0XFFFFFFFFUL 85 86 /* Control register. Not all of these bits have any effect (yet) */ 87 #define GPT_CR_EN (1 << 0) /* GPT Enable */ 88 #define GPT_CR_ENMOD (1 << 1) /* GPT Enable Mode */ 89 #define GPT_CR_DBGEN (1 << 2) /* GPT Debug mode enable */ 90 #define GPT_CR_WAITEN (1 << 3) /* GPT Wait Mode Enable */ 91 #define GPT_CR_DOZEN (1 << 4) /* GPT Doze mode enable */ 92 #define GPT_CR_STOPEN (1 << 5) /* GPT Stop Mode Enable */ 93 #define GPT_CR_CLKSRC_SHIFT (6) 94 #define GPT_CR_CLKSRC_MASK (0x7) 95 96 #define GPT_CR_FRR (1 << 9) /* Freerun or Restart */ 97 #define GPT_CR_SWR (1 << 15) /* Software Reset */ 98 #define GPT_CR_IM1 (3 << 16) /* Input capture channel 1 mode (2 bits) */ 99 #define GPT_CR_IM2 (3 << 18) /* Input capture channel 2 mode (2 bits) */ 100 #define GPT_CR_OM1 (7 << 20) /* Output Compare Channel 1 Mode (3 bits) */ 101 #define GPT_CR_OM2 (7 << 23) /* Output Compare Channel 2 Mode (3 bits) */ 102 #define GPT_CR_OM3 (7 << 26) /* Output Compare Channel 3 Mode (3 bits) */ 103 #define GPT_CR_FO1 (1 << 29) /* Force Output Compare Channel 1 */ 104 #define GPT_CR_FO2 (1 << 30) /* Force Output Compare Channel 2 */ 105 #define GPT_CR_FO3 (1 << 31) /* Force Output Compare Channel 3 */ 106 107 #define GPT_SR_OF1 (1 << 0) 108 #define GPT_SR_OF2 (1 << 1) 109 #define GPT_SR_OF3 (1 << 2) 110 #define GPT_SR_ROV (1 << 5) 111 112 #define GPT_IR_OF1IE (1 << 0) 113 #define GPT_IR_OF2IE (1 << 1) 114 #define GPT_IR_OF3IE (1 << 2) 115 #define GPT_IR_ROVIE (1 << 5) 116 117 typedef struct { 118 SysBusDevice busdev; 119 ptimer_state *timer; 120 MemoryRegion iomem; 121 DeviceState *ccm; 122 123 uint32_t cr; 124 uint32_t pr; 125 uint32_t sr; 126 uint32_t ir; 127 uint32_t ocr1; 128 uint32_t ocr2; 129 uint32_t ocr3; 130 uint32_t icr1; 131 uint32_t icr2; 132 uint32_t cnt; 133 134 uint32_t next_timeout; 135 uint32_t next_int; 136 137 uint32_t freq; 138 139 qemu_irq irq; 140 } IMXTimerGState; 141 142 static const VMStateDescription vmstate_imx_timerg = { 143 .name = TYPE_IMX_GPT, 144 .version_id = 3, 145 .minimum_version_id = 3, 146 .minimum_version_id_old = 3, 147 .fields = (VMStateField[]) { 148 VMSTATE_UINT32(cr, IMXTimerGState), 149 VMSTATE_UINT32(pr, IMXTimerGState), 150 VMSTATE_UINT32(sr, IMXTimerGState), 151 VMSTATE_UINT32(ir, IMXTimerGState), 152 VMSTATE_UINT32(ocr1, IMXTimerGState), 153 VMSTATE_UINT32(ocr2, IMXTimerGState), 154 VMSTATE_UINT32(ocr3, IMXTimerGState), 155 VMSTATE_UINT32(icr1, IMXTimerGState), 156 VMSTATE_UINT32(icr2, IMXTimerGState), 157 VMSTATE_UINT32(cnt, IMXTimerGState), 158 VMSTATE_UINT32(next_timeout, IMXTimerGState), 159 VMSTATE_UINT32(next_int, IMXTimerGState), 160 VMSTATE_UINT32(freq, IMXTimerGState), 161 VMSTATE_PTIMER(timer, IMXTimerGState), 162 VMSTATE_END_OF_LIST() 163 } 164 }; 165 166 static const IMXClk imx_timerg_clocks[] = { 167 NOCLK, /* 000 No clock source */ 168 IPG, /* 001 ipg_clk, 532MHz*/ 169 IPG, /* 010 ipg_clk_highfreq */ 170 NOCLK, /* 011 not defined */ 171 CLK_32k, /* 100 ipg_clk_32k */ 172 NOCLK, /* 101 not defined */ 173 NOCLK, /* 110 not defined */ 174 NOCLK, /* 111 not defined */ 175 }; 176 177 static void imx_timerg_set_freq(IMXTimerGState *s) 178 { 179 uint32_t clksrc = extract32(s->cr, GPT_CR_CLKSRC_SHIFT, 3); 180 uint32_t freq = imx_clock_frequency(s->ccm, imx_timerg_clocks[clksrc]) 181 / (1 + s->pr); 182 s->freq = freq; 183 184 DPRINTF("Setting clksrc %d to frequency %d\n", clksrc, freq); 185 186 if (freq) { 187 ptimer_set_freq(s->timer, freq); 188 } 189 } 190 191 static void imx_timerg_update(IMXTimerGState *s) 192 { 193 if ((s->sr & s->ir) && (s->cr & GPT_CR_EN)) { 194 qemu_irq_raise(s->irq); 195 } else { 196 qemu_irq_lower(s->irq); 197 } 198 } 199 200 static uint32_t imx_timerg_update_counts(IMXTimerGState *s) 201 { 202 s->cnt = s->next_timeout - (uint32_t)ptimer_get_count(s->timer); 203 204 return s->cnt; 205 } 206 207 static inline uint32_t imx_timerg_find_limit(uint32_t count, uint32_t reg, 208 uint32_t timeout) 209 { 210 if ((count < reg) && (timeout > reg)) { 211 timeout = reg; 212 } 213 214 return timeout; 215 } 216 217 static void imx_timerg_compute_next_timeout(IMXTimerGState *s, bool event) 218 { 219 uint32_t timeout = TIMER_MAX; 220 uint32_t count = 0; 221 long long limit; 222 223 if (!(s->cr & GPT_CR_EN)) { 224 /* if not enabled just return */ 225 return; 226 } 227 228 if (event) { 229 /* This is a timer event */ 230 231 if ((s->cr & GPT_CR_FRR) && (s->next_timeout != TIMER_MAX)) { 232 /* 233 * if we are in free running mode and we have not reached 234 * the TIMER_MAX limit, then update the count 235 */ 236 count = imx_timerg_update_counts(s); 237 } 238 } else { 239 /* not a timer event, then just update the count */ 240 241 count = imx_timerg_update_counts(s); 242 } 243 244 /* now, find the next timeout related to count */ 245 246 if (s->ir & GPT_IR_OF1IE) { 247 timeout = imx_timerg_find_limit(count, s->ocr1, timeout); 248 } 249 if (s->ir & GPT_IR_OF2IE) { 250 timeout = imx_timerg_find_limit(count, s->ocr2, timeout); 251 } 252 if (s->ir & GPT_IR_OF3IE) { 253 timeout = imx_timerg_find_limit(count, s->ocr3, timeout); 254 } 255 256 /* find the next set of interrupts to raise for next timer event */ 257 258 s->next_int = 0; 259 if ((s->ir & GPT_IR_OF1IE) && (timeout == s->ocr1)) { 260 s->next_int |= GPT_SR_OF1; 261 } 262 if ((s->ir & GPT_IR_OF2IE) && (timeout == s->ocr2)) { 263 s->next_int |= GPT_SR_OF2; 264 } 265 if ((s->ir & GPT_IR_OF3IE) && (timeout == s->ocr3)) { 266 s->next_int |= GPT_SR_OF3; 267 } 268 if ((s->ir & GPT_IR_ROVIE) && (timeout == TIMER_MAX)) { 269 s->next_int |= GPT_SR_ROV; 270 } 271 272 /* the new range to count down from */ 273 limit = timeout - imx_timerg_update_counts(s); 274 275 if (limit < 0) { 276 /* 277 * if we reach here, then QEMU is running too slow and we pass the 278 * timeout limit while computing it. Let's deliver the interrupt 279 * and compute a new limit. 280 */ 281 s->sr |= s->next_int; 282 283 imx_timerg_compute_next_timeout(s, event); 284 285 imx_timerg_update(s); 286 } else { 287 /* New timeout value */ 288 s->next_timeout = timeout; 289 290 /* reset the limit to the computed range */ 291 ptimer_set_limit(s->timer, limit, 1); 292 } 293 } 294 295 static uint64_t imx_timerg_read(void *opaque, hwaddr offset, 296 unsigned size) 297 { 298 IMXTimerGState *s = (IMXTimerGState *)opaque; 299 uint32_t reg_value = 0; 300 uint32_t reg = offset >> 2; 301 302 switch (reg) { 303 case 0: /* Control Register */ 304 reg_value = s->cr; 305 break; 306 307 case 1: /* prescaler */ 308 reg_value = s->pr; 309 break; 310 311 case 2: /* Status Register */ 312 reg_value = s->sr; 313 break; 314 315 case 3: /* Interrupt Register */ 316 reg_value = s->ir; 317 break; 318 319 case 4: /* Output Compare Register 1 */ 320 reg_value = s->ocr1; 321 break; 322 323 case 5: /* Output Compare Register 2 */ 324 reg_value = s->ocr2; 325 break; 326 327 case 6: /* Output Compare Register 3 */ 328 reg_value = s->ocr3; 329 break; 330 331 case 7: /* input Capture Register 1 */ 332 qemu_log_mask(LOG_UNIMP, "icr1 feature is not implemented\n"); 333 reg_value = s->icr1; 334 break; 335 336 case 8: /* input Capture Register 2 */ 337 qemu_log_mask(LOG_UNIMP, "icr2 feature is not implemented\n"); 338 reg_value = s->icr2; 339 break; 340 341 case 9: /* cnt */ 342 imx_timerg_update_counts(s); 343 reg_value = s->cnt; 344 break; 345 346 default: 347 IPRINTF("Bad offset %x\n", reg); 348 break; 349 } 350 351 DPRINTF("(%s) = 0x%08x\n", imx_timerg_reg_name(reg), reg_value); 352 353 return reg_value; 354 } 355 356 static void imx_timerg_reset(DeviceState *dev) 357 { 358 IMXTimerGState *s = container_of(dev, IMXTimerGState, busdev.qdev); 359 360 /* stop timer */ 361 ptimer_stop(s->timer); 362 363 /* 364 * Soft reset doesn't touch some bits; hard reset clears them 365 */ 366 s->cr &= ~(GPT_CR_EN|GPT_CR_ENMOD|GPT_CR_STOPEN|GPT_CR_DOZEN| 367 GPT_CR_WAITEN|GPT_CR_DBGEN); 368 s->sr = 0; 369 s->pr = 0; 370 s->ir = 0; 371 s->cnt = 0; 372 s->ocr1 = TIMER_MAX; 373 s->ocr2 = TIMER_MAX; 374 s->ocr3 = TIMER_MAX; 375 s->icr1 = 0; 376 s->icr2 = 0; 377 378 s->next_timeout = TIMER_MAX; 379 s->next_int = 0; 380 381 /* compute new freq */ 382 imx_timerg_set_freq(s); 383 384 /* reset the limit to TIMER_MAX */ 385 ptimer_set_limit(s->timer, TIMER_MAX, 1); 386 387 /* if the timer is still enabled, restart it */ 388 if (s->freq && (s->cr & GPT_CR_EN)) { 389 ptimer_run(s->timer, 1); 390 } 391 } 392 393 static void imx_timerg_write(void *opaque, hwaddr offset, 394 uint64_t value, unsigned size) 395 { 396 IMXTimerGState *s = (IMXTimerGState *)opaque; 397 uint32_t oldreg; 398 uint32_t reg = offset >> 2; 399 400 DPRINTF("(%s, value = 0x%08x)\n", imx_timerg_reg_name(reg), 401 (uint32_t)value); 402 403 switch (reg) { 404 case 0: 405 oldreg = s->cr; 406 s->cr = value & ~0x7c14; 407 if (s->cr & GPT_CR_SWR) { /* force reset */ 408 /* handle the reset */ 409 imx_timerg_reset(DEVICE(s)); 410 } else { 411 /* set our freq, as the source might have changed */ 412 imx_timerg_set_freq(s); 413 414 if ((oldreg ^ s->cr) & GPT_CR_EN) { 415 if (s->cr & GPT_CR_EN) { 416 if (s->cr & GPT_CR_ENMOD) { 417 s->next_timeout = TIMER_MAX; 418 ptimer_set_count(s->timer, TIMER_MAX); 419 imx_timerg_compute_next_timeout(s, false); 420 } 421 ptimer_run(s->timer, 1); 422 } else { 423 /* stop timer */ 424 ptimer_stop(s->timer); 425 } 426 } 427 } 428 break; 429 430 case 1: /* Prescaler */ 431 s->pr = value & 0xfff; 432 imx_timerg_set_freq(s); 433 break; 434 435 case 2: /* SR */ 436 s->sr &= ~(value & 0x3f); 437 imx_timerg_update(s); 438 break; 439 440 case 3: /* IR -- interrupt register */ 441 s->ir = value & 0x3f; 442 imx_timerg_update(s); 443 444 imx_timerg_compute_next_timeout(s, false); 445 446 break; 447 448 case 4: /* OCR1 -- output compare register */ 449 s->ocr1 = value; 450 451 /* In non-freerun mode, reset count when this register is written */ 452 if (!(s->cr & GPT_CR_FRR)) { 453 s->next_timeout = TIMER_MAX; 454 ptimer_set_limit(s->timer, TIMER_MAX, 1); 455 } 456 457 /* compute the new timeout */ 458 imx_timerg_compute_next_timeout(s, false); 459 460 break; 461 462 case 5: /* OCR2 -- output compare register */ 463 s->ocr2 = value; 464 465 /* compute the new timeout */ 466 imx_timerg_compute_next_timeout(s, false); 467 468 break; 469 470 case 6: /* OCR3 -- output compare register */ 471 s->ocr3 = value; 472 473 /* compute the new timeout */ 474 imx_timerg_compute_next_timeout(s, false); 475 476 break; 477 478 default: 479 IPRINTF("Bad offset %x\n", reg); 480 break; 481 } 482 } 483 484 static void imx_timerg_timeout(void *opaque) 485 { 486 IMXTimerGState *s = (IMXTimerGState *)opaque; 487 488 DPRINTF("\n"); 489 490 s->sr |= s->next_int; 491 s->next_int = 0; 492 493 imx_timerg_compute_next_timeout(s, true); 494 495 imx_timerg_update(s); 496 497 if (s->freq && (s->cr & GPT_CR_EN)) { 498 ptimer_run(s->timer, 1); 499 } 500 } 501 502 static const MemoryRegionOps imx_timerg_ops = { 503 .read = imx_timerg_read, 504 .write = imx_timerg_write, 505 .endianness = DEVICE_NATIVE_ENDIAN, 506 }; 507 508 509 static int imx_timerg_init(SysBusDevice *dev) 510 { 511 IMXTimerGState *s = FROM_SYSBUS(IMXTimerGState, dev); 512 QEMUBH *bh; 513 514 sysbus_init_irq(dev, &s->irq); 515 memory_region_init_io(&s->iomem, &imx_timerg_ops, 516 s, TYPE_IMX_GPT, 517 0x00001000); 518 sysbus_init_mmio(dev, &s->iomem); 519 520 bh = qemu_bh_new(imx_timerg_timeout, s); 521 s->timer = ptimer_init(bh); 522 523 /* Hard reset resets extra bits in CR */ 524 s->cr = 0; 525 return 0; 526 } 527 528 void imx_timerg_create(const hwaddr addr, qemu_irq irq, DeviceState *ccm) 529 { 530 IMXTimerGState *pp; 531 DeviceState *dev; 532 533 dev = sysbus_create_simple(TYPE_IMX_GPT, addr, irq); 534 pp = container_of(dev, IMXTimerGState, busdev.qdev); 535 pp->ccm = ccm; 536 } 537 538 static void imx_timerg_class_init(ObjectClass *klass, void *data) 539 { 540 DeviceClass *dc = DEVICE_CLASS(klass); 541 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 542 k->init = imx_timerg_init; 543 dc->vmsd = &vmstate_imx_timerg; 544 dc->reset = imx_timerg_reset; 545 dc->desc = "i.MX general timer"; 546 } 547 548 static const TypeInfo imx_timerg_info = { 549 .name = TYPE_IMX_GPT, 550 .parent = TYPE_SYS_BUS_DEVICE, 551 .instance_size = sizeof(IMXTimerGState), 552 .class_init = imx_timerg_class_init, 553 }; 554 555 static void imx_timer_register_types(void) 556 { 557 type_register_static(&imx_timerg_info); 558 } 559 560 type_init(imx_timer_register_types) 561