1 /* 2 * IMX EPIT Timer 3 * 4 * Copyright (c) 2008 OK Labs 5 * Copyright (c) 2011 NICTA Pty Ltd 6 * Originally written by Hans Jiang 7 * Updated by Peter Chubb 8 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> 9 * 10 * This code is licensed under GPL version 2 or later. See 11 * the COPYING file in the top-level directory. 12 * 13 */ 14 15 #include "qemu/osdep.h" 16 #include "hw/timer/imx_epit.h" 17 #include "migration/vmstate.h" 18 #include "hw/irq.h" 19 #include "hw/misc/imx_ccm.h" 20 #include "qemu/module.h" 21 #include "qemu/log.h" 22 23 #ifndef DEBUG_IMX_EPIT 24 #define DEBUG_IMX_EPIT 0 25 #endif 26 27 #define DPRINTF(fmt, args...) \ 28 do { \ 29 if (DEBUG_IMX_EPIT) { \ 30 fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_EPIT, \ 31 __func__, ##args); \ 32 } \ 33 } while (0) 34 35 static const char *imx_epit_reg_name(uint32_t reg) 36 { 37 switch (reg) { 38 case 0: 39 return "CR"; 40 case 1: 41 return "SR"; 42 case 2: 43 return "LR"; 44 case 3: 45 return "CMP"; 46 case 4: 47 return "CNT"; 48 default: 49 return "[?]"; 50 } 51 } 52 53 /* 54 * Exact clock frequencies vary from board to board. 55 * These are typical. 56 */ 57 static const IMXClk imx_epit_clocks[] = { 58 CLK_NONE, /* 00 disabled */ 59 CLK_IPG, /* 01 ipg_clk, ~532MHz */ 60 CLK_IPG_HIGH, /* 10 ipg_clk_highfreq */ 61 CLK_32k, /* 11 ipg_clk_32k -- ~32kHz */ 62 }; 63 64 /* 65 * Update interrupt status 66 */ 67 static void imx_epit_update_int(IMXEPITState *s) 68 { 69 if ((s->sr & SR_OCIF) && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) { 70 qemu_irq_raise(s->irq); 71 } else { 72 qemu_irq_lower(s->irq); 73 } 74 } 75 76 /* 77 * Must be called from within a ptimer_transaction_begin/commit block 78 * for both s->timer_cmp and s->timer_reload. 79 */ 80 static void imx_epit_set_freq(IMXEPITState *s) 81 { 82 uint32_t clksrc; 83 uint32_t prescaler; 84 85 clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, CR_CLKSRC_BITS); 86 prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, CR_PRESCALE_BITS); 87 88 s->freq = imx_ccm_get_clock_frequency(s->ccm, 89 imx_epit_clocks[clksrc]) / prescaler; 90 91 DPRINTF("Setting ptimer frequency to %u\n", s->freq); 92 93 if (s->freq) { 94 ptimer_set_freq(s->timer_reload, s->freq); 95 ptimer_set_freq(s->timer_cmp, s->freq); 96 } 97 } 98 99 /* 100 * This is called both on hardware (device) reset and software reset. 101 */ 102 static void imx_epit_reset(IMXEPITState *s, bool is_hard_reset) 103 { 104 /* Soft reset doesn't touch some bits; hard reset clears them */ 105 if (is_hard_reset) { 106 s->cr = 0; 107 } else { 108 s->cr &= (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN); 109 } 110 s->sr = 0; 111 s->lr = EPIT_TIMER_MAX; 112 s->cmp = 0; 113 s->cnt = 0; 114 ptimer_transaction_begin(s->timer_cmp); 115 ptimer_transaction_begin(s->timer_reload); 116 /* stop both timers */ 117 ptimer_stop(s->timer_cmp); 118 ptimer_stop(s->timer_reload); 119 /* compute new frequency */ 120 imx_epit_set_freq(s); 121 /* init both timers to EPIT_TIMER_MAX */ 122 ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1); 123 ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1); 124 if (s->freq && (s->cr & CR_EN)) { 125 /* if the timer is still enabled, restart it */ 126 ptimer_run(s->timer_reload, 0); 127 } 128 ptimer_transaction_commit(s->timer_cmp); 129 ptimer_transaction_commit(s->timer_reload); 130 } 131 132 static uint32_t imx_epit_update_count(IMXEPITState *s) 133 { 134 s->cnt = ptimer_get_count(s->timer_reload); 135 136 return s->cnt; 137 } 138 139 static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size) 140 { 141 IMXEPITState *s = IMX_EPIT(opaque); 142 uint32_t reg_value = 0; 143 144 switch (offset >> 2) { 145 case 0: /* Control Register */ 146 reg_value = s->cr; 147 break; 148 149 case 1: /* Status Register */ 150 reg_value = s->sr; 151 break; 152 153 case 2: /* LR - ticks*/ 154 reg_value = s->lr; 155 break; 156 157 case 3: /* CMP */ 158 reg_value = s->cmp; 159 break; 160 161 case 4: /* CNT */ 162 imx_epit_update_count(s); 163 reg_value = s->cnt; 164 break; 165 166 default: 167 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 168 HWADDR_PRIx "\n", TYPE_IMX_EPIT, __func__, offset); 169 break; 170 } 171 172 DPRINTF("(%s) = 0x%08x\n", imx_epit_reg_name(offset >> 2), reg_value); 173 174 return reg_value; 175 } 176 177 /* Must be called from ptimer_transaction_begin/commit block for s->timer_cmp */ 178 static void imx_epit_reload_compare_timer(IMXEPITState *s) 179 { 180 if ((s->cr & (CR_EN | CR_OCIEN)) == (CR_EN | CR_OCIEN)) { 181 /* if the compare feature is on and timers are running */ 182 uint32_t tmp = imx_epit_update_count(s); 183 uint64_t next; 184 if (tmp > s->cmp) { 185 /* It'll fire in this round of the timer */ 186 next = tmp - s->cmp; 187 } else { /* catch it next time around */ 188 next = tmp - s->cmp + ((s->cr & CR_RLD) ? EPIT_TIMER_MAX : s->lr); 189 } 190 ptimer_set_count(s->timer_cmp, next); 191 } 192 } 193 194 static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value, 195 unsigned size) 196 { 197 IMXEPITState *s = IMX_EPIT(opaque); 198 uint64_t oldcr; 199 200 DPRINTF("(%s, value = 0x%08x)\n", imx_epit_reg_name(offset >> 2), 201 (uint32_t)value); 202 203 switch (offset >> 2) { 204 case 0: /* CR */ 205 206 oldcr = s->cr; 207 s->cr = value & 0x03ffffff; 208 if (s->cr & CR_SWR) { 209 /* handle the reset */ 210 imx_epit_reset(s, false); 211 } 212 213 /* 214 * The interrupt state can change due to: 215 * - reset clears both SR.OCIF and CR.OCIE 216 * - write to CR.EN or CR.OCIE 217 */ 218 imx_epit_update_int(s); 219 220 /* 221 * TODO: could we 'break' here for reset? following operations appear 222 * to duplicate the work imx_epit_reset() already did. 223 */ 224 225 ptimer_transaction_begin(s->timer_cmp); 226 ptimer_transaction_begin(s->timer_reload); 227 228 /* Update the frequency. Has been done already in case of a reset. */ 229 if (!(s->cr & CR_SWR)) { 230 imx_epit_set_freq(s); 231 } 232 233 if (s->freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) { 234 if (s->cr & CR_ENMOD) { 235 if (s->cr & CR_RLD) { 236 ptimer_set_limit(s->timer_reload, s->lr, 1); 237 ptimer_set_limit(s->timer_cmp, s->lr, 1); 238 } else { 239 ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1); 240 ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1); 241 } 242 } 243 244 imx_epit_reload_compare_timer(s); 245 ptimer_run(s->timer_reload, 0); 246 if (s->cr & CR_OCIEN) { 247 ptimer_run(s->timer_cmp, 0); 248 } else { 249 ptimer_stop(s->timer_cmp); 250 } 251 } else if (!(s->cr & CR_EN)) { 252 /* stop both timers */ 253 ptimer_stop(s->timer_reload); 254 ptimer_stop(s->timer_cmp); 255 } else if (s->cr & CR_OCIEN) { 256 if (!(oldcr & CR_OCIEN)) { 257 imx_epit_reload_compare_timer(s); 258 ptimer_run(s->timer_cmp, 0); 259 } 260 } else { 261 ptimer_stop(s->timer_cmp); 262 } 263 264 ptimer_transaction_commit(s->timer_cmp); 265 ptimer_transaction_commit(s->timer_reload); 266 break; 267 268 case 1: /* SR - ACK*/ 269 /* writing 1 to SR.OCIF clears this bit and turns the interrupt off */ 270 if (value & SR_OCIF) { 271 s->sr = 0; /* SR.OCIF is the only bit in this register anyway */ 272 imx_epit_update_int(s); 273 } 274 break; 275 276 case 2: /* LR - set ticks */ 277 s->lr = value; 278 279 ptimer_transaction_begin(s->timer_cmp); 280 ptimer_transaction_begin(s->timer_reload); 281 if (s->cr & CR_RLD) { 282 /* Also set the limit if the LRD bit is set */ 283 /* If IOVW bit is set then set the timer value */ 284 ptimer_set_limit(s->timer_reload, s->lr, s->cr & CR_IOVW); 285 ptimer_set_limit(s->timer_cmp, s->lr, 0); 286 } else if (s->cr & CR_IOVW) { 287 /* If IOVW bit is set then set the timer value */ 288 ptimer_set_count(s->timer_reload, s->lr); 289 } 290 /* 291 * Commit the change to s->timer_reload, so it can propagate. Otherwise 292 * the timer interrupt may not fire properly. The commit must happen 293 * before calling imx_epit_reload_compare_timer(), which reads 294 * s->timer_reload internally again. 295 */ 296 ptimer_transaction_commit(s->timer_reload); 297 imx_epit_reload_compare_timer(s); 298 ptimer_transaction_commit(s->timer_cmp); 299 break; 300 301 case 3: /* CMP */ 302 s->cmp = value; 303 304 ptimer_transaction_begin(s->timer_cmp); 305 imx_epit_reload_compare_timer(s); 306 ptimer_transaction_commit(s->timer_cmp); 307 308 break; 309 310 default: 311 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 312 HWADDR_PRIx "\n", TYPE_IMX_EPIT, __func__, offset); 313 314 break; 315 } 316 } 317 static void imx_epit_cmp(void *opaque) 318 { 319 IMXEPITState *s = IMX_EPIT(opaque); 320 321 DPRINTF("sr was %d\n", s->sr); 322 /* Set interrupt status bit SR.OCIF and update the interrupt state */ 323 s->sr |= SR_OCIF; 324 imx_epit_update_int(s); 325 } 326 327 static void imx_epit_reload(void *opaque) 328 { 329 /* No action required on rollover of timer_reload */ 330 } 331 332 static const MemoryRegionOps imx_epit_ops = { 333 .read = imx_epit_read, 334 .write = imx_epit_write, 335 .endianness = DEVICE_NATIVE_ENDIAN, 336 }; 337 338 static const VMStateDescription vmstate_imx_timer_epit = { 339 .name = TYPE_IMX_EPIT, 340 .version_id = 2, 341 .minimum_version_id = 2, 342 .fields = (VMStateField[]) { 343 VMSTATE_UINT32(cr, IMXEPITState), 344 VMSTATE_UINT32(sr, IMXEPITState), 345 VMSTATE_UINT32(lr, IMXEPITState), 346 VMSTATE_UINT32(cmp, IMXEPITState), 347 VMSTATE_UINT32(cnt, IMXEPITState), 348 VMSTATE_UINT32(freq, IMXEPITState), 349 VMSTATE_PTIMER(timer_reload, IMXEPITState), 350 VMSTATE_PTIMER(timer_cmp, IMXEPITState), 351 VMSTATE_END_OF_LIST() 352 } 353 }; 354 355 static void imx_epit_realize(DeviceState *dev, Error **errp) 356 { 357 IMXEPITState *s = IMX_EPIT(dev); 358 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 359 360 DPRINTF("\n"); 361 362 sysbus_init_irq(sbd, &s->irq); 363 memory_region_init_io(&s->iomem, OBJECT(s), &imx_epit_ops, s, TYPE_IMX_EPIT, 364 0x00001000); 365 sysbus_init_mmio(sbd, &s->iomem); 366 367 /* 368 * The reload timer keeps running when the peripheral is enabled. It is a 369 * kind of wall clock that does not generate any interrupts. The callback 370 * needs to be provided, but it does nothing as the ptimer already supports 371 * all necessary reloading functionality. 372 */ 373 s->timer_reload = ptimer_init(imx_epit_reload, s, PTIMER_POLICY_LEGACY); 374 375 /* 376 * The compare timer is running only when the peripheral configuration is 377 * in a state that will generate compare interrupts. 378 */ 379 s->timer_cmp = ptimer_init(imx_epit_cmp, s, PTIMER_POLICY_LEGACY); 380 } 381 382 static void imx_epit_dev_reset(DeviceState *dev) 383 { 384 IMXEPITState *s = IMX_EPIT(dev); 385 imx_epit_reset(s, true); 386 } 387 388 static void imx_epit_class_init(ObjectClass *klass, void *data) 389 { 390 DeviceClass *dc = DEVICE_CLASS(klass); 391 392 dc->realize = imx_epit_realize; 393 dc->reset = imx_epit_dev_reset; 394 dc->vmsd = &vmstate_imx_timer_epit; 395 dc->desc = "i.MX periodic timer"; 396 } 397 398 static const TypeInfo imx_epit_info = { 399 .name = TYPE_IMX_EPIT, 400 .parent = TYPE_SYS_BUS_DEVICE, 401 .instance_size = sizeof(IMXEPITState), 402 .class_init = imx_epit_class_init, 403 }; 404 405 static void imx_epit_register_types(void) 406 { 407 type_register_static(&imx_epit_info); 408 } 409 410 type_init(imx_epit_register_types) 411