1 /* 2 * QEMU lowRISC Ibex Timer device 3 * 4 * Copyright (c) 2021 Western Digital 5 * 6 * For details check the documentation here: 7 * https://docs.opentitan.org/hw/ip/rv_timer/doc/ 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a copy 10 * of this software and associated documentation files (the "Software"), to deal 11 * in the Software without restriction, including without limitation the rights 12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 13 * copies of the Software, and to permit persons to whom the Software is 14 * furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in 17 * all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 25 * THE SOFTWARE. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qemu/log.h" 30 #include "qemu/timer.h" 31 #include "hw/timer/ibex_timer.h" 32 #include "hw/irq.h" 33 #include "hw/qdev-properties.h" 34 #include "target/riscv/cpu.h" 35 #include "migration/vmstate.h" 36 37 REG32(ALERT_TEST, 0x00) 38 FIELD(ALERT_TEST, FATAL_FAULT, 0, 1) 39 REG32(CTRL, 0x04) 40 FIELD(CTRL, ACTIVE, 0, 1) 41 REG32(CFG0, 0x100) 42 FIELD(CFG0, PRESCALE, 0, 12) 43 FIELD(CFG0, STEP, 16, 8) 44 REG32(LOWER0, 0x104) 45 REG32(UPPER0, 0x108) 46 REG32(COMPARE_LOWER0, 0x10C) 47 REG32(COMPARE_UPPER0, 0x110) 48 REG32(INTR_ENABLE, 0x114) 49 FIELD(INTR_ENABLE, IE_0, 0, 1) 50 REG32(INTR_STATE, 0x118) 51 FIELD(INTR_STATE, IS_0, 0, 1) 52 REG32(INTR_TEST, 0x11C) 53 FIELD(INTR_TEST, T_0, 0, 1) 54 55 static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq) 56 { 57 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 58 timebase_freq, NANOSECONDS_PER_SECOND); 59 } 60 61 static void ibex_timer_update_irqs(IbexTimerState *s) 62 { 63 uint64_t value = s->timer_compare_lower0 | 64 ((uint64_t)s->timer_compare_upper0 << 32); 65 uint64_t next, diff; 66 uint64_t now = cpu_riscv_read_rtc(s->timebase_freq); 67 68 if (!(s->timer_ctrl & R_CTRL_ACTIVE_MASK)) { 69 /* Timer isn't active */ 70 return; 71 } 72 73 /* Update the CPUs mtimecmp */ 74 s->mtimecmp = value; 75 76 if (s->mtimecmp <= now) { 77 /* 78 * If the mtimecmp was in the past raise the interrupt now. 79 */ 80 qemu_irq_raise(s->m_timer_irq); 81 if (s->timer_intr_enable & R_INTR_ENABLE_IE_0_MASK) { 82 s->timer_intr_state |= R_INTR_STATE_IS_0_MASK; 83 qemu_set_irq(s->irq, true); 84 } 85 return; 86 } 87 88 /* Setup a timer to trigger the interrupt in the future */ 89 qemu_irq_lower(s->m_timer_irq); 90 qemu_set_irq(s->irq, false); 91 92 diff = s->mtimecmp - now; 93 next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 94 muldiv64(diff, 95 NANOSECONDS_PER_SECOND, 96 s->timebase_freq); 97 98 if (next < qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) { 99 /* We overflowed the timer, just set it as large as we can */ 100 timer_mod(s->mtimer, 0x7FFFFFFFFFFFFFFF); 101 } else { 102 timer_mod(s->mtimer, next); 103 } 104 } 105 106 static void ibex_timer_cb(void *opaque) 107 { 108 IbexTimerState *s = opaque; 109 110 qemu_irq_raise(s->m_timer_irq); 111 if (s->timer_intr_enable & R_INTR_ENABLE_IE_0_MASK) { 112 s->timer_intr_state |= R_INTR_STATE_IS_0_MASK; 113 qemu_set_irq(s->irq, true); 114 } 115 } 116 117 static void ibex_timer_reset(DeviceState *dev) 118 { 119 IbexTimerState *s = IBEX_TIMER(dev); 120 121 s->mtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 122 &ibex_timer_cb, s); 123 s->mtimecmp = 0; 124 125 s->timer_ctrl = 0x00000000; 126 s->timer_cfg0 = 0x00010000; 127 s->timer_compare_lower0 = 0xFFFFFFFF; 128 s->timer_compare_upper0 = 0xFFFFFFFF; 129 s->timer_intr_enable = 0x00000000; 130 s->timer_intr_state = 0x00000000; 131 132 ibex_timer_update_irqs(s); 133 } 134 135 static uint64_t ibex_timer_read(void *opaque, hwaddr addr, 136 unsigned int size) 137 { 138 IbexTimerState *s = opaque; 139 uint64_t now = cpu_riscv_read_rtc(s->timebase_freq); 140 uint64_t retvalue = 0; 141 142 switch (addr >> 2) { 143 case R_ALERT_TEST: 144 qemu_log_mask(LOG_GUEST_ERROR, 145 "Attempted to read ALERT_TEST, a write only register"); 146 break; 147 case R_CTRL: 148 retvalue = s->timer_ctrl; 149 break; 150 case R_CFG0: 151 retvalue = s->timer_cfg0; 152 break; 153 case R_LOWER0: 154 retvalue = now; 155 break; 156 case R_UPPER0: 157 retvalue = now >> 32; 158 break; 159 case R_COMPARE_LOWER0: 160 retvalue = s->timer_compare_lower0; 161 break; 162 case R_COMPARE_UPPER0: 163 retvalue = s->timer_compare_upper0; 164 break; 165 case R_INTR_ENABLE: 166 retvalue = s->timer_intr_enable; 167 break; 168 case R_INTR_STATE: 169 retvalue = s->timer_intr_state; 170 break; 171 case R_INTR_TEST: 172 qemu_log_mask(LOG_GUEST_ERROR, 173 "Attempted to read INTR_TEST, a write only register"); 174 break; 175 default: 176 qemu_log_mask(LOG_GUEST_ERROR, 177 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); 178 return 0; 179 } 180 181 return retvalue; 182 } 183 184 static void ibex_timer_write(void *opaque, hwaddr addr, 185 uint64_t val64, unsigned int size) 186 { 187 IbexTimerState *s = opaque; 188 uint32_t val = val64; 189 190 switch (addr >> 2) { 191 case R_ALERT_TEST: 192 qemu_log_mask(LOG_UNIMP, "Alert triggering not supported"); 193 break; 194 case R_CTRL: 195 s->timer_ctrl = val; 196 break; 197 case R_CFG0: 198 qemu_log_mask(LOG_UNIMP, "Changing prescale or step not supported"); 199 s->timer_cfg0 = val; 200 break; 201 case R_LOWER0: 202 qemu_log_mask(LOG_UNIMP, "Changing timer value is not supported"); 203 break; 204 case R_UPPER0: 205 qemu_log_mask(LOG_UNIMP, "Changing timer value is not supported"); 206 break; 207 case R_COMPARE_LOWER0: 208 s->timer_compare_lower0 = val; 209 ibex_timer_update_irqs(s); 210 break; 211 case R_COMPARE_UPPER0: 212 s->timer_compare_upper0 = val; 213 ibex_timer_update_irqs(s); 214 break; 215 case R_INTR_ENABLE: 216 s->timer_intr_enable = val; 217 break; 218 case R_INTR_STATE: 219 /* Write 1 to clear */ 220 s->timer_intr_state &= ~val; 221 break; 222 case R_INTR_TEST: 223 if (s->timer_intr_enable & val & R_INTR_ENABLE_IE_0_MASK) { 224 s->timer_intr_state |= R_INTR_STATE_IS_0_MASK; 225 qemu_set_irq(s->irq, true); 226 } 227 break; 228 default: 229 qemu_log_mask(LOG_GUEST_ERROR, 230 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); 231 } 232 } 233 234 static const MemoryRegionOps ibex_timer_ops = { 235 .read = ibex_timer_read, 236 .write = ibex_timer_write, 237 .endianness = DEVICE_NATIVE_ENDIAN, 238 .impl.min_access_size = 4, 239 .impl.max_access_size = 4, 240 }; 241 242 static int ibex_timer_post_load(void *opaque, int version_id) 243 { 244 IbexTimerState *s = opaque; 245 246 ibex_timer_update_irqs(s); 247 return 0; 248 } 249 250 static const VMStateDescription vmstate_ibex_timer = { 251 .name = TYPE_IBEX_TIMER, 252 .version_id = 2, 253 .minimum_version_id = 2, 254 .post_load = ibex_timer_post_load, 255 .fields = (VMStateField[]) { 256 VMSTATE_UINT32(timer_ctrl, IbexTimerState), 257 VMSTATE_UINT32(timer_cfg0, IbexTimerState), 258 VMSTATE_UINT32(timer_compare_lower0, IbexTimerState), 259 VMSTATE_UINT32(timer_compare_upper0, IbexTimerState), 260 VMSTATE_UINT32(timer_intr_enable, IbexTimerState), 261 VMSTATE_UINT32(timer_intr_state, IbexTimerState), 262 VMSTATE_END_OF_LIST() 263 } 264 }; 265 266 static Property ibex_timer_properties[] = { 267 DEFINE_PROP_UINT32("timebase-freq", IbexTimerState, timebase_freq, 10000), 268 DEFINE_PROP_END_OF_LIST(), 269 }; 270 271 static void ibex_timer_init(Object *obj) 272 { 273 IbexTimerState *s = IBEX_TIMER(obj); 274 275 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); 276 277 memory_region_init_io(&s->mmio, obj, &ibex_timer_ops, s, 278 TYPE_IBEX_TIMER, 0x400); 279 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); 280 } 281 282 static void ibex_timer_realize(DeviceState *dev, Error **errp) 283 { 284 IbexTimerState *s = IBEX_TIMER(dev); 285 286 qdev_init_gpio_out(dev, &s->m_timer_irq, 1); 287 } 288 289 290 static void ibex_timer_class_init(ObjectClass *klass, void *data) 291 { 292 DeviceClass *dc = DEVICE_CLASS(klass); 293 294 dc->reset = ibex_timer_reset; 295 dc->vmsd = &vmstate_ibex_timer; 296 dc->realize = ibex_timer_realize; 297 device_class_set_props(dc, ibex_timer_properties); 298 } 299 300 static const TypeInfo ibex_timer_info = { 301 .name = TYPE_IBEX_TIMER, 302 .parent = TYPE_SYS_BUS_DEVICE, 303 .instance_size = sizeof(IbexTimerState), 304 .instance_init = ibex_timer_init, 305 .class_init = ibex_timer_class_init, 306 }; 307 308 static void ibex_timer_register_types(void) 309 { 310 type_register_static(&ibex_timer_info); 311 } 312 313 type_init(ibex_timer_register_types) 314