xref: /openbmc/qemu/hw/timer/ibex_timer.c (revision 40f23e4e)
1 /*
2  * QEMU lowRISC Ibex Timer device
3  *
4  * Copyright (c) 2021 Western Digital
5  *
6  * For details check the documentation here:
7  *    https://docs.opentitan.org/hw/ip/rv_timer/doc/
8  *
9  * Permission is hereby granted, free of charge, to any person obtaining a copy
10  * of this software and associated documentation files (the "Software"), to deal
11  * in the Software without restriction, including without limitation the rights
12  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13  * copies of the Software, and to permit persons to whom the Software is
14  * furnished to do so, subject to the following conditions:
15  *
16  * The above copyright notice and this permission notice shall be included in
17  * all copies or substantial portions of the Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25  * THE SOFTWARE.
26  */
27 
28 #include "qemu/osdep.h"
29 #include "qemu/log.h"
30 #include "qemu/timer.h"
31 #include "hw/timer/ibex_timer.h"
32 #include "hw/irq.h"
33 #include "hw/qdev-properties.h"
34 #include "target/riscv/cpu.h"
35 #include "migration/vmstate.h"
36 
37 REG32(CTRL, 0x00)
38     FIELD(CTRL, ACTIVE, 0, 1)
39 REG32(CFG0, 0x100)
40     FIELD(CFG0, PRESCALE, 0, 12)
41     FIELD(CFG0, STEP, 16, 8)
42 REG32(LOWER0, 0x104)
43 REG32(UPPER0, 0x108)
44 REG32(COMPARE_LOWER0, 0x10C)
45 REG32(COMPARE_UPPER0, 0x110)
46 REG32(INTR_ENABLE, 0x114)
47     FIELD(INTR_ENABLE, IE_0, 0, 1)
48 REG32(INTR_STATE, 0x118)
49     FIELD(INTR_STATE, IS_0, 0, 1)
50 REG32(INTR_TEST, 0x11C)
51     FIELD(INTR_TEST, T_0, 0, 1)
52 
53 static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
54 {
55     return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
56                     timebase_freq, NANOSECONDS_PER_SECOND);
57 }
58 
59 static void ibex_timer_update_irqs(IbexTimerState *s)
60 {
61     CPUState *cs = qemu_get_cpu(0);
62     RISCVCPU *cpu = RISCV_CPU(cs);
63     uint64_t value = s->timer_compare_lower0 |
64                          ((uint64_t)s->timer_compare_upper0 << 32);
65     uint64_t next, diff;
66     uint64_t now = cpu_riscv_read_rtc(s->timebase_freq);
67 
68     if (!(s->timer_ctrl & R_CTRL_ACTIVE_MASK)) {
69         /* Timer isn't active */
70         return;
71     }
72 
73     /* Update the CPUs mtimecmp */
74     cpu->env.timecmp = value;
75 
76     if (cpu->env.timecmp <= now) {
77         /*
78          * If the mtimecmp was in the past raise the interrupt now.
79          */
80         riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1));
81         if (s->timer_intr_enable & R_INTR_ENABLE_IE_0_MASK) {
82             s->timer_intr_state |= R_INTR_STATE_IS_0_MASK;
83             qemu_set_irq(s->irq, true);
84         }
85         return;
86     }
87 
88     /* Setup a timer to trigger the interrupt in the future */
89     riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(0));
90     qemu_set_irq(s->irq, false);
91 
92     diff = cpu->env.timecmp - now;
93     next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
94                                  muldiv64(diff,
95                                           NANOSECONDS_PER_SECOND,
96                                           s->timebase_freq);
97 
98     if (next < qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) {
99         /* We overflowed the timer, just set it as large as we can */
100         timer_mod(cpu->env.timer, 0x7FFFFFFFFFFFFFFF);
101     } else {
102         timer_mod(cpu->env.timer, next);
103     }
104 }
105 
106 static void ibex_timer_cb(void *opaque)
107 {
108     IbexTimerState *s = opaque;
109     CPUState *cs = qemu_get_cpu(0);
110     RISCVCPU *cpu = RISCV_CPU(cs);
111 
112     riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1));
113     if (s->timer_intr_enable & R_INTR_ENABLE_IE_0_MASK) {
114         s->timer_intr_state |= R_INTR_STATE_IS_0_MASK;
115         qemu_set_irq(s->irq, true);
116     }
117 }
118 
119 static void ibex_timer_reset(DeviceState *dev)
120 {
121     IbexTimerState *s = IBEX_TIMER(dev);
122 
123     CPUState *cpu = qemu_get_cpu(0);
124     CPURISCVState *env = cpu->env_ptr;
125     env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
126                               &ibex_timer_cb, s);
127     env->timecmp = 0;
128 
129     s->timer_ctrl = 0x00000000;
130     s->timer_cfg0 = 0x00010000;
131     s->timer_compare_lower0 = 0xFFFFFFFF;
132     s->timer_compare_upper0 = 0xFFFFFFFF;
133     s->timer_intr_enable = 0x00000000;
134     s->timer_intr_state = 0x00000000;
135     s->timer_intr_test = 0x00000000;
136 
137     ibex_timer_update_irqs(s);
138 }
139 
140 static uint64_t ibex_timer_read(void *opaque, hwaddr addr,
141                                        unsigned int size)
142 {
143     IbexTimerState *s = opaque;
144     uint64_t now = cpu_riscv_read_rtc(s->timebase_freq);
145     uint64_t retvalue = 0;
146 
147     switch (addr >> 2) {
148     case R_CTRL:
149         retvalue = s->timer_ctrl;
150         break;
151     case R_CFG0:
152         retvalue = s->timer_cfg0;
153         break;
154     case R_LOWER0:
155         retvalue = now;
156         break;
157     case R_UPPER0:
158         retvalue = now >> 32;
159         break;
160     case R_COMPARE_LOWER0:
161         retvalue = s->timer_compare_lower0;
162         break;
163     case R_COMPARE_UPPER0:
164         retvalue = s->timer_compare_upper0;
165         break;
166     case R_INTR_ENABLE:
167         retvalue = s->timer_intr_enable;
168         break;
169     case R_INTR_STATE:
170         retvalue = s->timer_intr_state;
171         break;
172     case R_INTR_TEST:
173         retvalue = s->timer_intr_test;
174         break;
175     default:
176         qemu_log_mask(LOG_GUEST_ERROR,
177                       "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
178         return 0;
179     }
180 
181     return retvalue;
182 }
183 
184 static void ibex_timer_write(void *opaque, hwaddr addr,
185                              uint64_t val64, unsigned int size)
186 {
187     IbexTimerState *s = opaque;
188     uint32_t val = val64;
189 
190     switch (addr >> 2) {
191     case R_CTRL:
192         s->timer_ctrl = val;
193         break;
194     case R_CFG0:
195         qemu_log_mask(LOG_UNIMP, "Changing prescale or step not supported");
196         s->timer_cfg0 = val;
197         break;
198     case R_LOWER0:
199         qemu_log_mask(LOG_UNIMP, "Changing timer value is not supported");
200         break;
201     case R_UPPER0:
202         qemu_log_mask(LOG_UNIMP, "Changing timer value is not supported");
203         break;
204     case R_COMPARE_LOWER0:
205         s->timer_compare_lower0 = val;
206         ibex_timer_update_irqs(s);
207         break;
208     case R_COMPARE_UPPER0:
209         s->timer_compare_upper0 = val;
210         ibex_timer_update_irqs(s);
211         break;
212     case R_INTR_ENABLE:
213         s->timer_intr_enable = val;
214         break;
215     case R_INTR_STATE:
216         /* Write 1 to clear */
217         s->timer_intr_state &= ~val;
218         break;
219     case R_INTR_TEST:
220         s->timer_intr_test = val;
221         if (s->timer_intr_enable &
222             s->timer_intr_test &
223             R_INTR_ENABLE_IE_0_MASK) {
224             s->timer_intr_state |= R_INTR_STATE_IS_0_MASK;
225             qemu_set_irq(s->irq, true);
226         }
227         break;
228     default:
229         qemu_log_mask(LOG_GUEST_ERROR,
230                       "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
231     }
232 }
233 
234 static const MemoryRegionOps ibex_timer_ops = {
235     .read = ibex_timer_read,
236     .write = ibex_timer_write,
237     .endianness = DEVICE_NATIVE_ENDIAN,
238     .impl.min_access_size = 4,
239     .impl.max_access_size = 4,
240 };
241 
242 static int ibex_timer_post_load(void *opaque, int version_id)
243 {
244     IbexTimerState *s = opaque;
245 
246     ibex_timer_update_irqs(s);
247     return 0;
248 }
249 
250 static const VMStateDescription vmstate_ibex_timer = {
251     .name = TYPE_IBEX_TIMER,
252     .version_id = 1,
253     .minimum_version_id = 1,
254     .post_load = ibex_timer_post_load,
255     .fields = (VMStateField[]) {
256         VMSTATE_UINT32(timer_ctrl, IbexTimerState),
257         VMSTATE_UINT32(timer_cfg0, IbexTimerState),
258         VMSTATE_UINT32(timer_compare_lower0, IbexTimerState),
259         VMSTATE_UINT32(timer_compare_upper0, IbexTimerState),
260         VMSTATE_UINT32(timer_intr_enable, IbexTimerState),
261         VMSTATE_UINT32(timer_intr_state, IbexTimerState),
262         VMSTATE_UINT32(timer_intr_test, IbexTimerState),
263         VMSTATE_END_OF_LIST()
264     }
265 };
266 
267 static Property ibex_timer_properties[] = {
268     DEFINE_PROP_UINT32("timebase-freq", IbexTimerState, timebase_freq, 10000),
269     DEFINE_PROP_END_OF_LIST(),
270 };
271 
272 static void ibex_timer_init(Object *obj)
273 {
274     IbexTimerState *s = IBEX_TIMER(obj);
275 
276     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
277 
278     memory_region_init_io(&s->mmio, obj, &ibex_timer_ops, s,
279                           TYPE_IBEX_TIMER, 0x400);
280     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
281 }
282 
283 static void ibex_timer_class_init(ObjectClass *klass, void *data)
284 {
285     DeviceClass *dc = DEVICE_CLASS(klass);
286 
287     dc->reset = ibex_timer_reset;
288     dc->vmsd = &vmstate_ibex_timer;
289     device_class_set_props(dc, ibex_timer_properties);
290 }
291 
292 static const TypeInfo ibex_timer_info = {
293     .name          = TYPE_IBEX_TIMER,
294     .parent        = TYPE_SYS_BUS_DEVICE,
295     .instance_size = sizeof(IbexTimerState),
296     .instance_init = ibex_timer_init,
297     .class_init    = ibex_timer_class_init,
298 };
299 
300 static void ibex_timer_register_types(void)
301 {
302     type_register_static(&ibex_timer_info);
303 }
304 
305 type_init(ibex_timer_register_types)
306