1 /* 2 * QEMU 8253/8254 - common bits of emulated and KVM kernel model 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2012 Jan Kiszka, Siemens AG 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/isa/isa.h" 28 #include "qemu/module.h" 29 #include "qemu/timer.h" 30 #include "hw/timer/i8254.h" 31 #include "hw/timer/i8254_internal.h" 32 #include "migration/vmstate.h" 33 34 /* val must be 0 or 1 */ 35 void pit_set_gate(ISADevice *dev, int channel, int val) 36 { 37 PITCommonState *pit = PIT_COMMON(dev); 38 PITChannelState *s = &pit->channels[channel]; 39 PITCommonClass *c = PIT_COMMON_GET_CLASS(pit); 40 41 c->set_channel_gate(pit, s, val); 42 } 43 44 /* get pit output bit */ 45 int pit_get_out(PITChannelState *s, int64_t current_time) 46 { 47 uint64_t d; 48 int out; 49 50 d = muldiv64(current_time - s->count_load_time, PIT_FREQ, 51 NANOSECONDS_PER_SECOND); 52 switch (s->mode) { 53 default: 54 case 0: 55 case 1: 56 out = (d >= s->count); 57 break; 58 case 2: 59 if ((d % s->count) == 0 && d != 0) { 60 out = 1; 61 } else { 62 out = 0; 63 } 64 break; 65 case 3: 66 out = (d % s->count) < ((s->count + 1) >> 1); 67 break; 68 case 4: 69 case 5: 70 out = (d == s->count); 71 break; 72 } 73 return out; 74 } 75 76 /* return -1 if no transition will occur. */ 77 int64_t pit_get_next_transition_time(PITChannelState *s, int64_t current_time) 78 { 79 uint64_t d, next_time, base; 80 int period2; 81 82 d = muldiv64(current_time - s->count_load_time, PIT_FREQ, 83 NANOSECONDS_PER_SECOND); 84 switch (s->mode) { 85 default: 86 case 0: 87 case 1: 88 if (d < s->count) { 89 next_time = s->count; 90 } else { 91 return -1; 92 } 93 break; 94 case 2: 95 base = QEMU_ALIGN_DOWN(d, s->count); 96 if ((d - base) == 0 && d != 0) { 97 next_time = base + s->count; 98 } else { 99 next_time = base + s->count + 1; 100 } 101 break; 102 case 3: 103 base = QEMU_ALIGN_DOWN(d, s->count); 104 period2 = ((s->count + 1) >> 1); 105 if ((d - base) < period2) { 106 next_time = base + period2; 107 } else { 108 next_time = base + s->count; 109 } 110 break; 111 case 4: 112 case 5: 113 if (d < s->count) { 114 next_time = s->count; 115 } else if (d == s->count) { 116 next_time = s->count + 1; 117 } else { 118 return -1; 119 } 120 break; 121 } 122 /* convert to timer units */ 123 next_time = s->count_load_time + muldiv64(next_time, NANOSECONDS_PER_SECOND, 124 PIT_FREQ); 125 /* fix potential rounding problems */ 126 /* XXX: better solution: use a clock at PIT_FREQ Hz */ 127 if (next_time <= current_time) { 128 next_time = current_time + 1; 129 } 130 return next_time; 131 } 132 133 void pit_get_channel_info_common(PITCommonState *s, PITChannelState *sc, 134 PITChannelInfo *info) 135 { 136 info->gate = sc->gate; 137 info->mode = sc->mode; 138 info->initial_count = sc->count; 139 info->out = pit_get_out(sc, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 140 } 141 142 void pit_get_channel_info(ISADevice *dev, int channel, PITChannelInfo *info) 143 { 144 PITCommonState *pit = PIT_COMMON(dev); 145 PITChannelState *s = &pit->channels[channel]; 146 PITCommonClass *c = PIT_COMMON_GET_CLASS(pit); 147 148 c->get_channel_info(pit, s, info); 149 } 150 151 void pit_reset_common(PITCommonState *pit) 152 { 153 PITChannelState *s; 154 int i; 155 156 for (i = 0; i < 3; i++) { 157 s = &pit->channels[i]; 158 s->mode = 3; 159 s->gate = (i != 2); 160 s->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 161 s->count = 0x10000; 162 if (i == 0 && !s->irq_disabled) { 163 s->next_transition_time = 164 pit_get_next_transition_time(s, s->count_load_time); 165 } 166 } 167 } 168 169 static void pit_common_realize(DeviceState *dev, Error **errp) 170 { 171 ISADevice *isadev = ISA_DEVICE(dev); 172 PITCommonState *pit = PIT_COMMON(dev); 173 174 isa_register_ioport(isadev, &pit->ioports, pit->iobase); 175 176 qdev_set_legacy_instance_id(dev, pit->iobase, 2); 177 } 178 179 static const VMStateDescription vmstate_pit_channel = { 180 .name = "pit channel", 181 .version_id = 2, 182 .minimum_version_id = 2, 183 .fields = (const VMStateField[]) { 184 VMSTATE_INT32(count, PITChannelState), 185 VMSTATE_UINT16(latched_count, PITChannelState), 186 VMSTATE_UINT8(count_latched, PITChannelState), 187 VMSTATE_UINT8(status_latched, PITChannelState), 188 VMSTATE_UINT8(status, PITChannelState), 189 VMSTATE_UINT8(read_state, PITChannelState), 190 VMSTATE_UINT8(write_state, PITChannelState), 191 VMSTATE_UINT8(write_latch, PITChannelState), 192 VMSTATE_UINT8(rw_mode, PITChannelState), 193 VMSTATE_UINT8(mode, PITChannelState), 194 VMSTATE_UINT8(bcd, PITChannelState), 195 VMSTATE_UINT8(gate, PITChannelState), 196 VMSTATE_INT64(count_load_time, PITChannelState), 197 VMSTATE_INT64(next_transition_time, PITChannelState), 198 VMSTATE_END_OF_LIST() 199 } 200 }; 201 202 static int pit_dispatch_pre_save(void *opaque) 203 { 204 PITCommonState *s = opaque; 205 PITCommonClass *c = PIT_COMMON_GET_CLASS(s); 206 207 if (c->pre_save) { 208 c->pre_save(s); 209 } 210 211 return 0; 212 } 213 214 static int pit_dispatch_post_load(void *opaque, int version_id) 215 { 216 PITCommonState *s = opaque; 217 PITCommonClass *c = PIT_COMMON_GET_CLASS(s); 218 219 if (c->post_load) { 220 c->post_load(s); 221 } 222 return 0; 223 } 224 225 static const VMStateDescription vmstate_pit_common = { 226 .name = "i8254", 227 .version_id = 3, 228 .minimum_version_id = 2, 229 .pre_save = pit_dispatch_pre_save, 230 .post_load = pit_dispatch_post_load, 231 .fields = (const VMStateField[]) { 232 VMSTATE_UINT32_V(channels[0].irq_disabled, PITCommonState, 3), 233 VMSTATE_STRUCT_ARRAY(channels, PITCommonState, 3, 2, 234 vmstate_pit_channel, PITChannelState), 235 VMSTATE_INT64(channels[0].next_transition_time, 236 PITCommonState), /* formerly irq_timer */ 237 VMSTATE_END_OF_LIST() 238 } 239 }; 240 241 static Property pit_common_properties[] = { 242 DEFINE_PROP_UINT32("iobase", PITCommonState, iobase, -1), 243 DEFINE_PROP_END_OF_LIST(), 244 }; 245 246 static void pit_common_class_init(ObjectClass *klass, void *data) 247 { 248 DeviceClass *dc = DEVICE_CLASS(klass); 249 250 dc->realize = pit_common_realize; 251 dc->vmsd = &vmstate_pit_common; 252 /* 253 * Reason: unlike ordinary ISA devices, the PIT may need to be 254 * wired to the HPET, and because of that, some wiring is always 255 * done by board code. 256 */ 257 dc->user_creatable = false; 258 device_class_set_props(dc, pit_common_properties); 259 } 260 261 static const TypeInfo pit_common_type = { 262 .name = TYPE_PIT_COMMON, 263 .parent = TYPE_ISA_DEVICE, 264 .instance_size = sizeof(PITCommonState), 265 .class_size = sizeof(PITCommonClass), 266 .class_init = pit_common_class_init, 267 .abstract = true, 268 }; 269 270 static void register_devices(void) 271 { 272 type_register_static(&pit_common_type); 273 } 274 275 type_init(register_devices); 276