1 /* 2 * QEMU 8253/8254 - common bits of emulated and KVM kernel model 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2012 Jan Kiszka, Siemens AG 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/hw.h" 28 #include "hw/isa/isa.h" 29 #include "qemu/module.h" 30 #include "qemu/timer.h" 31 #include "hw/timer/i8254.h" 32 #include "hw/timer/i8254_internal.h" 33 #include "migration/qemu-file-types.h" 34 35 /* val must be 0 or 1 */ 36 void pit_set_gate(ISADevice *dev, int channel, int val) 37 { 38 PITCommonState *pit = PIT_COMMON(dev); 39 PITChannelState *s = &pit->channels[channel]; 40 PITCommonClass *c = PIT_COMMON_GET_CLASS(pit); 41 42 c->set_channel_gate(pit, s, val); 43 } 44 45 /* get pit output bit */ 46 int pit_get_out(PITChannelState *s, int64_t current_time) 47 { 48 uint64_t d; 49 int out; 50 51 d = muldiv64(current_time - s->count_load_time, PIT_FREQ, 52 NANOSECONDS_PER_SECOND); 53 switch (s->mode) { 54 default: 55 case 0: 56 out = (d >= s->count); 57 break; 58 case 1: 59 out = (d < s->count); 60 break; 61 case 2: 62 if ((d % s->count) == 0 && d != 0) { 63 out = 1; 64 } else { 65 out = 0; 66 } 67 break; 68 case 3: 69 out = (d % s->count) < ((s->count + 1) >> 1); 70 break; 71 case 4: 72 case 5: 73 out = (d == s->count); 74 break; 75 } 76 return out; 77 } 78 79 /* return -1 if no transition will occur. */ 80 int64_t pit_get_next_transition_time(PITChannelState *s, int64_t current_time) 81 { 82 uint64_t d, next_time, base; 83 int period2; 84 85 d = muldiv64(current_time - s->count_load_time, PIT_FREQ, 86 NANOSECONDS_PER_SECOND); 87 switch (s->mode) { 88 default: 89 case 0: 90 case 1: 91 if (d < s->count) { 92 next_time = s->count; 93 } else { 94 return -1; 95 } 96 break; 97 case 2: 98 base = QEMU_ALIGN_DOWN(d, s->count); 99 if ((d - base) == 0 && d != 0) { 100 next_time = base + s->count; 101 } else { 102 next_time = base + s->count + 1; 103 } 104 break; 105 case 3: 106 base = QEMU_ALIGN_DOWN(d, s->count); 107 period2 = ((s->count + 1) >> 1); 108 if ((d - base) < period2) { 109 next_time = base + period2; 110 } else { 111 next_time = base + s->count; 112 } 113 break; 114 case 4: 115 case 5: 116 if (d < s->count) { 117 next_time = s->count; 118 } else if (d == s->count) { 119 next_time = s->count + 1; 120 } else { 121 return -1; 122 } 123 break; 124 } 125 /* convert to timer units */ 126 next_time = s->count_load_time + muldiv64(next_time, NANOSECONDS_PER_SECOND, 127 PIT_FREQ); 128 /* fix potential rounding problems */ 129 /* XXX: better solution: use a clock at PIT_FREQ Hz */ 130 if (next_time <= current_time) { 131 next_time = current_time + 1; 132 } 133 return next_time; 134 } 135 136 void pit_get_channel_info_common(PITCommonState *s, PITChannelState *sc, 137 PITChannelInfo *info) 138 { 139 info->gate = sc->gate; 140 info->mode = sc->mode; 141 info->initial_count = sc->count; 142 info->out = pit_get_out(sc, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 143 } 144 145 void pit_get_channel_info(ISADevice *dev, int channel, PITChannelInfo *info) 146 { 147 PITCommonState *pit = PIT_COMMON(dev); 148 PITChannelState *s = &pit->channels[channel]; 149 PITCommonClass *c = PIT_COMMON_GET_CLASS(pit); 150 151 c->get_channel_info(pit, s, info); 152 } 153 154 void pit_reset_common(PITCommonState *pit) 155 { 156 PITChannelState *s; 157 int i; 158 159 for (i = 0; i < 3; i++) { 160 s = &pit->channels[i]; 161 s->mode = 3; 162 s->gate = (i != 2); 163 s->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 164 s->count = 0x10000; 165 if (i == 0 && !s->irq_disabled) { 166 s->next_transition_time = 167 pit_get_next_transition_time(s, s->count_load_time); 168 } 169 } 170 } 171 172 static void pit_common_realize(DeviceState *dev, Error **errp) 173 { 174 ISADevice *isadev = ISA_DEVICE(dev); 175 PITCommonState *pit = PIT_COMMON(dev); 176 177 isa_register_ioport(isadev, &pit->ioports, pit->iobase); 178 179 qdev_set_legacy_instance_id(dev, pit->iobase, 2); 180 } 181 182 static const VMStateDescription vmstate_pit_channel = { 183 .name = "pit channel", 184 .version_id = 2, 185 .minimum_version_id = 2, 186 .fields = (VMStateField[]) { 187 VMSTATE_INT32(count, PITChannelState), 188 VMSTATE_UINT16(latched_count, PITChannelState), 189 VMSTATE_UINT8(count_latched, PITChannelState), 190 VMSTATE_UINT8(status_latched, PITChannelState), 191 VMSTATE_UINT8(status, PITChannelState), 192 VMSTATE_UINT8(read_state, PITChannelState), 193 VMSTATE_UINT8(write_state, PITChannelState), 194 VMSTATE_UINT8(write_latch, PITChannelState), 195 VMSTATE_UINT8(rw_mode, PITChannelState), 196 VMSTATE_UINT8(mode, PITChannelState), 197 VMSTATE_UINT8(bcd, PITChannelState), 198 VMSTATE_UINT8(gate, PITChannelState), 199 VMSTATE_INT64(count_load_time, PITChannelState), 200 VMSTATE_INT64(next_transition_time, PITChannelState), 201 VMSTATE_END_OF_LIST() 202 } 203 }; 204 205 static int pit_load_old(QEMUFile *f, void *opaque, int version_id) 206 { 207 PITCommonState *pit = opaque; 208 PITCommonClass *c = PIT_COMMON_GET_CLASS(pit); 209 PITChannelState *s; 210 int i; 211 212 if (version_id != 1) { 213 return -EINVAL; 214 } 215 216 for (i = 0; i < 3; i++) { 217 s = &pit->channels[i]; 218 s->count = qemu_get_be32(f); 219 qemu_get_be16s(f, &s->latched_count); 220 qemu_get_8s(f, &s->count_latched); 221 qemu_get_8s(f, &s->status_latched); 222 qemu_get_8s(f, &s->status); 223 qemu_get_8s(f, &s->read_state); 224 qemu_get_8s(f, &s->write_state); 225 qemu_get_8s(f, &s->write_latch); 226 qemu_get_8s(f, &s->rw_mode); 227 qemu_get_8s(f, &s->mode); 228 qemu_get_8s(f, &s->bcd); 229 qemu_get_8s(f, &s->gate); 230 s->count_load_time = qemu_get_be64(f); 231 s->irq_disabled = 0; 232 if (i == 0) { 233 s->next_transition_time = qemu_get_be64(f); 234 } 235 } 236 if (c->post_load) { 237 c->post_load(pit); 238 } 239 return 0; 240 } 241 242 static int pit_dispatch_pre_save(void *opaque) 243 { 244 PITCommonState *s = opaque; 245 PITCommonClass *c = PIT_COMMON_GET_CLASS(s); 246 247 if (c->pre_save) { 248 c->pre_save(s); 249 } 250 251 return 0; 252 } 253 254 static int pit_dispatch_post_load(void *opaque, int version_id) 255 { 256 PITCommonState *s = opaque; 257 PITCommonClass *c = PIT_COMMON_GET_CLASS(s); 258 259 if (c->post_load) { 260 c->post_load(s); 261 } 262 return 0; 263 } 264 265 static const VMStateDescription vmstate_pit_common = { 266 .name = "i8254", 267 .version_id = 3, 268 .minimum_version_id = 2, 269 .minimum_version_id_old = 1, 270 .load_state_old = pit_load_old, 271 .pre_save = pit_dispatch_pre_save, 272 .post_load = pit_dispatch_post_load, 273 .fields = (VMStateField[]) { 274 VMSTATE_UINT32_V(channels[0].irq_disabled, PITCommonState, 3), 275 VMSTATE_STRUCT_ARRAY(channels, PITCommonState, 3, 2, 276 vmstate_pit_channel, PITChannelState), 277 VMSTATE_INT64(channels[0].next_transition_time, 278 PITCommonState), /* formerly irq_timer */ 279 VMSTATE_END_OF_LIST() 280 } 281 }; 282 283 static void pit_common_class_init(ObjectClass *klass, void *data) 284 { 285 DeviceClass *dc = DEVICE_CLASS(klass); 286 287 dc->realize = pit_common_realize; 288 dc->vmsd = &vmstate_pit_common; 289 /* 290 * Reason: unlike ordinary ISA devices, the PIT may need to be 291 * wired to the HPET, and because of that, some wiring is always 292 * done by board code. 293 */ 294 dc->user_creatable = false; 295 } 296 297 static const TypeInfo pit_common_type = { 298 .name = TYPE_PIT_COMMON, 299 .parent = TYPE_ISA_DEVICE, 300 .instance_size = sizeof(PITCommonState), 301 .class_size = sizeof(PITCommonClass), 302 .class_init = pit_common_class_init, 303 .abstract = true, 304 }; 305 306 static void register_devices(void) 307 { 308 type_register_static(&pit_common_type); 309 } 310 311 type_init(register_devices); 312