1 /* 2 * QEMU 8253/8254 interval timer emulation 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/hw.h" 27 #include "hw/irq.h" 28 #include "qemu/module.h" 29 #include "qemu/timer.h" 30 #include "hw/timer/i8254.h" 31 #include "hw/timer/i8254_internal.h" 32 33 //#define DEBUG_PIT 34 35 #define RW_STATE_LSB 1 36 #define RW_STATE_MSB 2 37 #define RW_STATE_WORD0 3 38 #define RW_STATE_WORD1 4 39 40 #define PIT_CLASS(class) OBJECT_CLASS_CHECK(PITClass, (class), TYPE_I8254) 41 #define PIT_GET_CLASS(obj) OBJECT_GET_CLASS(PITClass, (obj), TYPE_I8254) 42 43 typedef struct PITClass { 44 PITCommonClass parent_class; 45 46 DeviceRealize parent_realize; 47 } PITClass; 48 49 static void pit_irq_timer_update(PITChannelState *s, int64_t current_time); 50 51 static int pit_get_count(PITChannelState *s) 52 { 53 uint64_t d; 54 int counter; 55 56 d = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->count_load_time, PIT_FREQ, 57 NANOSECONDS_PER_SECOND); 58 switch(s->mode) { 59 case 0: 60 case 1: 61 case 4: 62 case 5: 63 counter = (s->count - d) & 0xffff; 64 break; 65 case 3: 66 /* XXX: may be incorrect for odd counts */ 67 counter = s->count - ((2 * d) % s->count); 68 break; 69 default: 70 counter = s->count - (d % s->count); 71 break; 72 } 73 return counter; 74 } 75 76 /* val must be 0 or 1 */ 77 static void pit_set_channel_gate(PITCommonState *s, PITChannelState *sc, 78 int val) 79 { 80 switch (sc->mode) { 81 default: 82 case 0: 83 case 4: 84 /* XXX: just disable/enable counting */ 85 break; 86 case 1: 87 case 5: 88 if (sc->gate < val) { 89 /* restart counting on rising edge */ 90 sc->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 91 pit_irq_timer_update(sc, sc->count_load_time); 92 } 93 break; 94 case 2: 95 case 3: 96 if (sc->gate < val) { 97 /* restart counting on rising edge */ 98 sc->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 99 pit_irq_timer_update(sc, sc->count_load_time); 100 } 101 /* XXX: disable/enable counting */ 102 break; 103 } 104 sc->gate = val; 105 } 106 107 static inline void pit_load_count(PITChannelState *s, int val) 108 { 109 if (val == 0) 110 val = 0x10000; 111 s->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 112 s->count = val; 113 pit_irq_timer_update(s, s->count_load_time); 114 } 115 116 /* if already latched, do not latch again */ 117 static void pit_latch_count(PITChannelState *s) 118 { 119 if (!s->count_latched) { 120 s->latched_count = pit_get_count(s); 121 s->count_latched = s->rw_mode; 122 } 123 } 124 125 static void pit_ioport_write(void *opaque, hwaddr addr, 126 uint64_t val, unsigned size) 127 { 128 PITCommonState *pit = opaque; 129 int channel, access; 130 PITChannelState *s; 131 132 addr &= 3; 133 if (addr == 3) { 134 channel = val >> 6; 135 if (channel == 3) { 136 /* read back command */ 137 for(channel = 0; channel < 3; channel++) { 138 s = &pit->channels[channel]; 139 if (val & (2 << channel)) { 140 if (!(val & 0x20)) { 141 pit_latch_count(s); 142 } 143 if (!(val & 0x10) && !s->status_latched) { 144 /* status latch */ 145 /* XXX: add BCD and null count */ 146 s->status = 147 (pit_get_out(s, 148 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) << 7) | 149 (s->rw_mode << 4) | 150 (s->mode << 1) | 151 s->bcd; 152 s->status_latched = 1; 153 } 154 } 155 } 156 } else { 157 s = &pit->channels[channel]; 158 access = (val >> 4) & 3; 159 if (access == 0) { 160 pit_latch_count(s); 161 } else { 162 s->rw_mode = access; 163 s->read_state = access; 164 s->write_state = access; 165 166 s->mode = (val >> 1) & 7; 167 s->bcd = val & 1; 168 /* XXX: update irq timer ? */ 169 } 170 } 171 } else { 172 s = &pit->channels[addr]; 173 switch(s->write_state) { 174 default: 175 case RW_STATE_LSB: 176 pit_load_count(s, val); 177 break; 178 case RW_STATE_MSB: 179 pit_load_count(s, val << 8); 180 break; 181 case RW_STATE_WORD0: 182 s->write_latch = val; 183 s->write_state = RW_STATE_WORD1; 184 break; 185 case RW_STATE_WORD1: 186 pit_load_count(s, s->write_latch | (val << 8)); 187 s->write_state = RW_STATE_WORD0; 188 break; 189 } 190 } 191 } 192 193 static uint64_t pit_ioport_read(void *opaque, hwaddr addr, 194 unsigned size) 195 { 196 PITCommonState *pit = opaque; 197 int ret, count; 198 PITChannelState *s; 199 200 addr &= 3; 201 202 if (addr == 3) { 203 /* Mode/Command register is write only, read is ignored */ 204 return 0; 205 } 206 207 s = &pit->channels[addr]; 208 if (s->status_latched) { 209 s->status_latched = 0; 210 ret = s->status; 211 } else if (s->count_latched) { 212 switch(s->count_latched) { 213 default: 214 case RW_STATE_LSB: 215 ret = s->latched_count & 0xff; 216 s->count_latched = 0; 217 break; 218 case RW_STATE_MSB: 219 ret = s->latched_count >> 8; 220 s->count_latched = 0; 221 break; 222 case RW_STATE_WORD0: 223 ret = s->latched_count & 0xff; 224 s->count_latched = RW_STATE_MSB; 225 break; 226 } 227 } else { 228 switch(s->read_state) { 229 default: 230 case RW_STATE_LSB: 231 count = pit_get_count(s); 232 ret = count & 0xff; 233 break; 234 case RW_STATE_MSB: 235 count = pit_get_count(s); 236 ret = (count >> 8) & 0xff; 237 break; 238 case RW_STATE_WORD0: 239 count = pit_get_count(s); 240 ret = count & 0xff; 241 s->read_state = RW_STATE_WORD1; 242 break; 243 case RW_STATE_WORD1: 244 count = pit_get_count(s); 245 ret = (count >> 8) & 0xff; 246 s->read_state = RW_STATE_WORD0; 247 break; 248 } 249 } 250 return ret; 251 } 252 253 static void pit_irq_timer_update(PITChannelState *s, int64_t current_time) 254 { 255 int64_t expire_time; 256 int irq_level; 257 258 if (!s->irq_timer || s->irq_disabled) { 259 return; 260 } 261 expire_time = pit_get_next_transition_time(s, current_time); 262 irq_level = pit_get_out(s, current_time); 263 qemu_set_irq(s->irq, irq_level); 264 #ifdef DEBUG_PIT 265 printf("irq_level=%d next_delay=%f\n", 266 irq_level, 267 (double)(expire_time - current_time) / NANOSECONDS_PER_SECOND); 268 #endif 269 s->next_transition_time = expire_time; 270 if (expire_time != -1) 271 timer_mod(s->irq_timer, expire_time); 272 else 273 timer_del(s->irq_timer); 274 } 275 276 static void pit_irq_timer(void *opaque) 277 { 278 PITChannelState *s = opaque; 279 280 pit_irq_timer_update(s, s->next_transition_time); 281 } 282 283 static void pit_reset(DeviceState *dev) 284 { 285 PITCommonState *pit = PIT_COMMON(dev); 286 PITChannelState *s; 287 288 pit_reset_common(pit); 289 290 s = &pit->channels[0]; 291 if (!s->irq_disabled) { 292 timer_mod(s->irq_timer, s->next_transition_time); 293 } 294 } 295 296 /* When HPET is operating in legacy mode, suppress the ignored timer IRQ, 297 * reenable it when legacy mode is left again. */ 298 static void pit_irq_control(void *opaque, int n, int enable) 299 { 300 PITCommonState *pit = opaque; 301 PITChannelState *s = &pit->channels[0]; 302 303 if (enable) { 304 s->irq_disabled = 0; 305 pit_irq_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 306 } else { 307 s->irq_disabled = 1; 308 timer_del(s->irq_timer); 309 } 310 } 311 312 static const MemoryRegionOps pit_ioport_ops = { 313 .read = pit_ioport_read, 314 .write = pit_ioport_write, 315 .impl = { 316 .min_access_size = 1, 317 .max_access_size = 1, 318 }, 319 .endianness = DEVICE_LITTLE_ENDIAN, 320 }; 321 322 static void pit_post_load(PITCommonState *s) 323 { 324 PITChannelState *sc = &s->channels[0]; 325 326 if (sc->next_transition_time != -1) { 327 timer_mod(sc->irq_timer, sc->next_transition_time); 328 } else { 329 timer_del(sc->irq_timer); 330 } 331 } 332 333 static void pit_realizefn(DeviceState *dev, Error **errp) 334 { 335 PITCommonState *pit = PIT_COMMON(dev); 336 PITClass *pc = PIT_GET_CLASS(dev); 337 PITChannelState *s; 338 339 s = &pit->channels[0]; 340 /* the timer 0 is connected to an IRQ */ 341 s->irq_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pit_irq_timer, s); 342 qdev_init_gpio_out(dev, &s->irq, 1); 343 344 memory_region_init_io(&pit->ioports, OBJECT(pit), &pit_ioport_ops, 345 pit, "pit", 4); 346 347 qdev_init_gpio_in(dev, pit_irq_control, 1); 348 349 pc->parent_realize(dev, errp); 350 } 351 352 static Property pit_properties[] = { 353 DEFINE_PROP_UINT32("iobase", PITCommonState, iobase, -1), 354 DEFINE_PROP_END_OF_LIST(), 355 }; 356 357 static void pit_class_initfn(ObjectClass *klass, void *data) 358 { 359 PITClass *pc = PIT_CLASS(klass); 360 PITCommonClass *k = PIT_COMMON_CLASS(klass); 361 DeviceClass *dc = DEVICE_CLASS(klass); 362 363 device_class_set_parent_realize(dc, pit_realizefn, &pc->parent_realize); 364 k->set_channel_gate = pit_set_channel_gate; 365 k->get_channel_info = pit_get_channel_info_common; 366 k->post_load = pit_post_load; 367 dc->reset = pit_reset; 368 dc->props = pit_properties; 369 } 370 371 static const TypeInfo pit_info = { 372 .name = TYPE_I8254, 373 .parent = TYPE_PIT_COMMON, 374 .instance_size = sizeof(PITCommonState), 375 .class_init = pit_class_initfn, 376 .class_size = sizeof(PITClass), 377 }; 378 379 static void pit_register_types(void) 380 { 381 type_register_static(&pit_info); 382 } 383 384 type_init(pit_register_types) 385