1 /* 2 * Samsung exynos4210 Pulse Width Modulation Timer 3 * 4 * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd. 5 * All rights reserved. 6 * 7 * Evgeny Voevodin <e.voevodin@samsung.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 17 * See the GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qemu/log.h" 25 #include "hw/sysbus.h" 26 #include "migration/vmstate.h" 27 #include "qemu/timer.h" 28 #include "qemu/module.h" 29 #include "hw/ptimer.h" 30 31 #include "hw/arm/exynos4210.h" 32 #include "hw/irq.h" 33 #include "qom/object.h" 34 35 //#define DEBUG_PWM 36 37 #ifdef DEBUG_PWM 38 #define DPRINTF(fmt, ...) \ 39 do { fprintf(stdout, "PWM: [%24s:%5d] " fmt, __func__, __LINE__, \ 40 ## __VA_ARGS__); } while (0) 41 #else 42 #define DPRINTF(fmt, ...) do {} while (0) 43 #endif 44 45 #define EXYNOS4210_PWM_TIMERS_NUM 5 46 #define EXYNOS4210_PWM_REG_MEM_SIZE 0x50 47 48 #define TCFG0 0x0000 49 #define TCFG1 0x0004 50 #define TCON 0x0008 51 #define TCNTB0 0x000C 52 #define TCMPB0 0x0010 53 #define TCNTO0 0x0014 54 #define TCNTB1 0x0018 55 #define TCMPB1 0x001C 56 #define TCNTO1 0x0020 57 #define TCNTB2 0x0024 58 #define TCMPB2 0x0028 59 #define TCNTO2 0x002C 60 #define TCNTB3 0x0030 61 #define TCMPB3 0x0034 62 #define TCNTO3 0x0038 63 #define TCNTB4 0x003C 64 #define TCNTO4 0x0040 65 #define TINT_CSTAT 0x0044 66 67 #define TCNTB(x) (0xC * (x)) 68 #define TCMPB(x) (0xC * (x) + 1) 69 #define TCNTO(x) (0xC * (x) + 2) 70 71 #define GET_PRESCALER(reg, x) (((reg) & (0xFF << (8 * (x)))) >> 8 * (x)) 72 #define GET_DIVIDER(reg, x) (1 << (((reg) & (0xF << (4 * (x)))) >> (4 * (x)))) 73 74 /* 75 * Attention! Timer4 doesn't have OUTPUT_INVERTER, 76 * so Auto Reload bit is not accessible by macros! 77 */ 78 #define TCON_TIMER_BASE(x) (((x) ? 1 : 0) * 4 + 4 * (x)) 79 #define TCON_TIMER_START(x) (1 << (TCON_TIMER_BASE(x) + 0)) 80 #define TCON_TIMER_MANUAL_UPD(x) (1 << (TCON_TIMER_BASE(x) + 1)) 81 #define TCON_TIMER_OUTPUT_INV(x) (1 << (TCON_TIMER_BASE(x) + 2)) 82 #define TCON_TIMER_AUTO_RELOAD(x) (1 << (TCON_TIMER_BASE(x) + 3)) 83 #define TCON_TIMER4_AUTO_RELOAD (1 << 22) 84 85 #define TINT_CSTAT_STATUS(x) (1 << (5 + (x))) 86 #define TINT_CSTAT_ENABLE(x) (1 << (x)) 87 88 /* timer struct */ 89 typedef struct { 90 uint32_t id; /* timer id */ 91 qemu_irq irq; /* local timer irq */ 92 uint32_t freq; /* timer frequency */ 93 94 /* use ptimer.c to represent count down timer */ 95 ptimer_state *ptimer; /* timer */ 96 97 /* registers */ 98 uint32_t reg_tcntb; /* counter register buffer */ 99 uint32_t reg_tcmpb; /* compare register buffer */ 100 101 struct Exynos4210PWMState *parent; 102 103 } Exynos4210PWM; 104 105 #define TYPE_EXYNOS4210_PWM "exynos4210.pwm" 106 typedef struct Exynos4210PWMState Exynos4210PWMState; 107 DECLARE_INSTANCE_CHECKER(Exynos4210PWMState, EXYNOS4210_PWM, 108 TYPE_EXYNOS4210_PWM) 109 110 struct Exynos4210PWMState { 111 SysBusDevice parent_obj; 112 113 MemoryRegion iomem; 114 115 uint32_t reg_tcfg[2]; 116 uint32_t reg_tcon; 117 uint32_t reg_tint_cstat; 118 119 Exynos4210PWM timer[EXYNOS4210_PWM_TIMERS_NUM]; 120 121 }; 122 123 /*** VMState ***/ 124 static const VMStateDescription vmstate_exynos4210_pwm = { 125 .name = "exynos4210.pwm.pwm", 126 .version_id = 1, 127 .minimum_version_id = 1, 128 .fields = (VMStateField[]) { 129 VMSTATE_UINT32(id, Exynos4210PWM), 130 VMSTATE_UINT32(freq, Exynos4210PWM), 131 VMSTATE_PTIMER(ptimer, Exynos4210PWM), 132 VMSTATE_UINT32(reg_tcntb, Exynos4210PWM), 133 VMSTATE_UINT32(reg_tcmpb, Exynos4210PWM), 134 VMSTATE_END_OF_LIST() 135 } 136 }; 137 138 static const VMStateDescription vmstate_exynos4210_pwm_state = { 139 .name = "exynos4210.pwm", 140 .version_id = 1, 141 .minimum_version_id = 1, 142 .fields = (VMStateField[]) { 143 VMSTATE_UINT32_ARRAY(reg_tcfg, Exynos4210PWMState, 2), 144 VMSTATE_UINT32(reg_tcon, Exynos4210PWMState), 145 VMSTATE_UINT32(reg_tint_cstat, Exynos4210PWMState), 146 VMSTATE_STRUCT_ARRAY(timer, Exynos4210PWMState, 147 EXYNOS4210_PWM_TIMERS_NUM, 0, 148 vmstate_exynos4210_pwm, Exynos4210PWM), 149 VMSTATE_END_OF_LIST() 150 } 151 }; 152 153 /* 154 * PWM update frequency. 155 * Must be called within a ptimer_transaction_begin/commit block 156 * for s->timer[id].ptimer. 157 */ 158 static void exynos4210_pwm_update_freq(Exynos4210PWMState *s, uint32_t id) 159 { 160 uint32_t freq; 161 freq = s->timer[id].freq; 162 if (id > 1) { 163 s->timer[id].freq = 24000000 / 164 ((GET_PRESCALER(s->reg_tcfg[0], 1) + 1) * 165 (GET_DIVIDER(s->reg_tcfg[1], id))); 166 } else { 167 s->timer[id].freq = 24000000 / 168 ((GET_PRESCALER(s->reg_tcfg[0], 0) + 1) * 169 (GET_DIVIDER(s->reg_tcfg[1], id))); 170 } 171 172 if (freq != s->timer[id].freq) { 173 ptimer_set_freq(s->timer[id].ptimer, s->timer[id].freq); 174 DPRINTF("freq=%dHz\n", s->timer[id].freq); 175 } 176 } 177 178 /* 179 * Counter tick handler 180 */ 181 static void exynos4210_pwm_tick(void *opaque) 182 { 183 Exynos4210PWM *s = (Exynos4210PWM *)opaque; 184 Exynos4210PWMState *p = (Exynos4210PWMState *)s->parent; 185 uint32_t id = s->id; 186 bool cmp; 187 188 DPRINTF("timer %d tick\n", id); 189 190 /* set irq status */ 191 p->reg_tint_cstat |= TINT_CSTAT_STATUS(id); 192 193 /* raise IRQ */ 194 if (p->reg_tint_cstat & TINT_CSTAT_ENABLE(id)) { 195 DPRINTF("timer %d IRQ\n", id); 196 qemu_irq_raise(p->timer[id].irq); 197 } 198 199 /* reload timer */ 200 if (id != 4) { 201 cmp = p->reg_tcon & TCON_TIMER_AUTO_RELOAD(id); 202 } else { 203 cmp = p->reg_tcon & TCON_TIMER4_AUTO_RELOAD; 204 } 205 206 if (cmp) { 207 DPRINTF("auto reload timer %d count to %x\n", id, 208 p->timer[id].reg_tcntb); 209 ptimer_set_count(p->timer[id].ptimer, p->timer[id].reg_tcntb); 210 ptimer_run(p->timer[id].ptimer, 1); 211 } else { 212 /* stop timer, set status to STOP, see Basic Timer Operation */ 213 p->reg_tcon &= ~TCON_TIMER_START(id); 214 ptimer_stop(p->timer[id].ptimer); 215 } 216 } 217 218 /* 219 * PWM Read 220 */ 221 static uint64_t exynos4210_pwm_read(void *opaque, hwaddr offset, 222 unsigned size) 223 { 224 Exynos4210PWMState *s = (Exynos4210PWMState *)opaque; 225 uint32_t value = 0; 226 int index; 227 228 switch (offset) { 229 case TCFG0: case TCFG1: 230 index = (offset - TCFG0) >> 2; 231 value = s->reg_tcfg[index]; 232 break; 233 234 case TCON: 235 value = s->reg_tcon; 236 break; 237 238 case TCNTB0: case TCNTB1: 239 case TCNTB2: case TCNTB3: case TCNTB4: 240 index = (offset - TCNTB0) / 0xC; 241 value = s->timer[index].reg_tcntb; 242 break; 243 244 case TCMPB0: case TCMPB1: 245 case TCMPB2: case TCMPB3: 246 index = (offset - TCMPB0) / 0xC; 247 value = s->timer[index].reg_tcmpb; 248 break; 249 250 case TCNTO0: case TCNTO1: 251 case TCNTO2: case TCNTO3: case TCNTO4: 252 index = (offset == TCNTO4) ? 4 : (offset - TCNTO0) / 0xC; 253 value = ptimer_get_count(s->timer[index].ptimer); 254 break; 255 256 case TINT_CSTAT: 257 value = s->reg_tint_cstat; 258 break; 259 260 default: 261 qemu_log_mask(LOG_GUEST_ERROR, 262 "exynos4210.pwm: bad read offset " TARGET_FMT_plx, 263 offset); 264 break; 265 } 266 return value; 267 } 268 269 /* 270 * PWM Write 271 */ 272 static void exynos4210_pwm_write(void *opaque, hwaddr offset, 273 uint64_t value, unsigned size) 274 { 275 Exynos4210PWMState *s = (Exynos4210PWMState *)opaque; 276 int index; 277 uint32_t new_val; 278 int i; 279 280 switch (offset) { 281 case TCFG0: case TCFG1: 282 index = (offset - TCFG0) >> 2; 283 s->reg_tcfg[index] = value; 284 285 /* update timers frequencies */ 286 for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) { 287 ptimer_transaction_begin(s->timer[i].ptimer); 288 exynos4210_pwm_update_freq(s, s->timer[i].id); 289 ptimer_transaction_commit(s->timer[i].ptimer); 290 } 291 break; 292 293 case TCON: 294 for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) { 295 ptimer_transaction_begin(s->timer[i].ptimer); 296 if ((value & TCON_TIMER_MANUAL_UPD(i)) > 297 (s->reg_tcon & TCON_TIMER_MANUAL_UPD(i))) { 298 /* 299 * TCNTB and TCMPB are loaded into TCNT and TCMP. 300 * Update timers. 301 */ 302 303 /* this will start timer to run, this ok, because 304 * during processing start bit timer will be stopped 305 * if needed */ 306 ptimer_set_count(s->timer[i].ptimer, s->timer[i].reg_tcntb); 307 DPRINTF("set timer %d count to %x\n", i, 308 s->timer[i].reg_tcntb); 309 } 310 311 if ((value & TCON_TIMER_START(i)) > 312 (s->reg_tcon & TCON_TIMER_START(i))) { 313 /* changed to start */ 314 ptimer_run(s->timer[i].ptimer, 1); 315 DPRINTF("run timer %d\n", i); 316 } 317 318 if ((value & TCON_TIMER_START(i)) < 319 (s->reg_tcon & TCON_TIMER_START(i))) { 320 /* changed to stop */ 321 ptimer_stop(s->timer[i].ptimer); 322 DPRINTF("stop timer %d\n", i); 323 } 324 ptimer_transaction_commit(s->timer[i].ptimer); 325 } 326 s->reg_tcon = value; 327 break; 328 329 case TCNTB0: case TCNTB1: 330 case TCNTB2: case TCNTB3: case TCNTB4: 331 index = (offset - TCNTB0) / 0xC; 332 s->timer[index].reg_tcntb = value; 333 break; 334 335 case TCMPB0: case TCMPB1: 336 case TCMPB2: case TCMPB3: 337 index = (offset - TCMPB0) / 0xC; 338 s->timer[index].reg_tcmpb = value; 339 break; 340 341 case TINT_CSTAT: 342 new_val = (s->reg_tint_cstat & 0x3E0) + (0x1F & value); 343 new_val &= ~(0x3E0 & value); 344 345 for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) { 346 if ((new_val & TINT_CSTAT_STATUS(i)) < 347 (s->reg_tint_cstat & TINT_CSTAT_STATUS(i))) { 348 qemu_irq_lower(s->timer[i].irq); 349 } 350 } 351 352 s->reg_tint_cstat = new_val; 353 break; 354 355 default: 356 qemu_log_mask(LOG_GUEST_ERROR, 357 "exynos4210.pwm: bad write offset " TARGET_FMT_plx, 358 offset); 359 break; 360 361 } 362 } 363 364 /* 365 * Set default values to timer fields and registers 366 */ 367 static void exynos4210_pwm_reset(DeviceState *d) 368 { 369 Exynos4210PWMState *s = EXYNOS4210_PWM(d); 370 int i; 371 s->reg_tcfg[0] = 0x0101; 372 s->reg_tcfg[1] = 0x0; 373 s->reg_tcon = 0; 374 s->reg_tint_cstat = 0; 375 for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) { 376 s->timer[i].reg_tcmpb = 0; 377 s->timer[i].reg_tcntb = 0; 378 379 ptimer_transaction_begin(s->timer[i].ptimer); 380 exynos4210_pwm_update_freq(s, s->timer[i].id); 381 ptimer_stop(s->timer[i].ptimer); 382 ptimer_transaction_commit(s->timer[i].ptimer); 383 } 384 } 385 386 static const MemoryRegionOps exynos4210_pwm_ops = { 387 .read = exynos4210_pwm_read, 388 .write = exynos4210_pwm_write, 389 .endianness = DEVICE_NATIVE_ENDIAN, 390 }; 391 392 /* 393 * PWM timer initialization 394 */ 395 static void exynos4210_pwm_init(Object *obj) 396 { 397 Exynos4210PWMState *s = EXYNOS4210_PWM(obj); 398 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 399 int i; 400 401 for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) { 402 sysbus_init_irq(dev, &s->timer[i].irq); 403 s->timer[i].ptimer = ptimer_init(exynos4210_pwm_tick, 404 &s->timer[i], 405 PTIMER_POLICY_DEFAULT); 406 s->timer[i].id = i; 407 s->timer[i].parent = s; 408 } 409 410 memory_region_init_io(&s->iomem, obj, &exynos4210_pwm_ops, s, 411 "exynos4210-pwm", EXYNOS4210_PWM_REG_MEM_SIZE); 412 sysbus_init_mmio(dev, &s->iomem); 413 } 414 415 static void exynos4210_pwm_class_init(ObjectClass *klass, void *data) 416 { 417 DeviceClass *dc = DEVICE_CLASS(klass); 418 419 dc->reset = exynos4210_pwm_reset; 420 dc->vmsd = &vmstate_exynos4210_pwm_state; 421 } 422 423 static const TypeInfo exynos4210_pwm_info = { 424 .name = TYPE_EXYNOS4210_PWM, 425 .parent = TYPE_SYS_BUS_DEVICE, 426 .instance_size = sizeof(Exynos4210PWMState), 427 .instance_init = exynos4210_pwm_init, 428 .class_init = exynos4210_pwm_class_init, 429 }; 430 431 static void exynos4210_pwm_register_types(void) 432 { 433 type_register_static(&exynos4210_pwm_info); 434 } 435 436 type_init(exynos4210_pwm_register_types) 437