1 /* 2 * Samsung exynos4210 Pulse Width Modulation Timer 3 * 4 * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd. 5 * All rights reserved. 6 * 7 * Evgeny Voevodin <e.voevodin@samsung.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 17 * See the GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qemu/log.h" 25 #include "hw/sysbus.h" 26 #include "qemu/timer.h" 27 #include "qemu/main-loop.h" 28 #include "qemu/module.h" 29 #include "hw/ptimer.h" 30 31 #include "hw/arm/exynos4210.h" 32 #include "hw/irq.h" 33 34 //#define DEBUG_PWM 35 36 #ifdef DEBUG_PWM 37 #define DPRINTF(fmt, ...) \ 38 do { fprintf(stdout, "PWM: [%24s:%5d] " fmt, __func__, __LINE__, \ 39 ## __VA_ARGS__); } while (0) 40 #else 41 #define DPRINTF(fmt, ...) do {} while (0) 42 #endif 43 44 #define EXYNOS4210_PWM_TIMERS_NUM 5 45 #define EXYNOS4210_PWM_REG_MEM_SIZE 0x50 46 47 #define TCFG0 0x0000 48 #define TCFG1 0x0004 49 #define TCON 0x0008 50 #define TCNTB0 0x000C 51 #define TCMPB0 0x0010 52 #define TCNTO0 0x0014 53 #define TCNTB1 0x0018 54 #define TCMPB1 0x001C 55 #define TCNTO1 0x0020 56 #define TCNTB2 0x0024 57 #define TCMPB2 0x0028 58 #define TCNTO2 0x002C 59 #define TCNTB3 0x0030 60 #define TCMPB3 0x0034 61 #define TCNTO3 0x0038 62 #define TCNTB4 0x003C 63 #define TCNTO4 0x0040 64 #define TINT_CSTAT 0x0044 65 66 #define TCNTB(x) (0xC * (x)) 67 #define TCMPB(x) (0xC * (x) + 1) 68 #define TCNTO(x) (0xC * (x) + 2) 69 70 #define GET_PRESCALER(reg, x) (((reg) & (0xFF << (8 * (x)))) >> 8 * (x)) 71 #define GET_DIVIDER(reg, x) (1 << (((reg) & (0xF << (4 * (x)))) >> (4 * (x)))) 72 73 /* 74 * Attention! Timer4 doesn't have OUTPUT_INVERTER, 75 * so Auto Reload bit is not accessible by macros! 76 */ 77 #define TCON_TIMER_BASE(x) (((x) ? 1 : 0) * 4 + 4 * (x)) 78 #define TCON_TIMER_START(x) (1 << (TCON_TIMER_BASE(x) + 0)) 79 #define TCON_TIMER_MANUAL_UPD(x) (1 << (TCON_TIMER_BASE(x) + 1)) 80 #define TCON_TIMER_OUTPUT_INV(x) (1 << (TCON_TIMER_BASE(x) + 2)) 81 #define TCON_TIMER_AUTO_RELOAD(x) (1 << (TCON_TIMER_BASE(x) + 3)) 82 #define TCON_TIMER4_AUTO_RELOAD (1 << 22) 83 84 #define TINT_CSTAT_STATUS(x) (1 << (5 + (x))) 85 #define TINT_CSTAT_ENABLE(x) (1 << (x)) 86 87 /* timer struct */ 88 typedef struct { 89 uint32_t id; /* timer id */ 90 qemu_irq irq; /* local timer irq */ 91 uint32_t freq; /* timer frequency */ 92 93 /* use ptimer.c to represent count down timer */ 94 ptimer_state *ptimer; /* timer */ 95 96 /* registers */ 97 uint32_t reg_tcntb; /* counter register buffer */ 98 uint32_t reg_tcmpb; /* compare register buffer */ 99 100 struct Exynos4210PWMState *parent; 101 102 } Exynos4210PWM; 103 104 #define TYPE_EXYNOS4210_PWM "exynos4210.pwm" 105 #define EXYNOS4210_PWM(obj) \ 106 OBJECT_CHECK(Exynos4210PWMState, (obj), TYPE_EXYNOS4210_PWM) 107 108 typedef struct Exynos4210PWMState { 109 SysBusDevice parent_obj; 110 111 MemoryRegion iomem; 112 113 uint32_t reg_tcfg[2]; 114 uint32_t reg_tcon; 115 uint32_t reg_tint_cstat; 116 117 Exynos4210PWM timer[EXYNOS4210_PWM_TIMERS_NUM]; 118 119 } Exynos4210PWMState; 120 121 /*** VMState ***/ 122 static const VMStateDescription vmstate_exynos4210_pwm = { 123 .name = "exynos4210.pwm.pwm", 124 .version_id = 1, 125 .minimum_version_id = 1, 126 .fields = (VMStateField[]) { 127 VMSTATE_UINT32(id, Exynos4210PWM), 128 VMSTATE_UINT32(freq, Exynos4210PWM), 129 VMSTATE_PTIMER(ptimer, Exynos4210PWM), 130 VMSTATE_UINT32(reg_tcntb, Exynos4210PWM), 131 VMSTATE_UINT32(reg_tcmpb, Exynos4210PWM), 132 VMSTATE_END_OF_LIST() 133 } 134 }; 135 136 static const VMStateDescription vmstate_exynos4210_pwm_state = { 137 .name = "exynos4210.pwm", 138 .version_id = 1, 139 .minimum_version_id = 1, 140 .fields = (VMStateField[]) { 141 VMSTATE_UINT32_ARRAY(reg_tcfg, Exynos4210PWMState, 2), 142 VMSTATE_UINT32(reg_tcon, Exynos4210PWMState), 143 VMSTATE_UINT32(reg_tint_cstat, Exynos4210PWMState), 144 VMSTATE_STRUCT_ARRAY(timer, Exynos4210PWMState, 145 EXYNOS4210_PWM_TIMERS_NUM, 0, 146 vmstate_exynos4210_pwm, Exynos4210PWM), 147 VMSTATE_END_OF_LIST() 148 } 149 }; 150 151 /* 152 * PWM update frequency 153 */ 154 static void exynos4210_pwm_update_freq(Exynos4210PWMState *s, uint32_t id) 155 { 156 uint32_t freq; 157 freq = s->timer[id].freq; 158 if (id > 1) { 159 s->timer[id].freq = 24000000 / 160 ((GET_PRESCALER(s->reg_tcfg[0], 1) + 1) * 161 (GET_DIVIDER(s->reg_tcfg[1], id))); 162 } else { 163 s->timer[id].freq = 24000000 / 164 ((GET_PRESCALER(s->reg_tcfg[0], 0) + 1) * 165 (GET_DIVIDER(s->reg_tcfg[1], id))); 166 } 167 168 if (freq != s->timer[id].freq) { 169 ptimer_set_freq(s->timer[id].ptimer, s->timer[id].freq); 170 DPRINTF("freq=%dHz\n", s->timer[id].freq); 171 } 172 } 173 174 /* 175 * Counter tick handler 176 */ 177 static void exynos4210_pwm_tick(void *opaque) 178 { 179 Exynos4210PWM *s = (Exynos4210PWM *)opaque; 180 Exynos4210PWMState *p = (Exynos4210PWMState *)s->parent; 181 uint32_t id = s->id; 182 bool cmp; 183 184 DPRINTF("timer %d tick\n", id); 185 186 /* set irq status */ 187 p->reg_tint_cstat |= TINT_CSTAT_STATUS(id); 188 189 /* raise IRQ */ 190 if (p->reg_tint_cstat & TINT_CSTAT_ENABLE(id)) { 191 DPRINTF("timer %d IRQ\n", id); 192 qemu_irq_raise(p->timer[id].irq); 193 } 194 195 /* reload timer */ 196 if (id != 4) { 197 cmp = p->reg_tcon & TCON_TIMER_AUTO_RELOAD(id); 198 } else { 199 cmp = p->reg_tcon & TCON_TIMER4_AUTO_RELOAD; 200 } 201 202 if (cmp) { 203 DPRINTF("auto reload timer %d count to %x\n", id, 204 p->timer[id].reg_tcntb); 205 ptimer_set_count(p->timer[id].ptimer, p->timer[id].reg_tcntb); 206 ptimer_run(p->timer[id].ptimer, 1); 207 } else { 208 /* stop timer, set status to STOP, see Basic Timer Operation */ 209 p->reg_tcon &= ~TCON_TIMER_START(id); 210 ptimer_stop(p->timer[id].ptimer); 211 } 212 } 213 214 /* 215 * PWM Read 216 */ 217 static uint64_t exynos4210_pwm_read(void *opaque, hwaddr offset, 218 unsigned size) 219 { 220 Exynos4210PWMState *s = (Exynos4210PWMState *)opaque; 221 uint32_t value = 0; 222 int index; 223 224 switch (offset) { 225 case TCFG0: case TCFG1: 226 index = (offset - TCFG0) >> 2; 227 value = s->reg_tcfg[index]; 228 break; 229 230 case TCON: 231 value = s->reg_tcon; 232 break; 233 234 case TCNTB0: case TCNTB1: 235 case TCNTB2: case TCNTB3: case TCNTB4: 236 index = (offset - TCNTB0) / 0xC; 237 value = s->timer[index].reg_tcntb; 238 break; 239 240 case TCMPB0: case TCMPB1: 241 case TCMPB2: case TCMPB3: 242 index = (offset - TCMPB0) / 0xC; 243 value = s->timer[index].reg_tcmpb; 244 break; 245 246 case TCNTO0: case TCNTO1: 247 case TCNTO2: case TCNTO3: case TCNTO4: 248 index = (offset == TCNTO4) ? 4 : (offset - TCNTO0) / 0xC; 249 value = ptimer_get_count(s->timer[index].ptimer); 250 break; 251 252 case TINT_CSTAT: 253 value = s->reg_tint_cstat; 254 break; 255 256 default: 257 qemu_log_mask(LOG_GUEST_ERROR, 258 "exynos4210.pwm: bad read offset " TARGET_FMT_plx, 259 offset); 260 break; 261 } 262 return value; 263 } 264 265 /* 266 * PWM Write 267 */ 268 static void exynos4210_pwm_write(void *opaque, hwaddr offset, 269 uint64_t value, unsigned size) 270 { 271 Exynos4210PWMState *s = (Exynos4210PWMState *)opaque; 272 int index; 273 uint32_t new_val; 274 int i; 275 276 switch (offset) { 277 case TCFG0: case TCFG1: 278 index = (offset - TCFG0) >> 2; 279 s->reg_tcfg[index] = value; 280 281 /* update timers frequencies */ 282 for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) { 283 exynos4210_pwm_update_freq(s, s->timer[i].id); 284 } 285 break; 286 287 case TCON: 288 for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) { 289 if ((value & TCON_TIMER_MANUAL_UPD(i)) > 290 (s->reg_tcon & TCON_TIMER_MANUAL_UPD(i))) { 291 /* 292 * TCNTB and TCMPB are loaded into TCNT and TCMP. 293 * Update timers. 294 */ 295 296 /* this will start timer to run, this ok, because 297 * during processing start bit timer will be stopped 298 * if needed */ 299 ptimer_set_count(s->timer[i].ptimer, s->timer[i].reg_tcntb); 300 DPRINTF("set timer %d count to %x\n", i, 301 s->timer[i].reg_tcntb); 302 } 303 304 if ((value & TCON_TIMER_START(i)) > 305 (s->reg_tcon & TCON_TIMER_START(i))) { 306 /* changed to start */ 307 ptimer_run(s->timer[i].ptimer, 1); 308 DPRINTF("run timer %d\n", i); 309 } 310 311 if ((value & TCON_TIMER_START(i)) < 312 (s->reg_tcon & TCON_TIMER_START(i))) { 313 /* changed to stop */ 314 ptimer_stop(s->timer[i].ptimer); 315 DPRINTF("stop timer %d\n", i); 316 } 317 } 318 s->reg_tcon = value; 319 break; 320 321 case TCNTB0: case TCNTB1: 322 case TCNTB2: case TCNTB3: case TCNTB4: 323 index = (offset - TCNTB0) / 0xC; 324 s->timer[index].reg_tcntb = value; 325 break; 326 327 case TCMPB0: case TCMPB1: 328 case TCMPB2: case TCMPB3: 329 index = (offset - TCMPB0) / 0xC; 330 s->timer[index].reg_tcmpb = value; 331 break; 332 333 case TINT_CSTAT: 334 new_val = (s->reg_tint_cstat & 0x3E0) + (0x1F & value); 335 new_val &= ~(0x3E0 & value); 336 337 for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) { 338 if ((new_val & TINT_CSTAT_STATUS(i)) < 339 (s->reg_tint_cstat & TINT_CSTAT_STATUS(i))) { 340 qemu_irq_lower(s->timer[i].irq); 341 } 342 } 343 344 s->reg_tint_cstat = new_val; 345 break; 346 347 default: 348 qemu_log_mask(LOG_GUEST_ERROR, 349 "exynos4210.pwm: bad write offset " TARGET_FMT_plx, 350 offset); 351 break; 352 353 } 354 } 355 356 /* 357 * Set default values to timer fields and registers 358 */ 359 static void exynos4210_pwm_reset(DeviceState *d) 360 { 361 Exynos4210PWMState *s = EXYNOS4210_PWM(d); 362 int i; 363 s->reg_tcfg[0] = 0x0101; 364 s->reg_tcfg[1] = 0x0; 365 s->reg_tcon = 0; 366 s->reg_tint_cstat = 0; 367 for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) { 368 s->timer[i].reg_tcmpb = 0; 369 s->timer[i].reg_tcntb = 0; 370 371 exynos4210_pwm_update_freq(s, s->timer[i].id); 372 ptimer_stop(s->timer[i].ptimer); 373 } 374 } 375 376 static const MemoryRegionOps exynos4210_pwm_ops = { 377 .read = exynos4210_pwm_read, 378 .write = exynos4210_pwm_write, 379 .endianness = DEVICE_NATIVE_ENDIAN, 380 }; 381 382 /* 383 * PWM timer initialization 384 */ 385 static void exynos4210_pwm_init(Object *obj) 386 { 387 Exynos4210PWMState *s = EXYNOS4210_PWM(obj); 388 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 389 int i; 390 QEMUBH *bh; 391 392 for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) { 393 bh = qemu_bh_new(exynos4210_pwm_tick, &s->timer[i]); 394 sysbus_init_irq(dev, &s->timer[i].irq); 395 s->timer[i].ptimer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); 396 s->timer[i].id = i; 397 s->timer[i].parent = s; 398 } 399 400 memory_region_init_io(&s->iomem, obj, &exynos4210_pwm_ops, s, 401 "exynos4210-pwm", EXYNOS4210_PWM_REG_MEM_SIZE); 402 sysbus_init_mmio(dev, &s->iomem); 403 } 404 405 static void exynos4210_pwm_class_init(ObjectClass *klass, void *data) 406 { 407 DeviceClass *dc = DEVICE_CLASS(klass); 408 409 dc->reset = exynos4210_pwm_reset; 410 dc->vmsd = &vmstate_exynos4210_pwm_state; 411 } 412 413 static const TypeInfo exynos4210_pwm_info = { 414 .name = TYPE_EXYNOS4210_PWM, 415 .parent = TYPE_SYS_BUS_DEVICE, 416 .instance_size = sizeof(Exynos4210PWMState), 417 .instance_init = exynos4210_pwm_init, 418 .class_init = exynos4210_pwm_class_init, 419 }; 420 421 static void exynos4210_pwm_register_types(void) 422 { 423 type_register_static(&exynos4210_pwm_info); 424 } 425 426 type_init(exynos4210_pwm_register_types) 427