1 /* 2 * Samsung exynos4210 Multi Core timer 3 * 4 * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd. 5 * All rights reserved. 6 * 7 * Evgeny Voevodin <e.voevodin@samsung.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 17 * See the GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 /* 24 * Global Timer: 25 * 26 * Consists of two timers. First represents Free Running Counter and second 27 * is used to measure interval from FRC to nearest comparator. 28 * 29 * 0 UINT64_MAX 30 * | timer0 | 31 * | <-------------------------------------------------------------- | 32 * | --------------------------------------------frc---------------> | 33 * |______________________________________________|__________________| 34 * CMP0 CMP1 CMP2 | CMP3 35 * __| |_ 36 * | timer1 | 37 * | -------------> | 38 * frc CMPx 39 * 40 * Problem: when implementing global timer as is, overflow arises. 41 * next_time = cur_time + period * count; 42 * period and count are 64 bits width. 43 * Lets arm timer for MCT_GT_COUNTER_STEP count and update internal G_CNT 44 * register during each event. 45 * 46 * Problem: both timers need to be implemented using MCT_XT_COUNTER_STEP because 47 * local timer contains two counters: TCNT and ICNT. TCNT == 0 -> ICNT--. 48 * IRQ is generated when ICNT riches zero. Implementation where TCNT == 0 49 * generates IRQs suffers from too frequently events. Better to have one 50 * uint64_t counter equal to TCNT*ICNT and arm ptimer.c for a minimum(TCNT*ICNT, 51 * MCT_GT_COUNTER_STEP); (yes, if target tunes ICNT * TCNT to be too low values, 52 * there is no way to avoid frequently events). 53 */ 54 55 #include "qemu/osdep.h" 56 #include "qemu/log.h" 57 #include "hw/hw.h" 58 #include "hw/sysbus.h" 59 #include "migration/vmstate.h" 60 #include "qemu/timer.h" 61 #include "qemu/main-loop.h" 62 #include "qemu/module.h" 63 #include "hw/ptimer.h" 64 65 #include "hw/arm/exynos4210.h" 66 #include "hw/hw.h" 67 #include "hw/irq.h" 68 69 //#define DEBUG_MCT 70 71 #ifdef DEBUG_MCT 72 #define DPRINTF(fmt, ...) \ 73 do { fprintf(stdout, "MCT: [%24s:%5d] " fmt, __func__, __LINE__, \ 74 ## __VA_ARGS__); } while (0) 75 #else 76 #define DPRINTF(fmt, ...) do {} while (0) 77 #endif 78 79 #define MCT_CFG 0x000 80 #define G_CNT_L 0x100 81 #define G_CNT_U 0x104 82 #define G_CNT_WSTAT 0x110 83 #define G_COMP0_L 0x200 84 #define G_COMP0_U 0x204 85 #define G_COMP0_ADD_INCR 0x208 86 #define G_COMP1_L 0x210 87 #define G_COMP1_U 0x214 88 #define G_COMP1_ADD_INCR 0x218 89 #define G_COMP2_L 0x220 90 #define G_COMP2_U 0x224 91 #define G_COMP2_ADD_INCR 0x228 92 #define G_COMP3_L 0x230 93 #define G_COMP3_U 0x234 94 #define G_COMP3_ADD_INCR 0x238 95 #define G_TCON 0x240 96 #define G_INT_CSTAT 0x244 97 #define G_INT_ENB 0x248 98 #define G_WSTAT 0x24C 99 #define L0_TCNTB 0x300 100 #define L0_TCNTO 0x304 101 #define L0_ICNTB 0x308 102 #define L0_ICNTO 0x30C 103 #define L0_FRCNTB 0x310 104 #define L0_FRCNTO 0x314 105 #define L0_TCON 0x320 106 #define L0_INT_CSTAT 0x330 107 #define L0_INT_ENB 0x334 108 #define L0_WSTAT 0x340 109 #define L1_TCNTB 0x400 110 #define L1_TCNTO 0x404 111 #define L1_ICNTB 0x408 112 #define L1_ICNTO 0x40C 113 #define L1_FRCNTB 0x410 114 #define L1_FRCNTO 0x414 115 #define L1_TCON 0x420 116 #define L1_INT_CSTAT 0x430 117 #define L1_INT_ENB 0x434 118 #define L1_WSTAT 0x440 119 120 #define MCT_CFG_GET_PRESCALER(x) ((x) & 0xFF) 121 #define MCT_CFG_GET_DIVIDER(x) (1 << ((x) >> 8 & 7)) 122 123 #define GET_G_COMP_IDX(offset) (((offset) - G_COMP0_L) / 0x10) 124 #define GET_G_COMP_ADD_INCR_IDX(offset) (((offset) - G_COMP0_ADD_INCR) / 0x10) 125 126 #define G_COMP_L(x) (G_COMP0_L + (x) * 0x10) 127 #define G_COMP_U(x) (G_COMP0_U + (x) * 0x10) 128 129 #define G_COMP_ADD_INCR(x) (G_COMP0_ADD_INCR + (x) * 0x10) 130 131 /* MCT bits */ 132 #define G_TCON_COMP_ENABLE(x) (1 << 2 * (x)) 133 #define G_TCON_AUTO_ICREMENT(x) (1 << (2 * (x) + 1)) 134 #define G_TCON_TIMER_ENABLE (1 << 8) 135 136 #define G_INT_ENABLE(x) (1 << (x)) 137 #define G_INT_CSTAT_COMP(x) (1 << (x)) 138 139 #define G_CNT_WSTAT_L 1 140 #define G_CNT_WSTAT_U 2 141 142 #define G_WSTAT_COMP_L(x) (1 << 4 * (x)) 143 #define G_WSTAT_COMP_U(x) (1 << ((4 * (x)) + 1)) 144 #define G_WSTAT_COMP_ADDINCR(x) (1 << ((4 * (x)) + 2)) 145 #define G_WSTAT_TCON_WRITE (1 << 16) 146 147 #define GET_L_TIMER_IDX(offset) ((((offset) & 0xF00) - L0_TCNTB) / 0x100) 148 #define GET_L_TIMER_CNT_REG_IDX(offset, lt_i) \ 149 (((offset) - (L0_TCNTB + 0x100 * (lt_i))) >> 2) 150 151 #define L_ICNTB_MANUAL_UPDATE (1 << 31) 152 153 #define L_TCON_TICK_START (1) 154 #define L_TCON_INT_START (1 << 1) 155 #define L_TCON_INTERVAL_MODE (1 << 2) 156 #define L_TCON_FRC_START (1 << 3) 157 158 #define L_INT_CSTAT_INTCNT (1 << 0) 159 #define L_INT_CSTAT_FRCCNT (1 << 1) 160 161 #define L_INT_INTENB_ICNTEIE (1 << 0) 162 #define L_INT_INTENB_FRCEIE (1 << 1) 163 164 #define L_WSTAT_TCNTB_WRITE (1 << 0) 165 #define L_WSTAT_ICNTB_WRITE (1 << 1) 166 #define L_WSTAT_FRCCNTB_WRITE (1 << 2) 167 #define L_WSTAT_TCON_WRITE (1 << 3) 168 169 enum LocalTimerRegCntIndexes { 170 L_REG_CNT_TCNTB, 171 L_REG_CNT_TCNTO, 172 L_REG_CNT_ICNTB, 173 L_REG_CNT_ICNTO, 174 L_REG_CNT_FRCCNTB, 175 L_REG_CNT_FRCCNTO, 176 177 L_REG_CNT_AMOUNT 178 }; 179 180 #define MCT_SFR_SIZE 0x444 181 182 #define MCT_GT_CMP_NUM 4 183 184 #define MCT_GT_COUNTER_STEP 0x100000000ULL 185 #define MCT_LT_COUNTER_STEP 0x100000000ULL 186 #define MCT_LT_CNT_LOW_LIMIT 0x100 187 188 /* global timer */ 189 typedef struct { 190 qemu_irq irq[MCT_GT_CMP_NUM]; 191 192 struct gregs { 193 uint64_t cnt; 194 uint32_t cnt_wstat; 195 uint32_t tcon; 196 uint32_t int_cstat; 197 uint32_t int_enb; 198 uint32_t wstat; 199 uint64_t comp[MCT_GT_CMP_NUM]; 200 uint32_t comp_add_incr[MCT_GT_CMP_NUM]; 201 } reg; 202 203 uint64_t count; /* Value FRC was armed with */ 204 int32_t curr_comp; /* Current comparator FRC is running to */ 205 206 ptimer_state *ptimer_frc; /* FRC timer */ 207 208 } Exynos4210MCTGT; 209 210 /* local timer */ 211 typedef struct { 212 int id; /* timer id */ 213 qemu_irq irq; /* local timer irq */ 214 215 struct tick_timer { 216 uint32_t cnt_run; /* cnt timer is running */ 217 uint32_t int_run; /* int timer is running */ 218 219 uint32_t last_icnto; 220 uint32_t last_tcnto; 221 uint32_t tcntb; /* initial value for TCNTB */ 222 uint32_t icntb; /* initial value for ICNTB */ 223 224 /* for step mode */ 225 uint64_t distance; /* distance to count to the next event */ 226 uint64_t progress; /* progress when counting by steps */ 227 uint64_t count; /* count to arm timer with */ 228 229 ptimer_state *ptimer_tick; /* timer for tick counter */ 230 } tick_timer; 231 232 /* use ptimer.c to represent count down timer */ 233 234 ptimer_state *ptimer_frc; /* timer for free running counter */ 235 236 /* registers */ 237 struct lregs { 238 uint32_t cnt[L_REG_CNT_AMOUNT]; 239 uint32_t tcon; 240 uint32_t int_cstat; 241 uint32_t int_enb; 242 uint32_t wstat; 243 } reg; 244 245 } Exynos4210MCTLT; 246 247 #define TYPE_EXYNOS4210_MCT "exynos4210.mct" 248 #define EXYNOS4210_MCT(obj) \ 249 OBJECT_CHECK(Exynos4210MCTState, (obj), TYPE_EXYNOS4210_MCT) 250 251 typedef struct Exynos4210MCTState { 252 SysBusDevice parent_obj; 253 254 MemoryRegion iomem; 255 256 /* Registers */ 257 uint32_t reg_mct_cfg; 258 259 Exynos4210MCTLT l_timer[2]; 260 Exynos4210MCTGT g_timer; 261 262 uint32_t freq; /* all timers tick frequency, TCLK */ 263 } Exynos4210MCTState; 264 265 /*** VMState ***/ 266 static const VMStateDescription vmstate_tick_timer = { 267 .name = "exynos4210.mct.tick_timer", 268 .version_id = 1, 269 .minimum_version_id = 1, 270 .fields = (VMStateField[]) { 271 VMSTATE_UINT32(cnt_run, struct tick_timer), 272 VMSTATE_UINT32(int_run, struct tick_timer), 273 VMSTATE_UINT32(last_icnto, struct tick_timer), 274 VMSTATE_UINT32(last_tcnto, struct tick_timer), 275 VMSTATE_UINT32(tcntb, struct tick_timer), 276 VMSTATE_UINT32(icntb, struct tick_timer), 277 VMSTATE_UINT64(distance, struct tick_timer), 278 VMSTATE_UINT64(progress, struct tick_timer), 279 VMSTATE_UINT64(count, struct tick_timer), 280 VMSTATE_PTIMER(ptimer_tick, struct tick_timer), 281 VMSTATE_END_OF_LIST() 282 } 283 }; 284 285 static const VMStateDescription vmstate_lregs = { 286 .name = "exynos4210.mct.lregs", 287 .version_id = 1, 288 .minimum_version_id = 1, 289 .fields = (VMStateField[]) { 290 VMSTATE_UINT32_ARRAY(cnt, struct lregs, L_REG_CNT_AMOUNT), 291 VMSTATE_UINT32(tcon, struct lregs), 292 VMSTATE_UINT32(int_cstat, struct lregs), 293 VMSTATE_UINT32(int_enb, struct lregs), 294 VMSTATE_UINT32(wstat, struct lregs), 295 VMSTATE_END_OF_LIST() 296 } 297 }; 298 299 static const VMStateDescription vmstate_exynos4210_mct_lt = { 300 .name = "exynos4210.mct.lt", 301 .version_id = 1, 302 .minimum_version_id = 1, 303 .fields = (VMStateField[]) { 304 VMSTATE_INT32(id, Exynos4210MCTLT), 305 VMSTATE_STRUCT(tick_timer, Exynos4210MCTLT, 0, 306 vmstate_tick_timer, 307 struct tick_timer), 308 VMSTATE_PTIMER(ptimer_frc, Exynos4210MCTLT), 309 VMSTATE_STRUCT(reg, Exynos4210MCTLT, 0, 310 vmstate_lregs, 311 struct lregs), 312 VMSTATE_END_OF_LIST() 313 } 314 }; 315 316 static const VMStateDescription vmstate_gregs = { 317 .name = "exynos4210.mct.lregs", 318 .version_id = 1, 319 .minimum_version_id = 1, 320 .fields = (VMStateField[]) { 321 VMSTATE_UINT64(cnt, struct gregs), 322 VMSTATE_UINT32(cnt_wstat, struct gregs), 323 VMSTATE_UINT32(tcon, struct gregs), 324 VMSTATE_UINT32(int_cstat, struct gregs), 325 VMSTATE_UINT32(int_enb, struct gregs), 326 VMSTATE_UINT32(wstat, struct gregs), 327 VMSTATE_UINT64_ARRAY(comp, struct gregs, MCT_GT_CMP_NUM), 328 VMSTATE_UINT32_ARRAY(comp_add_incr, struct gregs, 329 MCT_GT_CMP_NUM), 330 VMSTATE_END_OF_LIST() 331 } 332 }; 333 334 static const VMStateDescription vmstate_exynos4210_mct_gt = { 335 .name = "exynos4210.mct.lt", 336 .version_id = 1, 337 .minimum_version_id = 1, 338 .fields = (VMStateField[]) { 339 VMSTATE_STRUCT(reg, Exynos4210MCTGT, 0, vmstate_gregs, 340 struct gregs), 341 VMSTATE_UINT64(count, Exynos4210MCTGT), 342 VMSTATE_INT32(curr_comp, Exynos4210MCTGT), 343 VMSTATE_PTIMER(ptimer_frc, Exynos4210MCTGT), 344 VMSTATE_END_OF_LIST() 345 } 346 }; 347 348 static const VMStateDescription vmstate_exynos4210_mct_state = { 349 .name = "exynos4210.mct", 350 .version_id = 1, 351 .minimum_version_id = 1, 352 .fields = (VMStateField[]) { 353 VMSTATE_UINT32(reg_mct_cfg, Exynos4210MCTState), 354 VMSTATE_STRUCT_ARRAY(l_timer, Exynos4210MCTState, 2, 0, 355 vmstate_exynos4210_mct_lt, Exynos4210MCTLT), 356 VMSTATE_STRUCT(g_timer, Exynos4210MCTState, 0, 357 vmstate_exynos4210_mct_gt, Exynos4210MCTGT), 358 VMSTATE_UINT32(freq, Exynos4210MCTState), 359 VMSTATE_END_OF_LIST() 360 } 361 }; 362 363 static void exynos4210_mct_update_freq(Exynos4210MCTState *s); 364 365 /* 366 * Set counter of FRC global timer. 367 * Must be called within exynos4210_gfrc_tx_begin/commit block. 368 */ 369 static void exynos4210_gfrc_set_count(Exynos4210MCTGT *s, uint64_t count) 370 { 371 s->count = count; 372 DPRINTF("global timer frc set count 0x%llx\n", count); 373 ptimer_set_count(s->ptimer_frc, count); 374 } 375 376 /* 377 * Get counter of FRC global timer. 378 */ 379 static uint64_t exynos4210_gfrc_get_count(Exynos4210MCTGT *s) 380 { 381 uint64_t count = 0; 382 count = ptimer_get_count(s->ptimer_frc); 383 count = s->count - count; 384 return s->reg.cnt + count; 385 } 386 387 /* 388 * Stop global FRC timer 389 * Must be called within exynos4210_gfrc_tx_begin/commit block. 390 */ 391 static void exynos4210_gfrc_stop(Exynos4210MCTGT *s) 392 { 393 DPRINTF("global timer frc stop\n"); 394 395 ptimer_stop(s->ptimer_frc); 396 } 397 398 /* 399 * Start global FRC timer 400 * Must be called within exynos4210_gfrc_tx_begin/commit block. 401 */ 402 static void exynos4210_gfrc_start(Exynos4210MCTGT *s) 403 { 404 DPRINTF("global timer frc start\n"); 405 406 ptimer_run(s->ptimer_frc, 1); 407 } 408 409 /* 410 * Start ptimer transaction for global FRC timer; this is just for 411 * consistency with the way we wrap operations like stop and run. 412 */ 413 static void exynos4210_gfrc_tx_begin(Exynos4210MCTGT *s) 414 { 415 ptimer_transaction_begin(s->ptimer_frc); 416 } 417 418 /* Commit ptimer transaction for global FRC timer. */ 419 static void exynos4210_gfrc_tx_commit(Exynos4210MCTGT *s) 420 { 421 ptimer_transaction_commit(s->ptimer_frc); 422 } 423 424 /* 425 * Find next nearest Comparator. If current Comparator value equals to other 426 * Comparator value, skip them both 427 */ 428 static int32_t exynos4210_gcomp_find(Exynos4210MCTState *s) 429 { 430 int res; 431 int i; 432 int enabled; 433 uint64_t min; 434 int min_comp_i; 435 uint64_t gfrc; 436 uint64_t distance; 437 uint64_t distance_min; 438 int comp_i; 439 440 /* get gfrc count */ 441 gfrc = exynos4210_gfrc_get_count(&s->g_timer); 442 443 min = UINT64_MAX; 444 distance_min = UINT64_MAX; 445 comp_i = MCT_GT_CMP_NUM; 446 min_comp_i = MCT_GT_CMP_NUM; 447 enabled = 0; 448 449 /* lookup for nearest comparator */ 450 for (i = 0; i < MCT_GT_CMP_NUM; i++) { 451 452 if (s->g_timer.reg.tcon & G_TCON_COMP_ENABLE(i)) { 453 454 enabled = 1; 455 456 if (s->g_timer.reg.comp[i] > gfrc) { 457 /* Comparator is upper then FRC */ 458 distance = s->g_timer.reg.comp[i] - gfrc; 459 460 if (distance <= distance_min) { 461 distance_min = distance; 462 comp_i = i; 463 } 464 } else { 465 /* Comparator is below FRC, find the smallest */ 466 467 if (s->g_timer.reg.comp[i] <= min) { 468 min = s->g_timer.reg.comp[i]; 469 min_comp_i = i; 470 } 471 } 472 } 473 } 474 475 if (!enabled) { 476 /* All Comparators disabled */ 477 res = -1; 478 } else if (comp_i < MCT_GT_CMP_NUM) { 479 /* Found upper Comparator */ 480 res = comp_i; 481 } else { 482 /* All Comparators are below or equal to FRC */ 483 res = min_comp_i; 484 } 485 486 DPRINTF("found comparator %d: comp 0x%llx distance 0x%llx, gfrc 0x%llx\n", 487 res, 488 s->g_timer.reg.comp[res], 489 distance_min, 490 gfrc); 491 492 return res; 493 } 494 495 /* 496 * Get distance to nearest Comparator 497 */ 498 static uint64_t exynos4210_gcomp_get_distance(Exynos4210MCTState *s, int32_t id) 499 { 500 if (id == -1) { 501 /* no enabled Comparators, choose max distance */ 502 return MCT_GT_COUNTER_STEP; 503 } 504 if (s->g_timer.reg.comp[id] - s->g_timer.reg.cnt < MCT_GT_COUNTER_STEP) { 505 return s->g_timer.reg.comp[id] - s->g_timer.reg.cnt; 506 } else { 507 return MCT_GT_COUNTER_STEP; 508 } 509 } 510 511 /* 512 * Restart global FRC timer 513 * Must be called within exynos4210_gfrc_tx_begin/commit block. 514 */ 515 static void exynos4210_gfrc_restart(Exynos4210MCTState *s) 516 { 517 uint64_t distance; 518 519 exynos4210_gfrc_stop(&s->g_timer); 520 521 s->g_timer.curr_comp = exynos4210_gcomp_find(s); 522 523 distance = exynos4210_gcomp_get_distance(s, s->g_timer.curr_comp); 524 525 if (distance > MCT_GT_COUNTER_STEP || !distance) { 526 distance = MCT_GT_COUNTER_STEP; 527 } 528 529 exynos4210_gfrc_set_count(&s->g_timer, distance); 530 exynos4210_gfrc_start(&s->g_timer); 531 } 532 533 /* 534 * Raise global timer CMP IRQ 535 */ 536 static void exynos4210_gcomp_raise_irq(void *opaque, uint32_t id) 537 { 538 Exynos4210MCTGT *s = opaque; 539 540 /* If CSTAT is pending and IRQ is enabled */ 541 if ((s->reg.int_cstat & G_INT_CSTAT_COMP(id)) && 542 (s->reg.int_enb & G_INT_ENABLE(id))) { 543 DPRINTF("gcmp timer[%d] IRQ\n", id); 544 qemu_irq_raise(s->irq[id]); 545 } 546 } 547 548 /* 549 * Lower global timer CMP IRQ 550 */ 551 static void exynos4210_gcomp_lower_irq(void *opaque, uint32_t id) 552 { 553 Exynos4210MCTGT *s = opaque; 554 qemu_irq_lower(s->irq[id]); 555 } 556 557 /* 558 * Global timer FRC event handler. 559 * Each event occurs when internal counter reaches counter + MCT_GT_COUNTER_STEP 560 * Every time we arm global FRC timer to count for MCT_GT_COUNTER_STEP value 561 */ 562 static void exynos4210_gfrc_event(void *opaque) 563 { 564 Exynos4210MCTState *s = (Exynos4210MCTState *)opaque; 565 int i; 566 uint64_t distance; 567 568 DPRINTF("\n"); 569 570 s->g_timer.reg.cnt += s->g_timer.count; 571 572 /* Process all comparators */ 573 for (i = 0; i < MCT_GT_CMP_NUM; i++) { 574 575 if (s->g_timer.reg.cnt == s->g_timer.reg.comp[i]) { 576 /* reached nearest comparator */ 577 578 s->g_timer.reg.int_cstat |= G_INT_CSTAT_COMP(i); 579 580 /* Auto increment */ 581 if (s->g_timer.reg.tcon & G_TCON_AUTO_ICREMENT(i)) { 582 s->g_timer.reg.comp[i] += s->g_timer.reg.comp_add_incr[i]; 583 } 584 585 /* IRQ */ 586 exynos4210_gcomp_raise_irq(&s->g_timer, i); 587 } 588 } 589 590 /* Reload FRC to reach nearest comparator */ 591 s->g_timer.curr_comp = exynos4210_gcomp_find(s); 592 distance = exynos4210_gcomp_get_distance(s, s->g_timer.curr_comp); 593 if (distance > MCT_GT_COUNTER_STEP || !distance) { 594 distance = MCT_GT_COUNTER_STEP; 595 } 596 exynos4210_gfrc_set_count(&s->g_timer, distance); 597 598 exynos4210_gfrc_start(&s->g_timer); 599 } 600 601 /* 602 * Get counter of FRC local timer. 603 */ 604 static uint64_t exynos4210_lfrc_get_count(Exynos4210MCTLT *s) 605 { 606 return ptimer_get_count(s->ptimer_frc); 607 } 608 609 /* 610 * Set counter of FRC local timer. 611 */ 612 static void exynos4210_lfrc_update_count(Exynos4210MCTLT *s) 613 { 614 if (!s->reg.cnt[L_REG_CNT_FRCCNTB]) { 615 ptimer_set_count(s->ptimer_frc, MCT_LT_COUNTER_STEP); 616 } else { 617 ptimer_set_count(s->ptimer_frc, s->reg.cnt[L_REG_CNT_FRCCNTB]); 618 } 619 } 620 621 /* 622 * Start local FRC timer 623 */ 624 static void exynos4210_lfrc_start(Exynos4210MCTLT *s) 625 { 626 ptimer_run(s->ptimer_frc, 1); 627 } 628 629 /* 630 * Stop local FRC timer 631 */ 632 static void exynos4210_lfrc_stop(Exynos4210MCTLT *s) 633 { 634 ptimer_stop(s->ptimer_frc); 635 } 636 637 /* 638 * Local timer free running counter tick handler 639 */ 640 static void exynos4210_lfrc_event(void *opaque) 641 { 642 Exynos4210MCTLT * s = (Exynos4210MCTLT *)opaque; 643 644 /* local frc expired */ 645 646 DPRINTF("\n"); 647 648 s->reg.int_cstat |= L_INT_CSTAT_FRCCNT; 649 650 /* update frc counter */ 651 exynos4210_lfrc_update_count(s); 652 653 /* raise irq */ 654 if (s->reg.int_enb & L_INT_INTENB_FRCEIE) { 655 qemu_irq_raise(s->irq); 656 } 657 658 /* we reached here, this means that timer is enabled */ 659 exynos4210_lfrc_start(s); 660 } 661 662 static uint32_t exynos4210_ltick_int_get_cnto(struct tick_timer *s); 663 static uint32_t exynos4210_ltick_cnt_get_cnto(struct tick_timer *s); 664 static void exynos4210_ltick_recalc_count(struct tick_timer *s); 665 666 /* 667 * Action on enabling local tick int timer 668 */ 669 static void exynos4210_ltick_int_start(struct tick_timer *s) 670 { 671 if (!s->int_run) { 672 s->int_run = 1; 673 } 674 } 675 676 /* 677 * Action on disabling local tick int timer 678 */ 679 static void exynos4210_ltick_int_stop(struct tick_timer *s) 680 { 681 if (s->int_run) { 682 s->last_icnto = exynos4210_ltick_int_get_cnto(s); 683 s->int_run = 0; 684 } 685 } 686 687 /* 688 * Get count for INT timer 689 */ 690 static uint32_t exynos4210_ltick_int_get_cnto(struct tick_timer *s) 691 { 692 uint32_t icnto; 693 uint64_t remain; 694 uint64_t count; 695 uint64_t counted; 696 uint64_t cur_progress; 697 698 count = ptimer_get_count(s->ptimer_tick); 699 if (count) { 700 /* timer is still counting, called not from event */ 701 counted = s->count - ptimer_get_count(s->ptimer_tick); 702 cur_progress = s->progress + counted; 703 } else { 704 /* timer expired earlier */ 705 cur_progress = s->progress; 706 } 707 708 remain = s->distance - cur_progress; 709 710 if (!s->int_run) { 711 /* INT is stopped. */ 712 icnto = s->last_icnto; 713 } else { 714 /* Both are counting */ 715 icnto = remain / s->tcntb; 716 } 717 718 return icnto; 719 } 720 721 /* 722 * Start local tick cnt timer. 723 */ 724 static void exynos4210_ltick_cnt_start(struct tick_timer *s) 725 { 726 if (!s->cnt_run) { 727 728 exynos4210_ltick_recalc_count(s); 729 ptimer_set_count(s->ptimer_tick, s->count); 730 ptimer_run(s->ptimer_tick, 1); 731 732 s->cnt_run = 1; 733 } 734 } 735 736 /* 737 * Stop local tick cnt timer. 738 */ 739 static void exynos4210_ltick_cnt_stop(struct tick_timer *s) 740 { 741 if (s->cnt_run) { 742 743 s->last_tcnto = exynos4210_ltick_cnt_get_cnto(s); 744 745 if (s->int_run) { 746 exynos4210_ltick_int_stop(s); 747 } 748 749 ptimer_stop(s->ptimer_tick); 750 751 s->cnt_run = 0; 752 } 753 } 754 755 /* 756 * Get counter for CNT timer 757 */ 758 static uint32_t exynos4210_ltick_cnt_get_cnto(struct tick_timer *s) 759 { 760 uint32_t tcnto; 761 uint32_t icnto; 762 uint64_t remain; 763 uint64_t counted; 764 uint64_t count; 765 uint64_t cur_progress; 766 767 count = ptimer_get_count(s->ptimer_tick); 768 if (count) { 769 /* timer is still counting, called not from event */ 770 counted = s->count - ptimer_get_count(s->ptimer_tick); 771 cur_progress = s->progress + counted; 772 } else { 773 /* timer expired earlier */ 774 cur_progress = s->progress; 775 } 776 777 remain = s->distance - cur_progress; 778 779 if (!s->cnt_run) { 780 /* Both are stopped. */ 781 tcnto = s->last_tcnto; 782 } else if (!s->int_run) { 783 /* INT counter is stopped, progress is by CNT timer */ 784 tcnto = remain % s->tcntb; 785 } else { 786 /* Both are counting */ 787 icnto = remain / s->tcntb; 788 if (icnto) { 789 tcnto = remain % (icnto * s->tcntb); 790 } else { 791 tcnto = remain % s->tcntb; 792 } 793 } 794 795 return tcnto; 796 } 797 798 /* 799 * Set new values of counters for CNT and INT timers 800 */ 801 static void exynos4210_ltick_set_cntb(struct tick_timer *s, uint32_t new_cnt, 802 uint32_t new_int) 803 { 804 uint32_t cnt_stopped = 0; 805 uint32_t int_stopped = 0; 806 807 if (s->cnt_run) { 808 exynos4210_ltick_cnt_stop(s); 809 cnt_stopped = 1; 810 } 811 812 if (s->int_run) { 813 exynos4210_ltick_int_stop(s); 814 int_stopped = 1; 815 } 816 817 s->tcntb = new_cnt + 1; 818 s->icntb = new_int + 1; 819 820 if (cnt_stopped) { 821 exynos4210_ltick_cnt_start(s); 822 } 823 if (int_stopped) { 824 exynos4210_ltick_int_start(s); 825 } 826 827 } 828 829 /* 830 * Calculate new counter value for tick timer 831 */ 832 static void exynos4210_ltick_recalc_count(struct tick_timer *s) 833 { 834 uint64_t to_count; 835 836 if ((s->cnt_run && s->last_tcnto) || (s->int_run && s->last_icnto)) { 837 /* 838 * one or both timers run and not counted to the end; 839 * distance is not passed, recalculate with last_tcnto * last_icnto 840 */ 841 842 if (s->last_tcnto) { 843 to_count = (uint64_t)s->last_tcnto * s->last_icnto; 844 } else { 845 to_count = s->last_icnto; 846 } 847 } else { 848 /* distance is passed, recalculate with tcnto * icnto */ 849 if (s->icntb) { 850 s->distance = (uint64_t)s->tcntb * s->icntb; 851 } else { 852 s->distance = s->tcntb; 853 } 854 855 to_count = s->distance; 856 s->progress = 0; 857 } 858 859 if (to_count > MCT_LT_COUNTER_STEP) { 860 /* count by step */ 861 s->count = MCT_LT_COUNTER_STEP; 862 } else { 863 s->count = to_count; 864 } 865 } 866 867 /* 868 * Initialize tick_timer 869 */ 870 static void exynos4210_ltick_timer_init(struct tick_timer *s) 871 { 872 exynos4210_ltick_int_stop(s); 873 exynos4210_ltick_cnt_stop(s); 874 875 s->count = 0; 876 s->distance = 0; 877 s->progress = 0; 878 s->icntb = 0; 879 s->tcntb = 0; 880 } 881 882 /* 883 * tick_timer event. 884 * Raises when abstract tick_timer expires. 885 */ 886 static void exynos4210_ltick_timer_event(struct tick_timer *s) 887 { 888 s->progress += s->count; 889 } 890 891 /* 892 * Local timer tick counter handler. 893 * Don't use reloaded timers. If timer counter = zero 894 * then handler called but after handler finished no 895 * timer reload occurs. 896 */ 897 static void exynos4210_ltick_event(void *opaque) 898 { 899 Exynos4210MCTLT * s = (Exynos4210MCTLT *)opaque; 900 uint32_t tcnto; 901 uint32_t icnto; 902 #ifdef DEBUG_MCT 903 static uint64_t time1[2] = {0}; 904 static uint64_t time2[2] = {0}; 905 #endif 906 907 /* Call tick_timer event handler, it will update its tcntb and icntb. */ 908 exynos4210_ltick_timer_event(&s->tick_timer); 909 910 /* get tick_timer cnt */ 911 tcnto = exynos4210_ltick_cnt_get_cnto(&s->tick_timer); 912 913 /* get tick_timer int */ 914 icnto = exynos4210_ltick_int_get_cnto(&s->tick_timer); 915 916 /* raise IRQ if needed */ 917 if (!icnto && s->reg.tcon & L_TCON_INT_START) { 918 /* INT counter enabled and expired */ 919 920 s->reg.int_cstat |= L_INT_CSTAT_INTCNT; 921 922 /* raise interrupt if enabled */ 923 if (s->reg.int_enb & L_INT_INTENB_ICNTEIE) { 924 #ifdef DEBUG_MCT 925 time2[s->id] = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 926 DPRINTF("local timer[%d] IRQ: %llx\n", s->id, 927 time2[s->id] - time1[s->id]); 928 time1[s->id] = time2[s->id]; 929 #endif 930 qemu_irq_raise(s->irq); 931 } 932 933 /* reload ICNTB */ 934 if (s->reg.tcon & L_TCON_INTERVAL_MODE) { 935 exynos4210_ltick_set_cntb(&s->tick_timer, 936 s->reg.cnt[L_REG_CNT_TCNTB], 937 s->reg.cnt[L_REG_CNT_ICNTB]); 938 } 939 } else { 940 /* reload TCNTB */ 941 if (!tcnto) { 942 exynos4210_ltick_set_cntb(&s->tick_timer, 943 s->reg.cnt[L_REG_CNT_TCNTB], 944 icnto); 945 } 946 } 947 948 /* start tick_timer cnt */ 949 exynos4210_ltick_cnt_start(&s->tick_timer); 950 951 /* start tick_timer int */ 952 exynos4210_ltick_int_start(&s->tick_timer); 953 } 954 955 static void tx_ptimer_set_freq(ptimer_state *s, uint32_t freq) 956 { 957 /* 958 * callers of exynos4210_mct_update_freq() never do anything 959 * else that needs to be in the same ptimer transaction, so 960 * to avoid a lot of repetition we have a convenience function 961 * for begin/set_freq/commit. 962 */ 963 ptimer_transaction_begin(s); 964 ptimer_set_freq(s, freq); 965 ptimer_transaction_commit(s); 966 } 967 968 /* update timer frequency */ 969 static void exynos4210_mct_update_freq(Exynos4210MCTState *s) 970 { 971 uint32_t freq = s->freq; 972 s->freq = 24000000 / 973 ((MCT_CFG_GET_PRESCALER(s->reg_mct_cfg) + 1) * 974 MCT_CFG_GET_DIVIDER(s->reg_mct_cfg)); 975 976 if (freq != s->freq) { 977 DPRINTF("freq=%dHz\n", s->freq); 978 979 /* global timer */ 980 tx_ptimer_set_freq(s->g_timer.ptimer_frc, s->freq); 981 982 /* local timer */ 983 ptimer_set_freq(s->l_timer[0].tick_timer.ptimer_tick, s->freq); 984 ptimer_set_freq(s->l_timer[0].ptimer_frc, s->freq); 985 ptimer_set_freq(s->l_timer[1].tick_timer.ptimer_tick, s->freq); 986 ptimer_set_freq(s->l_timer[1].ptimer_frc, s->freq); 987 } 988 } 989 990 /* set defaul_timer values for all fields */ 991 static void exynos4210_mct_reset(DeviceState *d) 992 { 993 Exynos4210MCTState *s = EXYNOS4210_MCT(d); 994 uint32_t i; 995 996 s->reg_mct_cfg = 0; 997 998 /* global timer */ 999 memset(&s->g_timer.reg, 0, sizeof(s->g_timer.reg)); 1000 exynos4210_gfrc_tx_begin(&s->g_timer); 1001 exynos4210_gfrc_stop(&s->g_timer); 1002 exynos4210_gfrc_tx_commit(&s->g_timer); 1003 1004 /* local timer */ 1005 memset(s->l_timer[0].reg.cnt, 0, sizeof(s->l_timer[0].reg.cnt)); 1006 memset(s->l_timer[1].reg.cnt, 0, sizeof(s->l_timer[1].reg.cnt)); 1007 for (i = 0; i < 2; i++) { 1008 s->l_timer[i].reg.int_cstat = 0; 1009 s->l_timer[i].reg.int_enb = 0; 1010 s->l_timer[i].reg.tcon = 0; 1011 s->l_timer[i].reg.wstat = 0; 1012 s->l_timer[i].tick_timer.count = 0; 1013 s->l_timer[i].tick_timer.distance = 0; 1014 s->l_timer[i].tick_timer.progress = 0; 1015 ptimer_stop(s->l_timer[i].ptimer_frc); 1016 1017 exynos4210_ltick_timer_init(&s->l_timer[i].tick_timer); 1018 } 1019 1020 exynos4210_mct_update_freq(s); 1021 1022 } 1023 1024 /* Multi Core Timer read */ 1025 static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset, 1026 unsigned size) 1027 { 1028 Exynos4210MCTState *s = (Exynos4210MCTState *)opaque; 1029 int index; 1030 int shift; 1031 uint64_t count; 1032 uint32_t value; 1033 int lt_i; 1034 1035 switch (offset) { 1036 1037 case MCT_CFG: 1038 value = s->reg_mct_cfg; 1039 break; 1040 1041 case G_CNT_L: case G_CNT_U: 1042 shift = 8 * (offset & 0x4); 1043 count = exynos4210_gfrc_get_count(&s->g_timer); 1044 value = UINT32_MAX & (count >> shift); 1045 DPRINTF("read FRC=0x%llx\n", count); 1046 break; 1047 1048 case G_CNT_WSTAT: 1049 value = s->g_timer.reg.cnt_wstat; 1050 break; 1051 1052 case G_COMP_L(0): case G_COMP_L(1): case G_COMP_L(2): case G_COMP_L(3): 1053 case G_COMP_U(0): case G_COMP_U(1): case G_COMP_U(2): case G_COMP_U(3): 1054 index = GET_G_COMP_IDX(offset); 1055 shift = 8 * (offset & 0x4); 1056 value = UINT32_MAX & (s->g_timer.reg.comp[index] >> shift); 1057 break; 1058 1059 case G_TCON: 1060 value = s->g_timer.reg.tcon; 1061 break; 1062 1063 case G_INT_CSTAT: 1064 value = s->g_timer.reg.int_cstat; 1065 break; 1066 1067 case G_INT_ENB: 1068 value = s->g_timer.reg.int_enb; 1069 break; 1070 case G_WSTAT: 1071 value = s->g_timer.reg.wstat; 1072 break; 1073 1074 case G_COMP0_ADD_INCR: case G_COMP1_ADD_INCR: 1075 case G_COMP2_ADD_INCR: case G_COMP3_ADD_INCR: 1076 value = s->g_timer.reg.comp_add_incr[GET_G_COMP_ADD_INCR_IDX(offset)]; 1077 break; 1078 1079 /* Local timers */ 1080 case L0_TCNTB: case L0_ICNTB: case L0_FRCNTB: 1081 case L1_TCNTB: case L1_ICNTB: case L1_FRCNTB: 1082 lt_i = GET_L_TIMER_IDX(offset); 1083 index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i); 1084 value = s->l_timer[lt_i].reg.cnt[index]; 1085 break; 1086 1087 case L0_TCNTO: case L1_TCNTO: 1088 lt_i = GET_L_TIMER_IDX(offset); 1089 1090 value = exynos4210_ltick_cnt_get_cnto(&s->l_timer[lt_i].tick_timer); 1091 DPRINTF("local timer[%d] read TCNTO %x\n", lt_i, value); 1092 break; 1093 1094 case L0_ICNTO: case L1_ICNTO: 1095 lt_i = GET_L_TIMER_IDX(offset); 1096 1097 value = exynos4210_ltick_int_get_cnto(&s->l_timer[lt_i].tick_timer); 1098 DPRINTF("local timer[%d] read ICNTO %x\n", lt_i, value); 1099 break; 1100 1101 case L0_FRCNTO: case L1_FRCNTO: 1102 lt_i = GET_L_TIMER_IDX(offset); 1103 1104 value = exynos4210_lfrc_get_count(&s->l_timer[lt_i]); 1105 break; 1106 1107 case L0_TCON: case L1_TCON: 1108 lt_i = ((offset & 0xF00) - L0_TCNTB) / 0x100; 1109 value = s->l_timer[lt_i].reg.tcon; 1110 break; 1111 1112 case L0_INT_CSTAT: case L1_INT_CSTAT: 1113 lt_i = ((offset & 0xF00) - L0_TCNTB) / 0x100; 1114 value = s->l_timer[lt_i].reg.int_cstat; 1115 break; 1116 1117 case L0_INT_ENB: case L1_INT_ENB: 1118 lt_i = ((offset & 0xF00) - L0_TCNTB) / 0x100; 1119 value = s->l_timer[lt_i].reg.int_enb; 1120 break; 1121 1122 case L0_WSTAT: case L1_WSTAT: 1123 lt_i = ((offset & 0xF00) - L0_TCNTB) / 0x100; 1124 value = s->l_timer[lt_i].reg.wstat; 1125 break; 1126 1127 default: 1128 hw_error("exynos4210.mct: bad read offset " 1129 TARGET_FMT_plx "\n", offset); 1130 break; 1131 } 1132 return value; 1133 } 1134 1135 /* MCT write */ 1136 static void exynos4210_mct_write(void *opaque, hwaddr offset, 1137 uint64_t value, unsigned size) 1138 { 1139 Exynos4210MCTState *s = (Exynos4210MCTState *)opaque; 1140 int index; /* index in buffer which represents register set */ 1141 int shift; 1142 int lt_i; 1143 uint64_t new_frc; 1144 uint32_t i; 1145 uint32_t old_val; 1146 #ifdef DEBUG_MCT 1147 static uint32_t icntb_max[2] = {0}; 1148 static uint32_t icntb_min[2] = {UINT32_MAX, UINT32_MAX}; 1149 static uint32_t tcntb_max[2] = {0}; 1150 static uint32_t tcntb_min[2] = {UINT32_MAX, UINT32_MAX}; 1151 #endif 1152 1153 new_frc = s->g_timer.reg.cnt; 1154 1155 switch (offset) { 1156 1157 case MCT_CFG: 1158 s->reg_mct_cfg = value; 1159 exynos4210_mct_update_freq(s); 1160 break; 1161 1162 case G_CNT_L: 1163 case G_CNT_U: 1164 if (offset == G_CNT_L) { 1165 1166 DPRINTF("global timer write to reg.cntl %llx\n", value); 1167 1168 new_frc = (s->g_timer.reg.cnt & (uint64_t)UINT32_MAX << 32) + value; 1169 s->g_timer.reg.cnt_wstat |= G_CNT_WSTAT_L; 1170 } 1171 if (offset == G_CNT_U) { 1172 1173 DPRINTF("global timer write to reg.cntu %llx\n", value); 1174 1175 new_frc = (s->g_timer.reg.cnt & UINT32_MAX) + 1176 ((uint64_t)value << 32); 1177 s->g_timer.reg.cnt_wstat |= G_CNT_WSTAT_U; 1178 } 1179 1180 s->g_timer.reg.cnt = new_frc; 1181 exynos4210_gfrc_tx_begin(&s->g_timer); 1182 exynos4210_gfrc_restart(s); 1183 exynos4210_gfrc_tx_commit(&s->g_timer); 1184 break; 1185 1186 case G_CNT_WSTAT: 1187 s->g_timer.reg.cnt_wstat &= ~(value); 1188 break; 1189 1190 case G_COMP_L(0): case G_COMP_L(1): case G_COMP_L(2): case G_COMP_L(3): 1191 case G_COMP_U(0): case G_COMP_U(1): case G_COMP_U(2): case G_COMP_U(3): 1192 index = GET_G_COMP_IDX(offset); 1193 shift = 8 * (offset & 0x4); 1194 s->g_timer.reg.comp[index] = 1195 (s->g_timer.reg.comp[index] & 1196 (((uint64_t)UINT32_MAX << 32) >> shift)) + 1197 (value << shift); 1198 1199 DPRINTF("comparator %d write 0x%llx val << %d\n", index, value, shift); 1200 1201 if (offset & 0x4) { 1202 s->g_timer.reg.wstat |= G_WSTAT_COMP_U(index); 1203 } else { 1204 s->g_timer.reg.wstat |= G_WSTAT_COMP_L(index); 1205 } 1206 1207 exynos4210_gfrc_tx_begin(&s->g_timer); 1208 exynos4210_gfrc_restart(s); 1209 exynos4210_gfrc_tx_commit(&s->g_timer); 1210 break; 1211 1212 case G_TCON: 1213 old_val = s->g_timer.reg.tcon; 1214 s->g_timer.reg.tcon = value; 1215 s->g_timer.reg.wstat |= G_WSTAT_TCON_WRITE; 1216 1217 DPRINTF("global timer write to reg.g_tcon %llx\n", value); 1218 1219 exynos4210_gfrc_tx_begin(&s->g_timer); 1220 1221 /* Start FRC if transition from disabled to enabled */ 1222 if ((value & G_TCON_TIMER_ENABLE) > (old_val & 1223 G_TCON_TIMER_ENABLE)) { 1224 exynos4210_gfrc_start(&s->g_timer); 1225 } 1226 if ((value & G_TCON_TIMER_ENABLE) < (old_val & 1227 G_TCON_TIMER_ENABLE)) { 1228 exynos4210_gfrc_stop(&s->g_timer); 1229 } 1230 1231 /* Start CMP if transition from disabled to enabled */ 1232 for (i = 0; i < MCT_GT_CMP_NUM; i++) { 1233 if ((value & G_TCON_COMP_ENABLE(i)) != (old_val & 1234 G_TCON_COMP_ENABLE(i))) { 1235 exynos4210_gfrc_restart(s); 1236 } 1237 } 1238 1239 exynos4210_gfrc_tx_commit(&s->g_timer); 1240 break; 1241 1242 case G_INT_CSTAT: 1243 s->g_timer.reg.int_cstat &= ~(value); 1244 for (i = 0; i < MCT_GT_CMP_NUM; i++) { 1245 if (value & G_INT_CSTAT_COMP(i)) { 1246 exynos4210_gcomp_lower_irq(&s->g_timer, i); 1247 } 1248 } 1249 break; 1250 1251 case G_INT_ENB: 1252 /* Raise IRQ if transition from disabled to enabled and CSTAT pending */ 1253 for (i = 0; i < MCT_GT_CMP_NUM; i++) { 1254 if ((value & G_INT_ENABLE(i)) > (s->g_timer.reg.tcon & 1255 G_INT_ENABLE(i))) { 1256 if (s->g_timer.reg.int_cstat & G_INT_CSTAT_COMP(i)) { 1257 exynos4210_gcomp_raise_irq(&s->g_timer, i); 1258 } 1259 } 1260 1261 if ((value & G_INT_ENABLE(i)) < (s->g_timer.reg.tcon & 1262 G_INT_ENABLE(i))) { 1263 exynos4210_gcomp_lower_irq(&s->g_timer, i); 1264 } 1265 } 1266 1267 DPRINTF("global timer INT enable %llx\n", value); 1268 s->g_timer.reg.int_enb = value; 1269 break; 1270 1271 case G_WSTAT: 1272 s->g_timer.reg.wstat &= ~(value); 1273 break; 1274 1275 case G_COMP0_ADD_INCR: case G_COMP1_ADD_INCR: 1276 case G_COMP2_ADD_INCR: case G_COMP3_ADD_INCR: 1277 index = GET_G_COMP_ADD_INCR_IDX(offset); 1278 s->g_timer.reg.comp_add_incr[index] = value; 1279 s->g_timer.reg.wstat |= G_WSTAT_COMP_ADDINCR(index); 1280 break; 1281 1282 /* Local timers */ 1283 case L0_TCON: case L1_TCON: 1284 lt_i = GET_L_TIMER_IDX(offset); 1285 old_val = s->l_timer[lt_i].reg.tcon; 1286 1287 s->l_timer[lt_i].reg.wstat |= L_WSTAT_TCON_WRITE; 1288 s->l_timer[lt_i].reg.tcon = value; 1289 1290 /* Stop local CNT */ 1291 if ((value & L_TCON_TICK_START) < 1292 (old_val & L_TCON_TICK_START)) { 1293 DPRINTF("local timer[%d] stop cnt\n", lt_i); 1294 exynos4210_ltick_cnt_stop(&s->l_timer[lt_i].tick_timer); 1295 } 1296 1297 /* Stop local INT */ 1298 if ((value & L_TCON_INT_START) < 1299 (old_val & L_TCON_INT_START)) { 1300 DPRINTF("local timer[%d] stop int\n", lt_i); 1301 exynos4210_ltick_int_stop(&s->l_timer[lt_i].tick_timer); 1302 } 1303 1304 /* Start local CNT */ 1305 if ((value & L_TCON_TICK_START) > 1306 (old_val & L_TCON_TICK_START)) { 1307 DPRINTF("local timer[%d] start cnt\n", lt_i); 1308 exynos4210_ltick_cnt_start(&s->l_timer[lt_i].tick_timer); 1309 } 1310 1311 /* Start local INT */ 1312 if ((value & L_TCON_INT_START) > 1313 (old_val & L_TCON_INT_START)) { 1314 DPRINTF("local timer[%d] start int\n", lt_i); 1315 exynos4210_ltick_int_start(&s->l_timer[lt_i].tick_timer); 1316 } 1317 1318 /* Start or Stop local FRC if TCON changed */ 1319 if ((value & L_TCON_FRC_START) > 1320 (s->l_timer[lt_i].reg.tcon & L_TCON_FRC_START)) { 1321 DPRINTF("local timer[%d] start frc\n", lt_i); 1322 exynos4210_lfrc_start(&s->l_timer[lt_i]); 1323 } 1324 if ((value & L_TCON_FRC_START) < 1325 (s->l_timer[lt_i].reg.tcon & L_TCON_FRC_START)) { 1326 DPRINTF("local timer[%d] stop frc\n", lt_i); 1327 exynos4210_lfrc_stop(&s->l_timer[lt_i]); 1328 } 1329 break; 1330 1331 case L0_TCNTB: case L1_TCNTB: 1332 lt_i = GET_L_TIMER_IDX(offset); 1333 index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i); 1334 1335 /* 1336 * TCNTB is updated to internal register only after CNT expired. 1337 * Due to this we should reload timer to nearest moment when CNT is 1338 * expired and then in event handler update tcntb to new TCNTB value. 1339 */ 1340 exynos4210_ltick_set_cntb(&s->l_timer[lt_i].tick_timer, value, 1341 s->l_timer[lt_i].tick_timer.icntb); 1342 1343 s->l_timer[lt_i].reg.wstat |= L_WSTAT_TCNTB_WRITE; 1344 s->l_timer[lt_i].reg.cnt[L_REG_CNT_TCNTB] = value; 1345 1346 #ifdef DEBUG_MCT 1347 if (tcntb_min[lt_i] > value) { 1348 tcntb_min[lt_i] = value; 1349 } 1350 if (tcntb_max[lt_i] < value) { 1351 tcntb_max[lt_i] = value; 1352 } 1353 DPRINTF("local timer[%d] TCNTB write %llx; max=%x, min=%x\n", 1354 lt_i, value, tcntb_max[lt_i], tcntb_min[lt_i]); 1355 #endif 1356 break; 1357 1358 case L0_ICNTB: case L1_ICNTB: 1359 lt_i = GET_L_TIMER_IDX(offset); 1360 index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i); 1361 1362 s->l_timer[lt_i].reg.wstat |= L_WSTAT_ICNTB_WRITE; 1363 s->l_timer[lt_i].reg.cnt[L_REG_CNT_ICNTB] = value & 1364 ~L_ICNTB_MANUAL_UPDATE; 1365 1366 /* 1367 * We need to avoid too small values for TCNTB*ICNTB. If not, IRQ event 1368 * could raise too fast disallowing QEMU to execute target code. 1369 */ 1370 if (s->l_timer[lt_i].reg.cnt[L_REG_CNT_ICNTB] * 1371 s->l_timer[lt_i].reg.cnt[L_REG_CNT_TCNTB] < MCT_LT_CNT_LOW_LIMIT) { 1372 if (!s->l_timer[lt_i].reg.cnt[L_REG_CNT_TCNTB]) { 1373 s->l_timer[lt_i].reg.cnt[L_REG_CNT_ICNTB] = 1374 MCT_LT_CNT_LOW_LIMIT; 1375 } else { 1376 s->l_timer[lt_i].reg.cnt[L_REG_CNT_ICNTB] = 1377 MCT_LT_CNT_LOW_LIMIT / 1378 s->l_timer[lt_i].reg.cnt[L_REG_CNT_TCNTB]; 1379 } 1380 } 1381 1382 if (value & L_ICNTB_MANUAL_UPDATE) { 1383 exynos4210_ltick_set_cntb(&s->l_timer[lt_i].tick_timer, 1384 s->l_timer[lt_i].tick_timer.tcntb, 1385 s->l_timer[lt_i].reg.cnt[L_REG_CNT_ICNTB]); 1386 } 1387 1388 #ifdef DEBUG_MCT 1389 if (icntb_min[lt_i] > value) { 1390 icntb_min[lt_i] = value; 1391 } 1392 if (icntb_max[lt_i] < value) { 1393 icntb_max[lt_i] = value; 1394 } 1395 DPRINTF("local timer[%d] ICNTB write %llx; max=%x, min=%x\n\n", 1396 lt_i, value, icntb_max[lt_i], icntb_min[lt_i]); 1397 #endif 1398 break; 1399 1400 case L0_FRCNTB: case L1_FRCNTB: 1401 lt_i = GET_L_TIMER_IDX(offset); 1402 index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i); 1403 1404 DPRINTF("local timer[%d] FRCNTB write %llx\n", lt_i, value); 1405 1406 s->l_timer[lt_i].reg.wstat |= L_WSTAT_FRCCNTB_WRITE; 1407 s->l_timer[lt_i].reg.cnt[L_REG_CNT_FRCCNTB] = value; 1408 1409 break; 1410 1411 case L0_TCNTO: case L1_TCNTO: 1412 case L0_ICNTO: case L1_ICNTO: 1413 case L0_FRCNTO: case L1_FRCNTO: 1414 qemu_log_mask(LOG_GUEST_ERROR, 1415 "exynos4210.mct: write to RO register " TARGET_FMT_plx, 1416 offset); 1417 break; 1418 1419 case L0_INT_CSTAT: case L1_INT_CSTAT: 1420 lt_i = GET_L_TIMER_IDX(offset); 1421 1422 DPRINTF("local timer[%d] CSTAT write %llx\n", lt_i, value); 1423 1424 s->l_timer[lt_i].reg.int_cstat &= ~value; 1425 if (!s->l_timer[lt_i].reg.int_cstat) { 1426 qemu_irq_lower(s->l_timer[lt_i].irq); 1427 } 1428 break; 1429 1430 case L0_INT_ENB: case L1_INT_ENB: 1431 lt_i = GET_L_TIMER_IDX(offset); 1432 old_val = s->l_timer[lt_i].reg.int_enb; 1433 1434 /* Raise Local timer IRQ if cstat is pending */ 1435 if ((value & L_INT_INTENB_ICNTEIE) > (old_val & L_INT_INTENB_ICNTEIE)) { 1436 if (s->l_timer[lt_i].reg.int_cstat & L_INT_CSTAT_INTCNT) { 1437 qemu_irq_raise(s->l_timer[lt_i].irq); 1438 } 1439 } 1440 1441 s->l_timer[lt_i].reg.int_enb = value; 1442 1443 break; 1444 1445 case L0_WSTAT: case L1_WSTAT: 1446 lt_i = GET_L_TIMER_IDX(offset); 1447 1448 s->l_timer[lt_i].reg.wstat &= ~value; 1449 break; 1450 1451 default: 1452 hw_error("exynos4210.mct: bad write offset " 1453 TARGET_FMT_plx "\n", offset); 1454 break; 1455 } 1456 } 1457 1458 static const MemoryRegionOps exynos4210_mct_ops = { 1459 .read = exynos4210_mct_read, 1460 .write = exynos4210_mct_write, 1461 .endianness = DEVICE_NATIVE_ENDIAN, 1462 }; 1463 1464 /* MCT init */ 1465 static void exynos4210_mct_init(Object *obj) 1466 { 1467 int i; 1468 Exynos4210MCTState *s = EXYNOS4210_MCT(obj); 1469 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 1470 QEMUBH *bh[2]; 1471 1472 /* Global timer */ 1473 s->g_timer.ptimer_frc = ptimer_init(exynos4210_gfrc_event, s, 1474 PTIMER_POLICY_DEFAULT); 1475 memset(&s->g_timer.reg, 0, sizeof(struct gregs)); 1476 1477 /* Local timers */ 1478 for (i = 0; i < 2; i++) { 1479 bh[0] = qemu_bh_new(exynos4210_ltick_event, &s->l_timer[i]); 1480 bh[1] = qemu_bh_new(exynos4210_lfrc_event, &s->l_timer[i]); 1481 s->l_timer[i].tick_timer.ptimer_tick = 1482 ptimer_init_with_bh(bh[0], PTIMER_POLICY_DEFAULT); 1483 s->l_timer[i].ptimer_frc = 1484 ptimer_init_with_bh(bh[1], PTIMER_POLICY_DEFAULT); 1485 s->l_timer[i].id = i; 1486 } 1487 1488 /* IRQs */ 1489 for (i = 0; i < MCT_GT_CMP_NUM; i++) { 1490 sysbus_init_irq(dev, &s->g_timer.irq[i]); 1491 } 1492 for (i = 0; i < 2; i++) { 1493 sysbus_init_irq(dev, &s->l_timer[i].irq); 1494 } 1495 1496 memory_region_init_io(&s->iomem, obj, &exynos4210_mct_ops, s, 1497 "exynos4210-mct", MCT_SFR_SIZE); 1498 sysbus_init_mmio(dev, &s->iomem); 1499 } 1500 1501 static void exynos4210_mct_class_init(ObjectClass *klass, void *data) 1502 { 1503 DeviceClass *dc = DEVICE_CLASS(klass); 1504 1505 dc->reset = exynos4210_mct_reset; 1506 dc->vmsd = &vmstate_exynos4210_mct_state; 1507 } 1508 1509 static const TypeInfo exynos4210_mct_info = { 1510 .name = TYPE_EXYNOS4210_MCT, 1511 .parent = TYPE_SYS_BUS_DEVICE, 1512 .instance_size = sizeof(Exynos4210MCTState), 1513 .instance_init = exynos4210_mct_init, 1514 .class_init = exynos4210_mct_class_init, 1515 }; 1516 1517 static void exynos4210_mct_register_types(void) 1518 { 1519 type_register_static(&exynos4210_mct_info); 1520 } 1521 1522 type_init(exynos4210_mct_register_types) 1523