1 /* 2 * QEMU ETRAX Timers 3 * 4 * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/sysbus.h" 25 #include "sysemu/sysemu.h" 26 #include "qemu/timer.h" 27 #include "hw/ptimer.h" 28 29 #define D(x) 30 31 #define RW_TMR0_DIV 0x00 32 #define R_TMR0_DATA 0x04 33 #define RW_TMR0_CTRL 0x08 34 #define RW_TMR1_DIV 0x10 35 #define R_TMR1_DATA 0x14 36 #define RW_TMR1_CTRL 0x18 37 #define R_TIME 0x38 38 #define RW_WD_CTRL 0x40 39 #define R_WD_STAT 0x44 40 #define RW_INTR_MASK 0x48 41 #define RW_ACK_INTR 0x4c 42 #define R_INTR 0x50 43 #define R_MASKED_INTR 0x54 44 45 struct etrax_timer { 46 SysBusDevice busdev; 47 MemoryRegion mmio; 48 qemu_irq irq; 49 qemu_irq nmi; 50 51 QEMUBH *bh_t0; 52 QEMUBH *bh_t1; 53 QEMUBH *bh_wd; 54 ptimer_state *ptimer_t0; 55 ptimer_state *ptimer_t1; 56 ptimer_state *ptimer_wd; 57 58 int wd_hits; 59 60 /* Control registers. */ 61 uint32_t rw_tmr0_div; 62 uint32_t r_tmr0_data; 63 uint32_t rw_tmr0_ctrl; 64 65 uint32_t rw_tmr1_div; 66 uint32_t r_tmr1_data; 67 uint32_t rw_tmr1_ctrl; 68 69 uint32_t rw_wd_ctrl; 70 71 uint32_t rw_intr_mask; 72 uint32_t rw_ack_intr; 73 uint32_t r_intr; 74 uint32_t r_masked_intr; 75 }; 76 77 static uint64_t 78 timer_read(void *opaque, hwaddr addr, unsigned int size) 79 { 80 struct etrax_timer *t = opaque; 81 uint32_t r = 0; 82 83 switch (addr) { 84 case R_TMR0_DATA: 85 r = ptimer_get_count(t->ptimer_t0); 86 break; 87 case R_TMR1_DATA: 88 r = ptimer_get_count(t->ptimer_t1); 89 break; 90 case R_TIME: 91 r = qemu_get_clock_ns(vm_clock) / 10; 92 break; 93 case RW_INTR_MASK: 94 r = t->rw_intr_mask; 95 break; 96 case R_MASKED_INTR: 97 r = t->r_intr & t->rw_intr_mask; 98 break; 99 default: 100 D(printf ("%s %x\n", __func__, addr)); 101 break; 102 } 103 return r; 104 } 105 106 static void update_ctrl(struct etrax_timer *t, int tnum) 107 { 108 unsigned int op; 109 unsigned int freq; 110 unsigned int freq_hz; 111 unsigned int div; 112 uint32_t ctrl; 113 114 ptimer_state *timer; 115 116 if (tnum == 0) { 117 ctrl = t->rw_tmr0_ctrl; 118 div = t->rw_tmr0_div; 119 timer = t->ptimer_t0; 120 } else { 121 ctrl = t->rw_tmr1_ctrl; 122 div = t->rw_tmr1_div; 123 timer = t->ptimer_t1; 124 } 125 126 127 op = ctrl & 3; 128 freq = ctrl >> 2; 129 freq_hz = 32000000; 130 131 switch (freq) 132 { 133 case 0: 134 case 1: 135 D(printf ("extern or disabled timer clock?\n")); 136 break; 137 case 4: freq_hz = 29493000; break; 138 case 5: freq_hz = 32000000; break; 139 case 6: freq_hz = 32768000; break; 140 case 7: freq_hz = 100000000; break; 141 default: 142 abort(); 143 break; 144 } 145 146 D(printf ("freq_hz=%d div=%d\n", freq_hz, div)); 147 ptimer_set_freq(timer, freq_hz); 148 ptimer_set_limit(timer, div, 0); 149 150 switch (op) 151 { 152 case 0: 153 /* Load. */ 154 ptimer_set_limit(timer, div, 1); 155 break; 156 case 1: 157 /* Hold. */ 158 ptimer_stop(timer); 159 break; 160 case 2: 161 /* Run. */ 162 ptimer_run(timer, 0); 163 break; 164 default: 165 abort(); 166 break; 167 } 168 } 169 170 static void timer_update_irq(struct etrax_timer *t) 171 { 172 t->r_intr &= ~(t->rw_ack_intr); 173 t->r_masked_intr = t->r_intr & t->rw_intr_mask; 174 175 D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr)); 176 qemu_set_irq(t->irq, !!t->r_masked_intr); 177 } 178 179 static void timer0_hit(void *opaque) 180 { 181 struct etrax_timer *t = opaque; 182 t->r_intr |= 1; 183 timer_update_irq(t); 184 } 185 186 static void timer1_hit(void *opaque) 187 { 188 struct etrax_timer *t = opaque; 189 t->r_intr |= 2; 190 timer_update_irq(t); 191 } 192 193 static void watchdog_hit(void *opaque) 194 { 195 struct etrax_timer *t = opaque; 196 if (t->wd_hits == 0) { 197 /* real hw gives a single tick before reseting but we are 198 a bit friendlier to compensate for our slower execution. */ 199 ptimer_set_count(t->ptimer_wd, 10); 200 ptimer_run(t->ptimer_wd, 1); 201 qemu_irq_raise(t->nmi); 202 } 203 else 204 qemu_system_reset_request(); 205 206 t->wd_hits++; 207 } 208 209 static inline void timer_watchdog_update(struct etrax_timer *t, uint32_t value) 210 { 211 unsigned int wd_en = t->rw_wd_ctrl & (1 << 8); 212 unsigned int wd_key = t->rw_wd_ctrl >> 9; 213 unsigned int wd_cnt = t->rw_wd_ctrl & 511; 214 unsigned int new_key = value >> 9 & ((1 << 7) - 1); 215 unsigned int new_cmd = (value >> 8) & 1; 216 217 /* If the watchdog is enabled, they written key must match the 218 complement of the previous. */ 219 wd_key = ~wd_key & ((1 << 7) - 1); 220 221 if (wd_en && wd_key != new_key) 222 return; 223 224 D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n", 225 wd_en, new_key, wd_key, new_cmd, wd_cnt)); 226 227 if (t->wd_hits) 228 qemu_irq_lower(t->nmi); 229 230 t->wd_hits = 0; 231 232 ptimer_set_freq(t->ptimer_wd, 760); 233 if (wd_cnt == 0) 234 wd_cnt = 256; 235 ptimer_set_count(t->ptimer_wd, wd_cnt); 236 if (new_cmd) 237 ptimer_run(t->ptimer_wd, 1); 238 else 239 ptimer_stop(t->ptimer_wd); 240 241 t->rw_wd_ctrl = value; 242 } 243 244 static void 245 timer_write(void *opaque, hwaddr addr, 246 uint64_t val64, unsigned int size) 247 { 248 struct etrax_timer *t = opaque; 249 uint32_t value = val64; 250 251 switch (addr) 252 { 253 case RW_TMR0_DIV: 254 t->rw_tmr0_div = value; 255 break; 256 case RW_TMR0_CTRL: 257 D(printf ("RW_TMR0_CTRL=%x\n", value)); 258 t->rw_tmr0_ctrl = value; 259 update_ctrl(t, 0); 260 break; 261 case RW_TMR1_DIV: 262 t->rw_tmr1_div = value; 263 break; 264 case RW_TMR1_CTRL: 265 D(printf ("RW_TMR1_CTRL=%x\n", value)); 266 t->rw_tmr1_ctrl = value; 267 update_ctrl(t, 1); 268 break; 269 case RW_INTR_MASK: 270 D(printf ("RW_INTR_MASK=%x\n", value)); 271 t->rw_intr_mask = value; 272 timer_update_irq(t); 273 break; 274 case RW_WD_CTRL: 275 timer_watchdog_update(t, value); 276 break; 277 case RW_ACK_INTR: 278 t->rw_ack_intr = value; 279 timer_update_irq(t); 280 t->rw_ack_intr = 0; 281 break; 282 default: 283 printf ("%s " TARGET_FMT_plx " %x\n", 284 __func__, addr, value); 285 break; 286 } 287 } 288 289 static const MemoryRegionOps timer_ops = { 290 .read = timer_read, 291 .write = timer_write, 292 .endianness = DEVICE_LITTLE_ENDIAN, 293 .valid = { 294 .min_access_size = 4, 295 .max_access_size = 4 296 } 297 }; 298 299 static void etraxfs_timer_reset(void *opaque) 300 { 301 struct etrax_timer *t = opaque; 302 303 ptimer_stop(t->ptimer_t0); 304 ptimer_stop(t->ptimer_t1); 305 ptimer_stop(t->ptimer_wd); 306 t->rw_wd_ctrl = 0; 307 t->r_intr = 0; 308 t->rw_intr_mask = 0; 309 qemu_irq_lower(t->irq); 310 } 311 312 static int etraxfs_timer_init(SysBusDevice *dev) 313 { 314 struct etrax_timer *t = FROM_SYSBUS(typeof (*t), dev); 315 316 t->bh_t0 = qemu_bh_new(timer0_hit, t); 317 t->bh_t1 = qemu_bh_new(timer1_hit, t); 318 t->bh_wd = qemu_bh_new(watchdog_hit, t); 319 t->ptimer_t0 = ptimer_init(t->bh_t0); 320 t->ptimer_t1 = ptimer_init(t->bh_t1); 321 t->ptimer_wd = ptimer_init(t->bh_wd); 322 323 sysbus_init_irq(dev, &t->irq); 324 sysbus_init_irq(dev, &t->nmi); 325 326 memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, 327 "etraxfs-timer", 0x5c); 328 sysbus_init_mmio(dev, &t->mmio); 329 qemu_register_reset(etraxfs_timer_reset, t); 330 return 0; 331 } 332 333 static void etraxfs_timer_class_init(ObjectClass *klass, void *data) 334 { 335 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 336 337 sdc->init = etraxfs_timer_init; 338 } 339 340 static const TypeInfo etraxfs_timer_info = { 341 .name = "etraxfs,timer", 342 .parent = TYPE_SYS_BUS_DEVICE, 343 .instance_size = sizeof (struct etrax_timer), 344 .class_init = etraxfs_timer_class_init, 345 }; 346 347 static void etraxfs_timer_register_types(void) 348 { 349 type_register_static(&etraxfs_timer_info); 350 } 351 352 type_init(etraxfs_timer_register_types) 353