1 /* 2 * QEMU ETRAX Timers 3 * 4 * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/sysbus.h" 27 #include "sysemu/reset.h" 28 #include "sysemu/sysemu.h" 29 #include "qemu/module.h" 30 #include "qemu/timer.h" 31 #include "hw/irq.h" 32 #include "hw/ptimer.h" 33 34 #define D(x) 35 36 #define RW_TMR0_DIV 0x00 37 #define R_TMR0_DATA 0x04 38 #define RW_TMR0_CTRL 0x08 39 #define RW_TMR1_DIV 0x10 40 #define R_TMR1_DATA 0x14 41 #define RW_TMR1_CTRL 0x18 42 #define R_TIME 0x38 43 #define RW_WD_CTRL 0x40 44 #define R_WD_STAT 0x44 45 #define RW_INTR_MASK 0x48 46 #define RW_ACK_INTR 0x4c 47 #define R_INTR 0x50 48 #define R_MASKED_INTR 0x54 49 50 #define TYPE_ETRAX_FS_TIMER "etraxfs,timer" 51 #define ETRAX_TIMER(obj) \ 52 OBJECT_CHECK(ETRAXTimerState, (obj), TYPE_ETRAX_FS_TIMER) 53 54 typedef struct ETRAXTimerState { 55 SysBusDevice parent_obj; 56 57 MemoryRegion mmio; 58 qemu_irq irq; 59 qemu_irq nmi; 60 61 QEMUBH *bh_t0; 62 QEMUBH *bh_t1; 63 QEMUBH *bh_wd; 64 ptimer_state *ptimer_t0; 65 ptimer_state *ptimer_t1; 66 ptimer_state *ptimer_wd; 67 68 int wd_hits; 69 70 /* Control registers. */ 71 uint32_t rw_tmr0_div; 72 uint32_t r_tmr0_data; 73 uint32_t rw_tmr0_ctrl; 74 75 uint32_t rw_tmr1_div; 76 uint32_t r_tmr1_data; 77 uint32_t rw_tmr1_ctrl; 78 79 uint32_t rw_wd_ctrl; 80 81 uint32_t rw_intr_mask; 82 uint32_t rw_ack_intr; 83 uint32_t r_intr; 84 uint32_t r_masked_intr; 85 } ETRAXTimerState; 86 87 static uint64_t 88 timer_read(void *opaque, hwaddr addr, unsigned int size) 89 { 90 ETRAXTimerState *t = opaque; 91 uint32_t r = 0; 92 93 switch (addr) { 94 case R_TMR0_DATA: 95 r = ptimer_get_count(t->ptimer_t0); 96 break; 97 case R_TMR1_DATA: 98 r = ptimer_get_count(t->ptimer_t1); 99 break; 100 case R_TIME: 101 r = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 10; 102 break; 103 case RW_INTR_MASK: 104 r = t->rw_intr_mask; 105 break; 106 case R_MASKED_INTR: 107 r = t->r_intr & t->rw_intr_mask; 108 break; 109 default: 110 D(printf ("%s %x\n", __func__, addr)); 111 break; 112 } 113 return r; 114 } 115 116 static void update_ctrl(ETRAXTimerState *t, int tnum) 117 { 118 unsigned int op; 119 unsigned int freq; 120 unsigned int freq_hz; 121 unsigned int div; 122 uint32_t ctrl; 123 124 ptimer_state *timer; 125 126 if (tnum == 0) { 127 ctrl = t->rw_tmr0_ctrl; 128 div = t->rw_tmr0_div; 129 timer = t->ptimer_t0; 130 } else { 131 ctrl = t->rw_tmr1_ctrl; 132 div = t->rw_tmr1_div; 133 timer = t->ptimer_t1; 134 } 135 136 137 op = ctrl & 3; 138 freq = ctrl >> 2; 139 freq_hz = 32000000; 140 141 switch (freq) 142 { 143 case 0: 144 case 1: 145 D(printf ("extern or disabled timer clock?\n")); 146 break; 147 case 4: freq_hz = 29493000; break; 148 case 5: freq_hz = 32000000; break; 149 case 6: freq_hz = 32768000; break; 150 case 7: freq_hz = 100000000; break; 151 default: 152 abort(); 153 break; 154 } 155 156 D(printf ("freq_hz=%d div=%d\n", freq_hz, div)); 157 ptimer_set_freq(timer, freq_hz); 158 ptimer_set_limit(timer, div, 0); 159 160 switch (op) 161 { 162 case 0: 163 /* Load. */ 164 ptimer_set_limit(timer, div, 1); 165 break; 166 case 1: 167 /* Hold. */ 168 ptimer_stop(timer); 169 break; 170 case 2: 171 /* Run. */ 172 ptimer_run(timer, 0); 173 break; 174 default: 175 abort(); 176 break; 177 } 178 } 179 180 static void timer_update_irq(ETRAXTimerState *t) 181 { 182 t->r_intr &= ~(t->rw_ack_intr); 183 t->r_masked_intr = t->r_intr & t->rw_intr_mask; 184 185 D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr)); 186 qemu_set_irq(t->irq, !!t->r_masked_intr); 187 } 188 189 static void timer0_hit(void *opaque) 190 { 191 ETRAXTimerState *t = opaque; 192 t->r_intr |= 1; 193 timer_update_irq(t); 194 } 195 196 static void timer1_hit(void *opaque) 197 { 198 ETRAXTimerState *t = opaque; 199 t->r_intr |= 2; 200 timer_update_irq(t); 201 } 202 203 static void watchdog_hit(void *opaque) 204 { 205 ETRAXTimerState *t = opaque; 206 if (t->wd_hits == 0) { 207 /* real hw gives a single tick before reseting but we are 208 a bit friendlier to compensate for our slower execution. */ 209 ptimer_set_count(t->ptimer_wd, 10); 210 ptimer_run(t->ptimer_wd, 1); 211 qemu_irq_raise(t->nmi); 212 } 213 else 214 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 215 216 t->wd_hits++; 217 } 218 219 static inline void timer_watchdog_update(ETRAXTimerState *t, uint32_t value) 220 { 221 unsigned int wd_en = t->rw_wd_ctrl & (1 << 8); 222 unsigned int wd_key = t->rw_wd_ctrl >> 9; 223 unsigned int wd_cnt = t->rw_wd_ctrl & 511; 224 unsigned int new_key = value >> 9 & ((1 << 7) - 1); 225 unsigned int new_cmd = (value >> 8) & 1; 226 227 /* If the watchdog is enabled, they written key must match the 228 complement of the previous. */ 229 wd_key = ~wd_key & ((1 << 7) - 1); 230 231 if (wd_en && wd_key != new_key) 232 return; 233 234 D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n", 235 wd_en, new_key, wd_key, new_cmd, wd_cnt)); 236 237 if (t->wd_hits) 238 qemu_irq_lower(t->nmi); 239 240 t->wd_hits = 0; 241 242 ptimer_set_freq(t->ptimer_wd, 760); 243 if (wd_cnt == 0) 244 wd_cnt = 256; 245 ptimer_set_count(t->ptimer_wd, wd_cnt); 246 if (new_cmd) 247 ptimer_run(t->ptimer_wd, 1); 248 else 249 ptimer_stop(t->ptimer_wd); 250 251 t->rw_wd_ctrl = value; 252 } 253 254 static void 255 timer_write(void *opaque, hwaddr addr, 256 uint64_t val64, unsigned int size) 257 { 258 ETRAXTimerState *t = opaque; 259 uint32_t value = val64; 260 261 switch (addr) 262 { 263 case RW_TMR0_DIV: 264 t->rw_tmr0_div = value; 265 break; 266 case RW_TMR0_CTRL: 267 D(printf ("RW_TMR0_CTRL=%x\n", value)); 268 t->rw_tmr0_ctrl = value; 269 update_ctrl(t, 0); 270 break; 271 case RW_TMR1_DIV: 272 t->rw_tmr1_div = value; 273 break; 274 case RW_TMR1_CTRL: 275 D(printf ("RW_TMR1_CTRL=%x\n", value)); 276 t->rw_tmr1_ctrl = value; 277 update_ctrl(t, 1); 278 break; 279 case RW_INTR_MASK: 280 D(printf ("RW_INTR_MASK=%x\n", value)); 281 t->rw_intr_mask = value; 282 timer_update_irq(t); 283 break; 284 case RW_WD_CTRL: 285 timer_watchdog_update(t, value); 286 break; 287 case RW_ACK_INTR: 288 t->rw_ack_intr = value; 289 timer_update_irq(t); 290 t->rw_ack_intr = 0; 291 break; 292 default: 293 printf ("%s " TARGET_FMT_plx " %x\n", 294 __func__, addr, value); 295 break; 296 } 297 } 298 299 static const MemoryRegionOps timer_ops = { 300 .read = timer_read, 301 .write = timer_write, 302 .endianness = DEVICE_LITTLE_ENDIAN, 303 .valid = { 304 .min_access_size = 4, 305 .max_access_size = 4 306 } 307 }; 308 309 static void etraxfs_timer_reset(void *opaque) 310 { 311 ETRAXTimerState *t = opaque; 312 313 ptimer_stop(t->ptimer_t0); 314 ptimer_stop(t->ptimer_t1); 315 ptimer_stop(t->ptimer_wd); 316 t->rw_wd_ctrl = 0; 317 t->r_intr = 0; 318 t->rw_intr_mask = 0; 319 qemu_irq_lower(t->irq); 320 } 321 322 static void etraxfs_timer_realize(DeviceState *dev, Error **errp) 323 { 324 ETRAXTimerState *t = ETRAX_TIMER(dev); 325 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 326 327 t->bh_t0 = qemu_bh_new(timer0_hit, t); 328 t->bh_t1 = qemu_bh_new(timer1_hit, t); 329 t->bh_wd = qemu_bh_new(watchdog_hit, t); 330 t->ptimer_t0 = ptimer_init(t->bh_t0, PTIMER_POLICY_DEFAULT); 331 t->ptimer_t1 = ptimer_init(t->bh_t1, PTIMER_POLICY_DEFAULT); 332 t->ptimer_wd = ptimer_init(t->bh_wd, PTIMER_POLICY_DEFAULT); 333 334 sysbus_init_irq(sbd, &t->irq); 335 sysbus_init_irq(sbd, &t->nmi); 336 337 memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, 338 "etraxfs-timer", 0x5c); 339 sysbus_init_mmio(sbd, &t->mmio); 340 qemu_register_reset(etraxfs_timer_reset, t); 341 } 342 343 static void etraxfs_timer_class_init(ObjectClass *klass, void *data) 344 { 345 DeviceClass *dc = DEVICE_CLASS(klass); 346 347 dc->realize = etraxfs_timer_realize; 348 } 349 350 static const TypeInfo etraxfs_timer_info = { 351 .name = TYPE_ETRAX_FS_TIMER, 352 .parent = TYPE_SYS_BUS_DEVICE, 353 .instance_size = sizeof(ETRAXTimerState), 354 .class_init = etraxfs_timer_class_init, 355 }; 356 357 static void etraxfs_timer_register_types(void) 358 { 359 type_register_static(&etraxfs_timer_info); 360 } 361 362 type_init(etraxfs_timer_register_types) 363