xref: /openbmc/qemu/hw/timer/digic-timer.c (revision 77d361b1)
1 /*
2  * QEMU model of the Canon DIGIC timer block.
3  *
4  * Copyright (C) 2013 Antony Pavlov <antonynpavlov@gmail.com>
5  *
6  * This model is based on reverse engineering efforts
7  * made by CHDK (http://chdk.wikia.com) and
8  * Magic Lantern (http://www.magiclantern.fm) projects
9  * contributors.
10  *
11  * See "Timer/Clock Module" docs here:
12  *   http://magiclantern.wikia.com/wiki/Register_Map
13  *
14  * The QEMU model of the OSTimer in PKUnity SoC by Guan Xuetao
15  * is used as a template.
16  *
17  * This program is free software; you can redistribute it and/or modify
18  * it under the terms of the GNU General Public License as published by
19  * the Free Software Foundation; either version 2 of the License, or
20  * (at your option) any later version.
21  *
22  * This program is distributed in the hope that it will be useful,
23  * but WITHOUT ANY WARRANTY; without even the implied warranty of
24  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25  * GNU General Public License for more details.
26  *
27  */
28 
29 #include "qemu/osdep.h"
30 #include "hw/sysbus.h"
31 #include "hw/ptimer.h"
32 #include "qemu/main-loop.h"
33 #include "qemu/log.h"
34 
35 #include "hw/timer/digic-timer.h"
36 
37 static const VMStateDescription vmstate_digic_timer = {
38     .name = "digic.timer",
39     .version_id = 1,
40     .minimum_version_id = 1,
41     .fields = (VMStateField[]) {
42         VMSTATE_PTIMER(ptimer, DigicTimerState),
43         VMSTATE_UINT32(control, DigicTimerState),
44         VMSTATE_UINT32(relvalue, DigicTimerState),
45         VMSTATE_END_OF_LIST()
46     }
47 };
48 
49 static void digic_timer_reset(DeviceState *dev)
50 {
51     DigicTimerState *s = DIGIC_TIMER(dev);
52 
53     ptimer_stop(s->ptimer);
54     s->control = 0;
55     s->relvalue = 0;
56 }
57 
58 static uint64_t digic_timer_read(void *opaque, hwaddr offset, unsigned size)
59 {
60     DigicTimerState *s = opaque;
61     uint64_t ret = 0;
62 
63     switch (offset) {
64     case DIGIC_TIMER_CONTROL:
65         ret = s->control;
66         break;
67     case DIGIC_TIMER_RELVALUE:
68         ret = s->relvalue;
69         break;
70     case DIGIC_TIMER_VALUE:
71         ret = ptimer_get_count(s->ptimer) & 0xffff;
72         break;
73     default:
74         qemu_log_mask(LOG_UNIMP,
75                       "digic-timer: read access to unknown register 0x"
76                       TARGET_FMT_plx "\n", offset);
77     }
78 
79     return ret;
80 }
81 
82 static void digic_timer_write(void *opaque, hwaddr offset,
83                               uint64_t value, unsigned size)
84 {
85     DigicTimerState *s = opaque;
86 
87     switch (offset) {
88     case DIGIC_TIMER_CONTROL:
89         if (value & DIGIC_TIMER_CONTROL_RST) {
90             digic_timer_reset((DeviceState *)s);
91             break;
92         }
93 
94         if (value & DIGIC_TIMER_CONTROL_EN) {
95             ptimer_run(s->ptimer, 0);
96         }
97 
98         s->control = (uint32_t)value;
99         break;
100 
101     case DIGIC_TIMER_RELVALUE:
102         s->relvalue = extract32(value, 0, 16);
103         ptimer_set_limit(s->ptimer, s->relvalue, 1);
104         break;
105 
106     case DIGIC_TIMER_VALUE:
107         break;
108 
109     default:
110         qemu_log_mask(LOG_UNIMP,
111                       "digic-timer: read access to unknown register 0x"
112                       TARGET_FMT_plx "\n", offset);
113     }
114 }
115 
116 static const MemoryRegionOps digic_timer_ops = {
117     .read = digic_timer_read,
118     .write = digic_timer_write,
119     .impl = {
120         .min_access_size = 4,
121         .max_access_size = 4,
122     },
123     .endianness = DEVICE_NATIVE_ENDIAN,
124 };
125 
126 static void digic_timer_init(Object *obj)
127 {
128     DigicTimerState *s = DIGIC_TIMER(obj);
129 
130     s->ptimer = ptimer_init(NULL, PTIMER_POLICY_DEFAULT);
131 
132     /*
133      * FIXME: there is no documentation on Digic timer
134      * frequency setup so let it always run at 1 MHz
135      */
136     ptimer_set_freq(s->ptimer, 1 * 1000 * 1000);
137 
138     memory_region_init_io(&s->iomem, OBJECT(s), &digic_timer_ops, s,
139                           TYPE_DIGIC_TIMER, 0x100);
140     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
141 }
142 
143 static void digic_timer_class_init(ObjectClass *klass, void *class_data)
144 {
145     DeviceClass *dc = DEVICE_CLASS(klass);
146 
147     dc->reset = digic_timer_reset;
148     dc->vmsd = &vmstate_digic_timer;
149 }
150 
151 static const TypeInfo digic_timer_info = {
152     .name = TYPE_DIGIC_TIMER,
153     .parent = TYPE_SYS_BUS_DEVICE,
154     .instance_size = sizeof(DigicTimerState),
155     .instance_init = digic_timer_init,
156     .class_init = digic_timer_class_init,
157 };
158 
159 static void digic_timer_register_type(void)
160 {
161     type_register_static(&digic_timer_info);
162 }
163 
164 type_init(digic_timer_register_type)
165