1 /* 2 * ARM CMSDK APB timer emulation 3 * 4 * Copyright (c) 2017 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* This is a model of the "APB timer" which is part of the Cortex-M 13 * System Design Kit (CMSDK) and documented in the Cortex-M System 14 * Design Kit Technical Reference Manual (ARM DDI0479C): 15 * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit 16 * 17 * The hardware has an EXTIN input wire, which can be configured 18 * by the guest to act either as a 'timer enable' (timer does not run 19 * when EXTIN is low), or as a 'timer clock' (timer runs at frequency 20 * of EXTIN clock, not PCLK frequency). We don't model this. 21 * 22 * The documentation is not very clear about the exact behaviour; 23 * we choose to implement that the interrupt is triggered when 24 * the counter goes from 1 to 0, that the counter then holds at 0 25 * for one clock cycle before reloading from the RELOAD register, 26 * and that if the RELOAD register is 0 this does not cause an 27 * interrupt (as there is no further 1->0 transition). 28 */ 29 30 #include "qemu/osdep.h" 31 #include "qemu/log.h" 32 #include "qemu/main-loop.h" 33 #include "qemu/module.h" 34 #include "qapi/error.h" 35 #include "trace.h" 36 #include "hw/sysbus.h" 37 #include "hw/registerfields.h" 38 #include "hw/timer/cmsdk-apb-timer.h" 39 40 REG32(CTRL, 0) 41 FIELD(CTRL, EN, 0, 1) 42 FIELD(CTRL, SELEXTEN, 1, 1) 43 FIELD(CTRL, SELEXTCLK, 2, 1) 44 FIELD(CTRL, IRQEN, 3, 1) 45 REG32(VALUE, 4) 46 REG32(RELOAD, 8) 47 REG32(INTSTATUS, 0xc) 48 FIELD(INTSTATUS, IRQ, 0, 1) 49 REG32(PID4, 0xFD0) 50 REG32(PID5, 0xFD4) 51 REG32(PID6, 0xFD8) 52 REG32(PID7, 0xFDC) 53 REG32(PID0, 0xFE0) 54 REG32(PID1, 0xFE4) 55 REG32(PID2, 0xFE8) 56 REG32(PID3, 0xFEC) 57 REG32(CID0, 0xFF0) 58 REG32(CID1, 0xFF4) 59 REG32(CID2, 0xFF8) 60 REG32(CID3, 0xFFC) 61 62 /* PID/CID values */ 63 static const int timer_id[] = { 64 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */ 65 0x22, 0xb8, 0x1b, 0x00, /* PID0..PID3 */ 66 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ 67 }; 68 69 static void cmsdk_apb_timer_update(CMSDKAPBTIMER *s) 70 { 71 qemu_set_irq(s->timerint, !!(s->intstatus & R_INTSTATUS_IRQ_MASK)); 72 } 73 74 static uint64_t cmsdk_apb_timer_read(void *opaque, hwaddr offset, unsigned size) 75 { 76 CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque); 77 uint64_t r; 78 79 switch (offset) { 80 case A_CTRL: 81 r = s->ctrl; 82 break; 83 case A_VALUE: 84 r = ptimer_get_count(s->timer); 85 break; 86 case A_RELOAD: 87 r = ptimer_get_limit(s->timer); 88 break; 89 case A_INTSTATUS: 90 r = s->intstatus; 91 break; 92 case A_PID4 ... A_CID3: 93 r = timer_id[(offset - A_PID4) / 4]; 94 break; 95 default: 96 qemu_log_mask(LOG_GUEST_ERROR, 97 "CMSDK APB timer read: bad offset %x\n", (int) offset); 98 r = 0; 99 break; 100 } 101 trace_cmsdk_apb_timer_read(offset, r, size); 102 return r; 103 } 104 105 static void cmsdk_apb_timer_write(void *opaque, hwaddr offset, uint64_t value, 106 unsigned size) 107 { 108 CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque); 109 110 trace_cmsdk_apb_timer_write(offset, value, size); 111 112 switch (offset) { 113 case A_CTRL: 114 if (value & 6) { 115 /* Bits [1] and [2] enable using EXTIN as either clock or 116 * an enable line. We don't model this. 117 */ 118 qemu_log_mask(LOG_UNIMP, 119 "CMSDK APB timer: EXTIN input not supported\n"); 120 } 121 s->ctrl = value & 0xf; 122 if (s->ctrl & R_CTRL_EN_MASK) { 123 ptimer_run(s->timer, ptimer_get_limit(s->timer) == 0); 124 } else { 125 ptimer_stop(s->timer); 126 } 127 break; 128 case A_RELOAD: 129 /* Writing to reload also sets the current timer value */ 130 if (!value) { 131 ptimer_stop(s->timer); 132 } 133 ptimer_set_limit(s->timer, value, 1); 134 if (value && (s->ctrl & R_CTRL_EN_MASK)) { 135 /* 136 * Make sure timer is running (it might have stopped if this 137 * was an expired one-shot timer) 138 */ 139 ptimer_run(s->timer, 0); 140 } 141 break; 142 case A_VALUE: 143 if (!value && !ptimer_get_limit(s->timer)) { 144 ptimer_stop(s->timer); 145 } 146 ptimer_set_count(s->timer, value); 147 if (value && (s->ctrl & R_CTRL_EN_MASK)) { 148 ptimer_run(s->timer, ptimer_get_limit(s->timer) == 0); 149 } 150 break; 151 case A_INTSTATUS: 152 /* Just one bit, which is W1C. */ 153 value &= 1; 154 s->intstatus &= ~value; 155 cmsdk_apb_timer_update(s); 156 break; 157 case A_PID4 ... A_CID3: 158 qemu_log_mask(LOG_GUEST_ERROR, 159 "CMSDK APB timer write: write to RO offset 0x%x\n", 160 (int)offset); 161 break; 162 default: 163 qemu_log_mask(LOG_GUEST_ERROR, 164 "CMSDK APB timer write: bad offset 0x%x\n", (int) offset); 165 break; 166 } 167 } 168 169 static const MemoryRegionOps cmsdk_apb_timer_ops = { 170 .read = cmsdk_apb_timer_read, 171 .write = cmsdk_apb_timer_write, 172 .endianness = DEVICE_LITTLE_ENDIAN, 173 }; 174 175 static void cmsdk_apb_timer_tick(void *opaque) 176 { 177 CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque); 178 179 if (s->ctrl & R_CTRL_IRQEN_MASK) { 180 s->intstatus |= R_INTSTATUS_IRQ_MASK; 181 cmsdk_apb_timer_update(s); 182 } 183 } 184 185 static void cmsdk_apb_timer_reset(DeviceState *dev) 186 { 187 CMSDKAPBTIMER *s = CMSDK_APB_TIMER(dev); 188 189 trace_cmsdk_apb_timer_reset(); 190 s->ctrl = 0; 191 s->intstatus = 0; 192 ptimer_stop(s->timer); 193 /* Set the limit and the count */ 194 ptimer_set_limit(s->timer, 0, 1); 195 } 196 197 static void cmsdk_apb_timer_init(Object *obj) 198 { 199 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 200 CMSDKAPBTIMER *s = CMSDK_APB_TIMER(obj); 201 202 memory_region_init_io(&s->iomem, obj, &cmsdk_apb_timer_ops, 203 s, "cmsdk-apb-timer", 0x1000); 204 sysbus_init_mmio(sbd, &s->iomem); 205 sysbus_init_irq(sbd, &s->timerint); 206 } 207 208 static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp) 209 { 210 CMSDKAPBTIMER *s = CMSDK_APB_TIMER(dev); 211 QEMUBH *bh; 212 213 if (s->pclk_frq == 0) { 214 error_setg(errp, "CMSDK APB timer: pclk-frq property must be set"); 215 return; 216 } 217 218 bh = qemu_bh_new(cmsdk_apb_timer_tick, s); 219 s->timer = ptimer_init(bh, 220 PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | 221 PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT | 222 PTIMER_POLICY_NO_IMMEDIATE_RELOAD | 223 PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); 224 225 ptimer_set_freq(s->timer, s->pclk_frq); 226 } 227 228 static const VMStateDescription cmsdk_apb_timer_vmstate = { 229 .name = "cmsdk-apb-timer", 230 .version_id = 1, 231 .minimum_version_id = 1, 232 .fields = (VMStateField[]) { 233 VMSTATE_PTIMER(timer, CMSDKAPBTIMER), 234 VMSTATE_UINT32(ctrl, CMSDKAPBTIMER), 235 VMSTATE_UINT32(value, CMSDKAPBTIMER), 236 VMSTATE_UINT32(reload, CMSDKAPBTIMER), 237 VMSTATE_UINT32(intstatus, CMSDKAPBTIMER), 238 VMSTATE_END_OF_LIST() 239 } 240 }; 241 242 static Property cmsdk_apb_timer_properties[] = { 243 DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBTIMER, pclk_frq, 0), 244 DEFINE_PROP_END_OF_LIST(), 245 }; 246 247 static void cmsdk_apb_timer_class_init(ObjectClass *klass, void *data) 248 { 249 DeviceClass *dc = DEVICE_CLASS(klass); 250 251 dc->realize = cmsdk_apb_timer_realize; 252 dc->vmsd = &cmsdk_apb_timer_vmstate; 253 dc->reset = cmsdk_apb_timer_reset; 254 dc->props = cmsdk_apb_timer_properties; 255 } 256 257 static const TypeInfo cmsdk_apb_timer_info = { 258 .name = TYPE_CMSDK_APB_TIMER, 259 .parent = TYPE_SYS_BUS_DEVICE, 260 .instance_size = sizeof(CMSDKAPBTIMER), 261 .instance_init = cmsdk_apb_timer_init, 262 .class_init = cmsdk_apb_timer_class_init, 263 }; 264 265 static void cmsdk_apb_timer_register_types(void) 266 { 267 type_register_static(&cmsdk_apb_timer_info); 268 } 269 270 type_init(cmsdk_apb_timer_register_types); 271