1 /* 2 * ARM CMSDK APB timer emulation 3 * 4 * Copyright (c) 2017 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* This is a model of the "APB timer" which is part of the Cortex-M 13 * System Design Kit (CMSDK) and documented in the Cortex-M System 14 * Design Kit Technical Reference Manual (ARM DDI0479C): 15 * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit 16 * 17 * The hardware has an EXTIN input wire, which can be configured 18 * by the guest to act either as a 'timer enable' (timer does not run 19 * when EXTIN is low), or as a 'timer clock' (timer runs at frequency 20 * of EXTIN clock, not PCLK frequency). We don't model this. 21 * 22 * The documentation is not very clear about the exact behaviour; 23 * we choose to implement that the interrupt is triggered when 24 * the counter goes from 1 to 0, that the counter then holds at 0 25 * for one clock cycle before reloading from the RELOAD register, 26 * and that if the RELOAD register is 0 this does not cause an 27 * interrupt (as there is no further 1->0 transition). 28 */ 29 30 #include "qemu/osdep.h" 31 #include "qemu/log.h" 32 #include "qemu/main-loop.h" 33 #include "qemu/module.h" 34 #include "qapi/error.h" 35 #include "trace.h" 36 #include "hw/sysbus.h" 37 #include "hw/irq.h" 38 #include "hw/registerfields.h" 39 #include "hw/timer/cmsdk-apb-timer.h" 40 41 REG32(CTRL, 0) 42 FIELD(CTRL, EN, 0, 1) 43 FIELD(CTRL, SELEXTEN, 1, 1) 44 FIELD(CTRL, SELEXTCLK, 2, 1) 45 FIELD(CTRL, IRQEN, 3, 1) 46 REG32(VALUE, 4) 47 REG32(RELOAD, 8) 48 REG32(INTSTATUS, 0xc) 49 FIELD(INTSTATUS, IRQ, 0, 1) 50 REG32(PID4, 0xFD0) 51 REG32(PID5, 0xFD4) 52 REG32(PID6, 0xFD8) 53 REG32(PID7, 0xFDC) 54 REG32(PID0, 0xFE0) 55 REG32(PID1, 0xFE4) 56 REG32(PID2, 0xFE8) 57 REG32(PID3, 0xFEC) 58 REG32(CID0, 0xFF0) 59 REG32(CID1, 0xFF4) 60 REG32(CID2, 0xFF8) 61 REG32(CID3, 0xFFC) 62 63 /* PID/CID values */ 64 static const int timer_id[] = { 65 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */ 66 0x22, 0xb8, 0x1b, 0x00, /* PID0..PID3 */ 67 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ 68 }; 69 70 static void cmsdk_apb_timer_update(CMSDKAPBTIMER *s) 71 { 72 qemu_set_irq(s->timerint, !!(s->intstatus & R_INTSTATUS_IRQ_MASK)); 73 } 74 75 static uint64_t cmsdk_apb_timer_read(void *opaque, hwaddr offset, unsigned size) 76 { 77 CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque); 78 uint64_t r; 79 80 switch (offset) { 81 case A_CTRL: 82 r = s->ctrl; 83 break; 84 case A_VALUE: 85 r = ptimer_get_count(s->timer); 86 break; 87 case A_RELOAD: 88 r = ptimer_get_limit(s->timer); 89 break; 90 case A_INTSTATUS: 91 r = s->intstatus; 92 break; 93 case A_PID4 ... A_CID3: 94 r = timer_id[(offset - A_PID4) / 4]; 95 break; 96 default: 97 qemu_log_mask(LOG_GUEST_ERROR, 98 "CMSDK APB timer read: bad offset %x\n", (int) offset); 99 r = 0; 100 break; 101 } 102 trace_cmsdk_apb_timer_read(offset, r, size); 103 return r; 104 } 105 106 static void cmsdk_apb_timer_write(void *opaque, hwaddr offset, uint64_t value, 107 unsigned size) 108 { 109 CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque); 110 111 trace_cmsdk_apb_timer_write(offset, value, size); 112 113 switch (offset) { 114 case A_CTRL: 115 if (value & 6) { 116 /* Bits [1] and [2] enable using EXTIN as either clock or 117 * an enable line. We don't model this. 118 */ 119 qemu_log_mask(LOG_UNIMP, 120 "CMSDK APB timer: EXTIN input not supported\n"); 121 } 122 s->ctrl = value & 0xf; 123 if (s->ctrl & R_CTRL_EN_MASK) { 124 ptimer_run(s->timer, ptimer_get_limit(s->timer) == 0); 125 } else { 126 ptimer_stop(s->timer); 127 } 128 break; 129 case A_RELOAD: 130 /* Writing to reload also sets the current timer value */ 131 if (!value) { 132 ptimer_stop(s->timer); 133 } 134 ptimer_set_limit(s->timer, value, 1); 135 if (value && (s->ctrl & R_CTRL_EN_MASK)) { 136 /* 137 * Make sure timer is running (it might have stopped if this 138 * was an expired one-shot timer) 139 */ 140 ptimer_run(s->timer, 0); 141 } 142 break; 143 case A_VALUE: 144 if (!value && !ptimer_get_limit(s->timer)) { 145 ptimer_stop(s->timer); 146 } 147 ptimer_set_count(s->timer, value); 148 if (value && (s->ctrl & R_CTRL_EN_MASK)) { 149 ptimer_run(s->timer, ptimer_get_limit(s->timer) == 0); 150 } 151 break; 152 case A_INTSTATUS: 153 /* Just one bit, which is W1C. */ 154 value &= 1; 155 s->intstatus &= ~value; 156 cmsdk_apb_timer_update(s); 157 break; 158 case A_PID4 ... A_CID3: 159 qemu_log_mask(LOG_GUEST_ERROR, 160 "CMSDK APB timer write: write to RO offset 0x%x\n", 161 (int)offset); 162 break; 163 default: 164 qemu_log_mask(LOG_GUEST_ERROR, 165 "CMSDK APB timer write: bad offset 0x%x\n", (int) offset); 166 break; 167 } 168 } 169 170 static const MemoryRegionOps cmsdk_apb_timer_ops = { 171 .read = cmsdk_apb_timer_read, 172 .write = cmsdk_apb_timer_write, 173 .endianness = DEVICE_LITTLE_ENDIAN, 174 }; 175 176 static void cmsdk_apb_timer_tick(void *opaque) 177 { 178 CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque); 179 180 if (s->ctrl & R_CTRL_IRQEN_MASK) { 181 s->intstatus |= R_INTSTATUS_IRQ_MASK; 182 cmsdk_apb_timer_update(s); 183 } 184 } 185 186 static void cmsdk_apb_timer_reset(DeviceState *dev) 187 { 188 CMSDKAPBTIMER *s = CMSDK_APB_TIMER(dev); 189 190 trace_cmsdk_apb_timer_reset(); 191 s->ctrl = 0; 192 s->intstatus = 0; 193 ptimer_stop(s->timer); 194 /* Set the limit and the count */ 195 ptimer_set_limit(s->timer, 0, 1); 196 } 197 198 static void cmsdk_apb_timer_init(Object *obj) 199 { 200 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 201 CMSDKAPBTIMER *s = CMSDK_APB_TIMER(obj); 202 203 memory_region_init_io(&s->iomem, obj, &cmsdk_apb_timer_ops, 204 s, "cmsdk-apb-timer", 0x1000); 205 sysbus_init_mmio(sbd, &s->iomem); 206 sysbus_init_irq(sbd, &s->timerint); 207 } 208 209 static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp) 210 { 211 CMSDKAPBTIMER *s = CMSDK_APB_TIMER(dev); 212 QEMUBH *bh; 213 214 if (s->pclk_frq == 0) { 215 error_setg(errp, "CMSDK APB timer: pclk-frq property must be set"); 216 return; 217 } 218 219 bh = qemu_bh_new(cmsdk_apb_timer_tick, s); 220 s->timer = ptimer_init(bh, 221 PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | 222 PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT | 223 PTIMER_POLICY_NO_IMMEDIATE_RELOAD | 224 PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); 225 226 ptimer_set_freq(s->timer, s->pclk_frq); 227 } 228 229 static const VMStateDescription cmsdk_apb_timer_vmstate = { 230 .name = "cmsdk-apb-timer", 231 .version_id = 1, 232 .minimum_version_id = 1, 233 .fields = (VMStateField[]) { 234 VMSTATE_PTIMER(timer, CMSDKAPBTIMER), 235 VMSTATE_UINT32(ctrl, CMSDKAPBTIMER), 236 VMSTATE_UINT32(value, CMSDKAPBTIMER), 237 VMSTATE_UINT32(reload, CMSDKAPBTIMER), 238 VMSTATE_UINT32(intstatus, CMSDKAPBTIMER), 239 VMSTATE_END_OF_LIST() 240 } 241 }; 242 243 static Property cmsdk_apb_timer_properties[] = { 244 DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBTIMER, pclk_frq, 0), 245 DEFINE_PROP_END_OF_LIST(), 246 }; 247 248 static void cmsdk_apb_timer_class_init(ObjectClass *klass, void *data) 249 { 250 DeviceClass *dc = DEVICE_CLASS(klass); 251 252 dc->realize = cmsdk_apb_timer_realize; 253 dc->vmsd = &cmsdk_apb_timer_vmstate; 254 dc->reset = cmsdk_apb_timer_reset; 255 dc->props = cmsdk_apb_timer_properties; 256 } 257 258 static const TypeInfo cmsdk_apb_timer_info = { 259 .name = TYPE_CMSDK_APB_TIMER, 260 .parent = TYPE_SYS_BUS_DEVICE, 261 .instance_size = sizeof(CMSDKAPBTIMER), 262 .instance_init = cmsdk_apb_timer_init, 263 .class_init = cmsdk_apb_timer_class_init, 264 }; 265 266 static void cmsdk_apb_timer_register_types(void) 267 { 268 type_register_static(&cmsdk_apb_timer_info); 269 } 270 271 type_init(cmsdk_apb_timer_register_types); 272