1 /* 2 * ARM CMSDK APB timer emulation 3 * 4 * Copyright (c) 2017 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* This is a model of the "APB timer" which is part of the Cortex-M 13 * System Design Kit (CMSDK) and documented in the Cortex-M System 14 * Design Kit Technical Reference Manual (ARM DDI0479C): 15 * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit 16 * 17 * The hardware has an EXTIN input wire, which can be configured 18 * by the guest to act either as a 'timer enable' (timer does not run 19 * when EXTIN is low), or as a 'timer clock' (timer runs at frequency 20 * of EXTIN clock, not PCLK frequency). We don't model this. 21 * 22 * The documentation is not very clear about the exact behaviour; 23 * we choose to implement that the interrupt is triggered when 24 * the counter goes from 1 to 0, that the counter then holds at 0 25 * for one clock cycle before reloading from the RELOAD register, 26 * and that if the RELOAD register is 0 this does not cause an 27 * interrupt (as there is no further 1->0 transition). 28 */ 29 30 #include "qemu/osdep.h" 31 #include "qemu/log.h" 32 #include "qemu/main-loop.h" 33 #include "qapi/error.h" 34 #include "trace.h" 35 #include "hw/sysbus.h" 36 #include "hw/registerfields.h" 37 #include "hw/timer/cmsdk-apb-timer.h" 38 39 REG32(CTRL, 0) 40 FIELD(CTRL, EN, 0, 1) 41 FIELD(CTRL, SELEXTEN, 1, 1) 42 FIELD(CTRL, SELEXTCLK, 2, 1) 43 FIELD(CTRL, IRQEN, 3, 1) 44 REG32(VALUE, 4) 45 REG32(RELOAD, 8) 46 REG32(INTSTATUS, 0xc) 47 FIELD(INTSTATUS, IRQ, 0, 1) 48 REG32(PID4, 0xFD0) 49 REG32(PID5, 0xFD4) 50 REG32(PID6, 0xFD8) 51 REG32(PID7, 0xFDC) 52 REG32(PID0, 0xFE0) 53 REG32(PID1, 0xFE4) 54 REG32(PID2, 0xFE8) 55 REG32(PID3, 0xFEC) 56 REG32(CID0, 0xFF0) 57 REG32(CID1, 0xFF4) 58 REG32(CID2, 0xFF8) 59 REG32(CID3, 0xFFC) 60 61 /* PID/CID values */ 62 static const int timer_id[] = { 63 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */ 64 0x22, 0xb8, 0x1b, 0x00, /* PID0..PID3 */ 65 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ 66 }; 67 68 static void cmsdk_apb_timer_update(CMSDKAPBTIMER *s) 69 { 70 qemu_set_irq(s->timerint, !!(s->intstatus & R_INTSTATUS_IRQ_MASK)); 71 } 72 73 static uint64_t cmsdk_apb_timer_read(void *opaque, hwaddr offset, unsigned size) 74 { 75 CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque); 76 uint64_t r; 77 78 switch (offset) { 79 case A_CTRL: 80 r = s->ctrl; 81 break; 82 case A_VALUE: 83 r = ptimer_get_count(s->timer); 84 break; 85 case A_RELOAD: 86 r = ptimer_get_limit(s->timer); 87 break; 88 case A_INTSTATUS: 89 r = s->intstatus; 90 break; 91 case A_PID4 ... A_CID3: 92 r = timer_id[(offset - A_PID4) / 4]; 93 break; 94 default: 95 qemu_log_mask(LOG_GUEST_ERROR, 96 "CMSDK APB timer read: bad offset %x\n", (int) offset); 97 r = 0; 98 break; 99 } 100 trace_cmsdk_apb_timer_read(offset, r, size); 101 return r; 102 } 103 104 static void cmsdk_apb_timer_write(void *opaque, hwaddr offset, uint64_t value, 105 unsigned size) 106 { 107 CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque); 108 109 trace_cmsdk_apb_timer_write(offset, value, size); 110 111 switch (offset) { 112 case A_CTRL: 113 if (value & 6) { 114 /* Bits [1] and [2] enable using EXTIN as either clock or 115 * an enable line. We don't model this. 116 */ 117 qemu_log_mask(LOG_UNIMP, 118 "CMSDK APB timer: EXTIN input not supported\n"); 119 } 120 s->ctrl = value & 0xf; 121 if (s->ctrl & R_CTRL_EN_MASK) { 122 ptimer_run(s->timer, ptimer_get_limit(s->timer) == 0); 123 } else { 124 ptimer_stop(s->timer); 125 } 126 break; 127 case A_RELOAD: 128 /* Writing to reload also sets the current timer value */ 129 if (!value) { 130 ptimer_stop(s->timer); 131 } 132 ptimer_set_limit(s->timer, value, 1); 133 if (value && (s->ctrl & R_CTRL_EN_MASK)) { 134 /* 135 * Make sure timer is running (it might have stopped if this 136 * was an expired one-shot timer) 137 */ 138 ptimer_run(s->timer, 0); 139 } 140 break; 141 case A_VALUE: 142 if (!value && !ptimer_get_limit(s->timer)) { 143 ptimer_stop(s->timer); 144 } 145 ptimer_set_count(s->timer, value); 146 if (value && (s->ctrl & R_CTRL_EN_MASK)) { 147 ptimer_run(s->timer, ptimer_get_limit(s->timer) == 0); 148 } 149 break; 150 case A_INTSTATUS: 151 /* Just one bit, which is W1C. */ 152 value &= 1; 153 s->intstatus &= ~value; 154 cmsdk_apb_timer_update(s); 155 break; 156 case A_PID4 ... A_CID3: 157 qemu_log_mask(LOG_GUEST_ERROR, 158 "CMSDK APB timer write: write to RO offset 0x%x\n", 159 (int)offset); 160 break; 161 default: 162 qemu_log_mask(LOG_GUEST_ERROR, 163 "CMSDK APB timer write: bad offset 0x%x\n", (int) offset); 164 break; 165 } 166 } 167 168 static const MemoryRegionOps cmsdk_apb_timer_ops = { 169 .read = cmsdk_apb_timer_read, 170 .write = cmsdk_apb_timer_write, 171 .endianness = DEVICE_LITTLE_ENDIAN, 172 }; 173 174 static void cmsdk_apb_timer_tick(void *opaque) 175 { 176 CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque); 177 178 if (s->ctrl & R_CTRL_IRQEN_MASK) { 179 s->intstatus |= R_INTSTATUS_IRQ_MASK; 180 cmsdk_apb_timer_update(s); 181 } 182 } 183 184 static void cmsdk_apb_timer_reset(DeviceState *dev) 185 { 186 CMSDKAPBTIMER *s = CMSDK_APB_TIMER(dev); 187 188 trace_cmsdk_apb_timer_reset(); 189 s->ctrl = 0; 190 s->intstatus = 0; 191 ptimer_stop(s->timer); 192 /* Set the limit and the count */ 193 ptimer_set_limit(s->timer, 0, 1); 194 } 195 196 static void cmsdk_apb_timer_init(Object *obj) 197 { 198 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 199 CMSDKAPBTIMER *s = CMSDK_APB_TIMER(obj); 200 201 memory_region_init_io(&s->iomem, obj, &cmsdk_apb_timer_ops, 202 s, "cmsdk-apb-timer", 0x1000); 203 sysbus_init_mmio(sbd, &s->iomem); 204 sysbus_init_irq(sbd, &s->timerint); 205 } 206 207 static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp) 208 { 209 CMSDKAPBTIMER *s = CMSDK_APB_TIMER(dev); 210 QEMUBH *bh; 211 212 if (s->pclk_frq == 0) { 213 error_setg(errp, "CMSDK APB timer: pclk-frq property must be set"); 214 return; 215 } 216 217 bh = qemu_bh_new(cmsdk_apb_timer_tick, s); 218 s->timer = ptimer_init(bh, 219 PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | 220 PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT | 221 PTIMER_POLICY_NO_IMMEDIATE_RELOAD | 222 PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); 223 224 ptimer_set_freq(s->timer, s->pclk_frq); 225 } 226 227 static const VMStateDescription cmsdk_apb_timer_vmstate = { 228 .name = "cmsdk-apb-timer", 229 .version_id = 1, 230 .minimum_version_id = 1, 231 .fields = (VMStateField[]) { 232 VMSTATE_PTIMER(timer, CMSDKAPBTIMER), 233 VMSTATE_UINT32(ctrl, CMSDKAPBTIMER), 234 VMSTATE_UINT32(value, CMSDKAPBTIMER), 235 VMSTATE_UINT32(reload, CMSDKAPBTIMER), 236 VMSTATE_UINT32(intstatus, CMSDKAPBTIMER), 237 VMSTATE_END_OF_LIST() 238 } 239 }; 240 241 static Property cmsdk_apb_timer_properties[] = { 242 DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBTIMER, pclk_frq, 0), 243 DEFINE_PROP_END_OF_LIST(), 244 }; 245 246 static void cmsdk_apb_timer_class_init(ObjectClass *klass, void *data) 247 { 248 DeviceClass *dc = DEVICE_CLASS(klass); 249 250 dc->realize = cmsdk_apb_timer_realize; 251 dc->vmsd = &cmsdk_apb_timer_vmstate; 252 dc->reset = cmsdk_apb_timer_reset; 253 dc->props = cmsdk_apb_timer_properties; 254 } 255 256 static const TypeInfo cmsdk_apb_timer_info = { 257 .name = TYPE_CMSDK_APB_TIMER, 258 .parent = TYPE_SYS_BUS_DEVICE, 259 .instance_size = sizeof(CMSDKAPBTIMER), 260 .instance_init = cmsdk_apb_timer_init, 261 .class_init = cmsdk_apb_timer_class_init, 262 }; 263 264 static void cmsdk_apb_timer_register_types(void) 265 { 266 type_register_static(&cmsdk_apb_timer_info); 267 } 268 269 type_init(cmsdk_apb_timer_register_types); 270