1 /* 2 * Xilinx Zynq cadence TTC model 3 * 4 * Copyright (c) 2011 Xilinx Inc. 5 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com) 6 * Copyright (c) 2012 PetaLogix Pty Ltd. 7 * Written By Haibing Ma 8 * M. Habib 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License 12 * as published by the Free Software Foundation; either version 13 * 2 of the License, or (at your option) any later version. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "hw/sysbus.h" 21 #include "qemu/module.h" 22 #include "qemu/timer.h" 23 24 #ifdef CADENCE_TTC_ERR_DEBUG 25 #define DB_PRINT(...) do { \ 26 fprintf(stderr, ": %s: ", __func__); \ 27 fprintf(stderr, ## __VA_ARGS__); \ 28 } while (0) 29 #else 30 #define DB_PRINT(...) 31 #endif 32 33 #define COUNTER_INTR_IV 0x00000001 34 #define COUNTER_INTR_M1 0x00000002 35 #define COUNTER_INTR_M2 0x00000004 36 #define COUNTER_INTR_M3 0x00000008 37 #define COUNTER_INTR_OV 0x00000010 38 #define COUNTER_INTR_EV 0x00000020 39 40 #define COUNTER_CTRL_DIS 0x00000001 41 #define COUNTER_CTRL_INT 0x00000002 42 #define COUNTER_CTRL_DEC 0x00000004 43 #define COUNTER_CTRL_MATCH 0x00000008 44 #define COUNTER_CTRL_RST 0x00000010 45 46 #define CLOCK_CTRL_PS_EN 0x00000001 47 #define CLOCK_CTRL_PS_V 0x0000001e 48 49 typedef struct { 50 QEMUTimer *timer; 51 int freq; 52 53 uint32_t reg_clock; 54 uint32_t reg_count; 55 uint32_t reg_value; 56 uint16_t reg_interval; 57 uint16_t reg_match[3]; 58 uint32_t reg_intr; 59 uint32_t reg_intr_en; 60 uint32_t reg_event_ctrl; 61 uint32_t reg_event; 62 63 uint64_t cpu_time; 64 unsigned int cpu_time_valid; 65 66 qemu_irq irq; 67 } CadenceTimerState; 68 69 #define TYPE_CADENCE_TTC "cadence_ttc" 70 #define CADENCE_TTC(obj) \ 71 OBJECT_CHECK(CadenceTTCState, (obj), TYPE_CADENCE_TTC) 72 73 typedef struct CadenceTTCState { 74 SysBusDevice parent_obj; 75 76 MemoryRegion iomem; 77 CadenceTimerState timer[3]; 78 } CadenceTTCState; 79 80 static void cadence_timer_update(CadenceTimerState *s) 81 { 82 qemu_set_irq(s->irq, !!(s->reg_intr & s->reg_intr_en)); 83 } 84 85 static CadenceTimerState *cadence_timer_from_addr(void *opaque, 86 hwaddr offset) 87 { 88 unsigned int index; 89 CadenceTTCState *s = (CadenceTTCState *)opaque; 90 91 index = (offset >> 2) % 3; 92 93 return &s->timer[index]; 94 } 95 96 static uint64_t cadence_timer_get_ns(CadenceTimerState *s, uint64_t timer_steps) 97 { 98 /* timer_steps has max value of 0x100000000. double check it 99 * (or overflow can happen below) */ 100 assert(timer_steps <= 1ULL << 32); 101 102 uint64_t r = timer_steps * 1000000000ULL; 103 if (s->reg_clock & CLOCK_CTRL_PS_EN) { 104 r >>= 16 - (((s->reg_clock & CLOCK_CTRL_PS_V) >> 1) + 1); 105 } else { 106 r >>= 16; 107 } 108 r /= (uint64_t)s->freq; 109 return r; 110 } 111 112 static uint64_t cadence_timer_get_steps(CadenceTimerState *s, uint64_t ns) 113 { 114 uint64_t to_divide = 1000000000ULL; 115 116 uint64_t r = ns; 117 /* for very large intervals (> 8s) do some division first to stop 118 * overflow (costs some prescision) */ 119 while (r >= 8ULL << 30 && to_divide > 1) { 120 r /= 1000; 121 to_divide /= 1000; 122 } 123 r <<= 16; 124 /* keep early-dividing as needed */ 125 while (r >= 8ULL << 30 && to_divide > 1) { 126 r /= 1000; 127 to_divide /= 1000; 128 } 129 r *= (uint64_t)s->freq; 130 if (s->reg_clock & CLOCK_CTRL_PS_EN) { 131 r /= 1 << (((s->reg_clock & CLOCK_CTRL_PS_V) >> 1) + 1); 132 } 133 134 r /= to_divide; 135 return r; 136 } 137 138 /* determine if x is in between a and b, exclusive of a, inclusive of b */ 139 140 static inline int64_t is_between(int64_t x, int64_t a, int64_t b) 141 { 142 if (a < b) { 143 return x > a && x <= b; 144 } 145 return x < a && x >= b; 146 } 147 148 static void cadence_timer_run(CadenceTimerState *s) 149 { 150 int i; 151 int64_t event_interval, next_value; 152 153 assert(s->cpu_time_valid); /* cadence_timer_sync must be called first */ 154 155 if (s->reg_count & COUNTER_CTRL_DIS) { 156 s->cpu_time_valid = 0; 157 return; 158 } 159 160 { /* figure out what's going to happen next (rollover or match) */ 161 int64_t interval = (uint64_t)((s->reg_count & COUNTER_CTRL_INT) ? 162 (int64_t)s->reg_interval + 1 : 0x10000ULL) << 16; 163 next_value = (s->reg_count & COUNTER_CTRL_DEC) ? -1ULL : interval; 164 for (i = 0; i < 3; ++i) { 165 int64_t cand = (uint64_t)s->reg_match[i] << 16; 166 if (is_between(cand, (uint64_t)s->reg_value, next_value)) { 167 next_value = cand; 168 } 169 } 170 } 171 DB_PRINT("next timer event value: %09llx\n", 172 (unsigned long long)next_value); 173 174 event_interval = next_value - (int64_t)s->reg_value; 175 event_interval = (event_interval < 0) ? -event_interval : event_interval; 176 177 timer_mod(s->timer, s->cpu_time + 178 cadence_timer_get_ns(s, event_interval)); 179 } 180 181 static void cadence_timer_sync(CadenceTimerState *s) 182 { 183 int i; 184 int64_t r, x; 185 int64_t interval = ((s->reg_count & COUNTER_CTRL_INT) ? 186 (int64_t)s->reg_interval + 1 : 0x10000ULL) << 16; 187 uint64_t old_time = s->cpu_time; 188 189 s->cpu_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 190 DB_PRINT("cpu time: %lld ns\n", (long long)old_time); 191 192 if (!s->cpu_time_valid || old_time == s->cpu_time) { 193 s->cpu_time_valid = 1; 194 return; 195 } 196 197 r = (int64_t)cadence_timer_get_steps(s, s->cpu_time - old_time); 198 x = (int64_t)s->reg_value + ((s->reg_count & COUNTER_CTRL_DEC) ? -r : r); 199 200 for (i = 0; i < 3; ++i) { 201 int64_t m = (int64_t)s->reg_match[i] << 16; 202 if (m > interval) { 203 continue; 204 } 205 /* check to see if match event has occurred. check m +/- interval 206 * to account for match events in wrap around cases */ 207 if (is_between(m, s->reg_value, x) || 208 is_between(m + interval, s->reg_value, x) || 209 is_between(m - interval, s->reg_value, x)) { 210 s->reg_intr |= (2 << i); 211 } 212 } 213 if ((x < 0) || (x >= interval)) { 214 s->reg_intr |= (s->reg_count & COUNTER_CTRL_INT) ? 215 COUNTER_INTR_IV : COUNTER_INTR_OV; 216 } 217 while (x < 0) { 218 x += interval; 219 } 220 s->reg_value = (uint32_t)(x % interval); 221 cadence_timer_update(s); 222 } 223 224 static void cadence_timer_tick(void *opaque) 225 { 226 CadenceTimerState *s = opaque; 227 228 DB_PRINT("\n"); 229 cadence_timer_sync(s); 230 cadence_timer_run(s); 231 } 232 233 static uint32_t cadence_ttc_read_imp(void *opaque, hwaddr offset) 234 { 235 CadenceTimerState *s = cadence_timer_from_addr(opaque, offset); 236 uint32_t value; 237 238 cadence_timer_sync(s); 239 cadence_timer_run(s); 240 241 switch (offset) { 242 case 0x00: /* clock control */ 243 case 0x04: 244 case 0x08: 245 return s->reg_clock; 246 247 case 0x0c: /* counter control */ 248 case 0x10: 249 case 0x14: 250 return s->reg_count; 251 252 case 0x18: /* counter value */ 253 case 0x1c: 254 case 0x20: 255 return (uint16_t)(s->reg_value >> 16); 256 257 case 0x24: /* reg_interval counter */ 258 case 0x28: 259 case 0x2c: 260 return s->reg_interval; 261 262 case 0x30: /* match 1 counter */ 263 case 0x34: 264 case 0x38: 265 return s->reg_match[0]; 266 267 case 0x3c: /* match 2 counter */ 268 case 0x40: 269 case 0x44: 270 return s->reg_match[1]; 271 272 case 0x48: /* match 3 counter */ 273 case 0x4c: 274 case 0x50: 275 return s->reg_match[2]; 276 277 case 0x54: /* interrupt register */ 278 case 0x58: 279 case 0x5c: 280 /* cleared after read */ 281 value = s->reg_intr; 282 s->reg_intr = 0; 283 cadence_timer_update(s); 284 return value; 285 286 case 0x60: /* interrupt enable */ 287 case 0x64: 288 case 0x68: 289 return s->reg_intr_en; 290 291 case 0x6c: 292 case 0x70: 293 case 0x74: 294 return s->reg_event_ctrl; 295 296 case 0x78: 297 case 0x7c: 298 case 0x80: 299 return s->reg_event; 300 301 default: 302 return 0; 303 } 304 } 305 306 static uint64_t cadence_ttc_read(void *opaque, hwaddr offset, 307 unsigned size) 308 { 309 uint32_t ret = cadence_ttc_read_imp(opaque, offset); 310 311 DB_PRINT("addr: %08x data: %08x\n", (unsigned)offset, (unsigned)ret); 312 return ret; 313 } 314 315 static void cadence_ttc_write(void *opaque, hwaddr offset, 316 uint64_t value, unsigned size) 317 { 318 CadenceTimerState *s = cadence_timer_from_addr(opaque, offset); 319 320 DB_PRINT("addr: %08x data %08x\n", (unsigned)offset, (unsigned)value); 321 322 cadence_timer_sync(s); 323 324 switch (offset) { 325 case 0x00: /* clock control */ 326 case 0x04: 327 case 0x08: 328 s->reg_clock = value & 0x3F; 329 break; 330 331 case 0x0c: /* counter control */ 332 case 0x10: 333 case 0x14: 334 if (value & COUNTER_CTRL_RST) { 335 s->reg_value = 0; 336 } 337 s->reg_count = value & 0x3f & ~COUNTER_CTRL_RST; 338 break; 339 340 case 0x24: /* interval register */ 341 case 0x28: 342 case 0x2c: 343 s->reg_interval = value & 0xffff; 344 break; 345 346 case 0x30: /* match register */ 347 case 0x34: 348 case 0x38: 349 s->reg_match[0] = value & 0xffff; 350 break; 351 352 case 0x3c: /* match register */ 353 case 0x40: 354 case 0x44: 355 s->reg_match[1] = value & 0xffff; 356 break; 357 358 case 0x48: /* match register */ 359 case 0x4c: 360 case 0x50: 361 s->reg_match[2] = value & 0xffff; 362 break; 363 364 case 0x54: /* interrupt register */ 365 case 0x58: 366 case 0x5c: 367 break; 368 369 case 0x60: /* interrupt enable */ 370 case 0x64: 371 case 0x68: 372 s->reg_intr_en = value & 0x3f; 373 break; 374 375 case 0x6c: /* event control */ 376 case 0x70: 377 case 0x74: 378 s->reg_event_ctrl = value & 0x07; 379 break; 380 381 default: 382 return; 383 } 384 385 cadence_timer_run(s); 386 cadence_timer_update(s); 387 } 388 389 static const MemoryRegionOps cadence_ttc_ops = { 390 .read = cadence_ttc_read, 391 .write = cadence_ttc_write, 392 .endianness = DEVICE_NATIVE_ENDIAN, 393 }; 394 395 static void cadence_timer_reset(CadenceTimerState *s) 396 { 397 s->reg_count = 0x21; 398 } 399 400 static void cadence_timer_init(uint32_t freq, CadenceTimerState *s) 401 { 402 memset(s, 0, sizeof(CadenceTimerState)); 403 s->freq = freq; 404 405 cadence_timer_reset(s); 406 407 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cadence_timer_tick, s); 408 } 409 410 static void cadence_ttc_init(Object *obj) 411 { 412 CadenceTTCState *s = CADENCE_TTC(obj); 413 int i; 414 415 for (i = 0; i < 3; ++i) { 416 cadence_timer_init(133000000, &s->timer[i]); 417 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->timer[i].irq); 418 } 419 420 memory_region_init_io(&s->iomem, obj, &cadence_ttc_ops, s, 421 "timer", 0x1000); 422 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); 423 } 424 425 static int cadence_timer_pre_save(void *opaque) 426 { 427 cadence_timer_sync((CadenceTimerState *)opaque); 428 429 return 0; 430 } 431 432 static int cadence_timer_post_load(void *opaque, int version_id) 433 { 434 CadenceTimerState *s = opaque; 435 436 s->cpu_time_valid = 0; 437 cadence_timer_sync(s); 438 cadence_timer_run(s); 439 cadence_timer_update(s); 440 return 0; 441 } 442 443 static const VMStateDescription vmstate_cadence_timer = { 444 .name = "cadence_timer", 445 .version_id = 1, 446 .minimum_version_id = 1, 447 .pre_save = cadence_timer_pre_save, 448 .post_load = cadence_timer_post_load, 449 .fields = (VMStateField[]) { 450 VMSTATE_UINT32(reg_clock, CadenceTimerState), 451 VMSTATE_UINT32(reg_count, CadenceTimerState), 452 VMSTATE_UINT32(reg_value, CadenceTimerState), 453 VMSTATE_UINT16(reg_interval, CadenceTimerState), 454 VMSTATE_UINT16_ARRAY(reg_match, CadenceTimerState, 3), 455 VMSTATE_UINT32(reg_intr, CadenceTimerState), 456 VMSTATE_UINT32(reg_intr_en, CadenceTimerState), 457 VMSTATE_UINT32(reg_event_ctrl, CadenceTimerState), 458 VMSTATE_UINT32(reg_event, CadenceTimerState), 459 VMSTATE_END_OF_LIST() 460 } 461 }; 462 463 static const VMStateDescription vmstate_cadence_ttc = { 464 .name = "cadence_TTC", 465 .version_id = 1, 466 .minimum_version_id = 1, 467 .fields = (VMStateField[]) { 468 VMSTATE_STRUCT_ARRAY(timer, CadenceTTCState, 3, 0, 469 vmstate_cadence_timer, 470 CadenceTimerState), 471 VMSTATE_END_OF_LIST() 472 } 473 }; 474 475 static void cadence_ttc_class_init(ObjectClass *klass, void *data) 476 { 477 DeviceClass *dc = DEVICE_CLASS(klass); 478 479 dc->vmsd = &vmstate_cadence_ttc; 480 } 481 482 static const TypeInfo cadence_ttc_info = { 483 .name = TYPE_CADENCE_TTC, 484 .parent = TYPE_SYS_BUS_DEVICE, 485 .instance_size = sizeof(CadenceTTCState), 486 .instance_init = cadence_ttc_init, 487 .class_init = cadence_ttc_class_init, 488 }; 489 490 static void cadence_ttc_register_types(void) 491 { 492 type_register_static(&cadence_ttc_info); 493 } 494 495 type_init(cadence_ttc_register_types) 496