1 /* 2 * Xilinx Zynq cadence TTC model 3 * 4 * Copyright (c) 2011 Xilinx Inc. 5 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com) 6 * Copyright (c) 2012 PetaLogix Pty Ltd. 7 * Written By Haibing Ma 8 * M. Habib 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License 12 * as published by the Free Software Foundation; either version 13 * 2 of the License, or (at your option) any later version. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "hw/irq.h" 21 #include "hw/sysbus.h" 22 #include "migration/vmstate.h" 23 #include "qemu/module.h" 24 #include "qemu/timer.h" 25 #include "qom/object.h" 26 27 #ifdef CADENCE_TTC_ERR_DEBUG 28 #define DB_PRINT(...) do { \ 29 fprintf(stderr, ": %s: ", __func__); \ 30 fprintf(stderr, ## __VA_ARGS__); \ 31 } while (0) 32 #else 33 #define DB_PRINT(...) 34 #endif 35 36 #define COUNTER_INTR_IV 0x00000001 37 #define COUNTER_INTR_M1 0x00000002 38 #define COUNTER_INTR_M2 0x00000004 39 #define COUNTER_INTR_M3 0x00000008 40 #define COUNTER_INTR_OV 0x00000010 41 #define COUNTER_INTR_EV 0x00000020 42 43 #define COUNTER_CTRL_DIS 0x00000001 44 #define COUNTER_CTRL_INT 0x00000002 45 #define COUNTER_CTRL_DEC 0x00000004 46 #define COUNTER_CTRL_MATCH 0x00000008 47 #define COUNTER_CTRL_RST 0x00000010 48 49 #define CLOCK_CTRL_PS_EN 0x00000001 50 #define CLOCK_CTRL_PS_V 0x0000001e 51 52 typedef struct { 53 QEMUTimer *timer; 54 int freq; 55 56 uint32_t reg_clock; 57 uint32_t reg_count; 58 uint32_t reg_value; 59 uint16_t reg_interval; 60 uint16_t reg_match[3]; 61 uint32_t reg_intr; 62 uint32_t reg_intr_en; 63 uint32_t reg_event_ctrl; 64 uint32_t reg_event; 65 66 uint64_t cpu_time; 67 unsigned int cpu_time_valid; 68 69 qemu_irq irq; 70 } CadenceTimerState; 71 72 #define TYPE_CADENCE_TTC "cadence_ttc" 73 typedef struct CadenceTTCState CadenceTTCState; 74 DECLARE_INSTANCE_CHECKER(CadenceTTCState, CADENCE_TTC, 75 TYPE_CADENCE_TTC) 76 77 struct CadenceTTCState { 78 SysBusDevice parent_obj; 79 80 MemoryRegion iomem; 81 CadenceTimerState timer[3]; 82 }; 83 84 static void cadence_timer_update(CadenceTimerState *s) 85 { 86 qemu_set_irq(s->irq, !!(s->reg_intr & s->reg_intr_en)); 87 } 88 89 static CadenceTimerState *cadence_timer_from_addr(void *opaque, 90 hwaddr offset) 91 { 92 unsigned int index; 93 CadenceTTCState *s = (CadenceTTCState *)opaque; 94 95 index = (offset >> 2) % 3; 96 97 return &s->timer[index]; 98 } 99 100 static uint64_t cadence_timer_get_ns(CadenceTimerState *s, uint64_t timer_steps) 101 { 102 /* timer_steps has max value of 0x100000000. double check it 103 * (or overflow can happen below) */ 104 assert(timer_steps <= 1ULL << 32); 105 106 uint64_t r = timer_steps * 1000000000ULL; 107 if (s->reg_clock & CLOCK_CTRL_PS_EN) { 108 r >>= 16 - (((s->reg_clock & CLOCK_CTRL_PS_V) >> 1) + 1); 109 } else { 110 r >>= 16; 111 } 112 r /= (uint64_t)s->freq; 113 return r; 114 } 115 116 static uint64_t cadence_timer_get_steps(CadenceTimerState *s, uint64_t ns) 117 { 118 uint64_t to_divide = 1000000000ULL; 119 120 uint64_t r = ns; 121 /* for very large intervals (> 8s) do some division first to stop 122 * overflow (costs some prescision) */ 123 while (r >= 8ULL << 30 && to_divide > 1) { 124 r /= 1000; 125 to_divide /= 1000; 126 } 127 r <<= 16; 128 /* keep early-dividing as needed */ 129 while (r >= 8ULL << 30 && to_divide > 1) { 130 r /= 1000; 131 to_divide /= 1000; 132 } 133 r *= (uint64_t)s->freq; 134 if (s->reg_clock & CLOCK_CTRL_PS_EN) { 135 r /= 1 << (((s->reg_clock & CLOCK_CTRL_PS_V) >> 1) + 1); 136 } 137 138 r /= to_divide; 139 return r; 140 } 141 142 /* determine if x is in between a and b, exclusive of a, inclusive of b */ 143 144 static inline int64_t is_between(int64_t x, int64_t a, int64_t b) 145 { 146 if (a < b) { 147 return x > a && x <= b; 148 } 149 return x < a && x >= b; 150 } 151 152 static void cadence_timer_run(CadenceTimerState *s) 153 { 154 int i; 155 int64_t event_interval, next_value; 156 157 assert(s->cpu_time_valid); /* cadence_timer_sync must be called first */ 158 159 if (s->reg_count & COUNTER_CTRL_DIS) { 160 s->cpu_time_valid = 0; 161 return; 162 } 163 164 { /* figure out what's going to happen next (rollover or match) */ 165 int64_t interval = (uint64_t)((s->reg_count & COUNTER_CTRL_INT) ? 166 (int64_t)s->reg_interval + 1 : 0x10000ULL) << 16; 167 next_value = (s->reg_count & COUNTER_CTRL_DEC) ? -1ULL : interval; 168 for (i = 0; i < 3; ++i) { 169 int64_t cand = (uint64_t)s->reg_match[i] << 16; 170 if (is_between(cand, (uint64_t)s->reg_value, next_value)) { 171 next_value = cand; 172 } 173 } 174 } 175 DB_PRINT("next timer event value: %09llx\n", 176 (unsigned long long)next_value); 177 178 event_interval = next_value - (int64_t)s->reg_value; 179 event_interval = (event_interval < 0) ? -event_interval : event_interval; 180 181 timer_mod(s->timer, s->cpu_time + 182 cadence_timer_get_ns(s, event_interval)); 183 } 184 185 static void cadence_timer_sync(CadenceTimerState *s) 186 { 187 int i; 188 int64_t r, x; 189 int64_t interval = ((s->reg_count & COUNTER_CTRL_INT) ? 190 (int64_t)s->reg_interval + 1 : 0x10000ULL) << 16; 191 uint64_t old_time = s->cpu_time; 192 193 s->cpu_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 194 DB_PRINT("cpu time: %lld ns\n", (long long)old_time); 195 196 if (!s->cpu_time_valid || old_time == s->cpu_time) { 197 s->cpu_time_valid = 1; 198 return; 199 } 200 201 r = (int64_t)cadence_timer_get_steps(s, s->cpu_time - old_time); 202 x = (int64_t)s->reg_value + ((s->reg_count & COUNTER_CTRL_DEC) ? -r : r); 203 204 for (i = 0; i < 3; ++i) { 205 int64_t m = (int64_t)s->reg_match[i] << 16; 206 if (m > interval) { 207 continue; 208 } 209 /* check to see if match event has occurred. check m +/- interval 210 * to account for match events in wrap around cases */ 211 if (is_between(m, s->reg_value, x) || 212 is_between(m + interval, s->reg_value, x) || 213 is_between(m - interval, s->reg_value, x)) { 214 s->reg_intr |= (2 << i); 215 } 216 } 217 if ((x < 0) || (x >= interval)) { 218 s->reg_intr |= (s->reg_count & COUNTER_CTRL_INT) ? 219 COUNTER_INTR_IV : COUNTER_INTR_OV; 220 } 221 while (x < 0) { 222 x += interval; 223 } 224 s->reg_value = (uint32_t)(x % interval); 225 cadence_timer_update(s); 226 } 227 228 static void cadence_timer_tick(void *opaque) 229 { 230 CadenceTimerState *s = opaque; 231 232 DB_PRINT("\n"); 233 cadence_timer_sync(s); 234 cadence_timer_run(s); 235 } 236 237 static uint32_t cadence_ttc_read_imp(void *opaque, hwaddr offset) 238 { 239 CadenceTimerState *s = cadence_timer_from_addr(opaque, offset); 240 uint32_t value; 241 242 cadence_timer_sync(s); 243 cadence_timer_run(s); 244 245 switch (offset) { 246 case 0x00: /* clock control */ 247 case 0x04: 248 case 0x08: 249 return s->reg_clock; 250 251 case 0x0c: /* counter control */ 252 case 0x10: 253 case 0x14: 254 return s->reg_count; 255 256 case 0x18: /* counter value */ 257 case 0x1c: 258 case 0x20: 259 return (uint16_t)(s->reg_value >> 16); 260 261 case 0x24: /* reg_interval counter */ 262 case 0x28: 263 case 0x2c: 264 return s->reg_interval; 265 266 case 0x30: /* match 1 counter */ 267 case 0x34: 268 case 0x38: 269 return s->reg_match[0]; 270 271 case 0x3c: /* match 2 counter */ 272 case 0x40: 273 case 0x44: 274 return s->reg_match[1]; 275 276 case 0x48: /* match 3 counter */ 277 case 0x4c: 278 case 0x50: 279 return s->reg_match[2]; 280 281 case 0x54: /* interrupt register */ 282 case 0x58: 283 case 0x5c: 284 /* cleared after read */ 285 value = s->reg_intr; 286 s->reg_intr = 0; 287 cadence_timer_update(s); 288 return value; 289 290 case 0x60: /* interrupt enable */ 291 case 0x64: 292 case 0x68: 293 return s->reg_intr_en; 294 295 case 0x6c: 296 case 0x70: 297 case 0x74: 298 return s->reg_event_ctrl; 299 300 case 0x78: 301 case 0x7c: 302 case 0x80: 303 return s->reg_event; 304 305 default: 306 return 0; 307 } 308 } 309 310 static uint64_t cadence_ttc_read(void *opaque, hwaddr offset, 311 unsigned size) 312 { 313 uint32_t ret = cadence_ttc_read_imp(opaque, offset); 314 315 DB_PRINT("addr: %08x data: %08x\n", (unsigned)offset, (unsigned)ret); 316 return ret; 317 } 318 319 static void cadence_ttc_write(void *opaque, hwaddr offset, 320 uint64_t value, unsigned size) 321 { 322 CadenceTimerState *s = cadence_timer_from_addr(opaque, offset); 323 324 DB_PRINT("addr: %08x data %08x\n", (unsigned)offset, (unsigned)value); 325 326 cadence_timer_sync(s); 327 328 switch (offset) { 329 case 0x00: /* clock control */ 330 case 0x04: 331 case 0x08: 332 s->reg_clock = value & 0x3F; 333 break; 334 335 case 0x0c: /* counter control */ 336 case 0x10: 337 case 0x14: 338 if (value & COUNTER_CTRL_RST) { 339 s->reg_value = 0; 340 } 341 s->reg_count = value & 0x3f & ~COUNTER_CTRL_RST; 342 break; 343 344 case 0x24: /* interval register */ 345 case 0x28: 346 case 0x2c: 347 s->reg_interval = value & 0xffff; 348 break; 349 350 case 0x30: /* match register */ 351 case 0x34: 352 case 0x38: 353 s->reg_match[0] = value & 0xffff; 354 break; 355 356 case 0x3c: /* match register */ 357 case 0x40: 358 case 0x44: 359 s->reg_match[1] = value & 0xffff; 360 break; 361 362 case 0x48: /* match register */ 363 case 0x4c: 364 case 0x50: 365 s->reg_match[2] = value & 0xffff; 366 break; 367 368 case 0x54: /* interrupt register */ 369 case 0x58: 370 case 0x5c: 371 break; 372 373 case 0x60: /* interrupt enable */ 374 case 0x64: 375 case 0x68: 376 s->reg_intr_en = value & 0x3f; 377 break; 378 379 case 0x6c: /* event control */ 380 case 0x70: 381 case 0x74: 382 s->reg_event_ctrl = value & 0x07; 383 break; 384 385 default: 386 return; 387 } 388 389 cadence_timer_run(s); 390 cadence_timer_update(s); 391 } 392 393 static const MemoryRegionOps cadence_ttc_ops = { 394 .read = cadence_ttc_read, 395 .write = cadence_ttc_write, 396 .endianness = DEVICE_NATIVE_ENDIAN, 397 }; 398 399 static void cadence_timer_reset(CadenceTimerState *s) 400 { 401 s->reg_count = 0x21; 402 } 403 404 static void cadence_timer_init(uint32_t freq, CadenceTimerState *s) 405 { 406 memset(s, 0, sizeof(CadenceTimerState)); 407 s->freq = freq; 408 409 cadence_timer_reset(s); 410 411 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cadence_timer_tick, s); 412 } 413 414 static void cadence_ttc_init(Object *obj) 415 { 416 CadenceTTCState *s = CADENCE_TTC(obj); 417 418 memory_region_init_io(&s->iomem, obj, &cadence_ttc_ops, s, 419 "timer", 0x1000); 420 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); 421 } 422 423 static void cadence_ttc_realize(DeviceState *dev, Error **errp) 424 { 425 CadenceTTCState *s = CADENCE_TTC(dev); 426 int i; 427 428 for (i = 0; i < 3; ++i) { 429 cadence_timer_init(133000000, &s->timer[i]); 430 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->timer[i].irq); 431 } 432 } 433 434 static int cadence_timer_pre_save(void *opaque) 435 { 436 cadence_timer_sync((CadenceTimerState *)opaque); 437 438 return 0; 439 } 440 441 static int cadence_timer_post_load(void *opaque, int version_id) 442 { 443 CadenceTimerState *s = opaque; 444 445 s->cpu_time_valid = 0; 446 cadence_timer_sync(s); 447 cadence_timer_run(s); 448 cadence_timer_update(s); 449 return 0; 450 } 451 452 static const VMStateDescription vmstate_cadence_timer = { 453 .name = "cadence_timer", 454 .version_id = 1, 455 .minimum_version_id = 1, 456 .pre_save = cadence_timer_pre_save, 457 .post_load = cadence_timer_post_load, 458 .fields = (VMStateField[]) { 459 VMSTATE_UINT32(reg_clock, CadenceTimerState), 460 VMSTATE_UINT32(reg_count, CadenceTimerState), 461 VMSTATE_UINT32(reg_value, CadenceTimerState), 462 VMSTATE_UINT16(reg_interval, CadenceTimerState), 463 VMSTATE_UINT16_ARRAY(reg_match, CadenceTimerState, 3), 464 VMSTATE_UINT32(reg_intr, CadenceTimerState), 465 VMSTATE_UINT32(reg_intr_en, CadenceTimerState), 466 VMSTATE_UINT32(reg_event_ctrl, CadenceTimerState), 467 VMSTATE_UINT32(reg_event, CadenceTimerState), 468 VMSTATE_END_OF_LIST() 469 } 470 }; 471 472 static const VMStateDescription vmstate_cadence_ttc = { 473 .name = "cadence_TTC", 474 .version_id = 1, 475 .minimum_version_id = 1, 476 .fields = (VMStateField[]) { 477 VMSTATE_STRUCT_ARRAY(timer, CadenceTTCState, 3, 0, 478 vmstate_cadence_timer, 479 CadenceTimerState), 480 VMSTATE_END_OF_LIST() 481 } 482 }; 483 484 static void cadence_ttc_class_init(ObjectClass *klass, void *data) 485 { 486 DeviceClass *dc = DEVICE_CLASS(klass); 487 488 dc->vmsd = &vmstate_cadence_ttc; 489 dc->realize = cadence_ttc_realize; 490 } 491 492 static const TypeInfo cadence_ttc_info = { 493 .name = TYPE_CADENCE_TTC, 494 .parent = TYPE_SYS_BUS_DEVICE, 495 .instance_size = sizeof(CadenceTTCState), 496 .instance_init = cadence_ttc_init, 497 .class_init = cadence_ttc_class_init, 498 }; 499 500 static void cadence_ttc_register_types(void) 501 { 502 type_register_static(&cadence_ttc_info); 503 } 504 505 type_init(cadence_ttc_register_types) 506